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| exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? preliminary XRT72L13 m13 multiplexer/clear channel ds3 framer ic april 2001 rev. p1.0.6 general description the XRT72L13 is a fully integrated, low power, multi- plexer/framer ic which performs multiplexing/de- mutiplexing of 28 ds1or 21 e1 signals into/from a ds3 signal with either m13 or c-bit parity frame for- mat, performs clear channel ds3 framing, and sup- ports high speed hdlc/lapd data linking. the XRT72L13 also contains m12 and m23 bit-inter- leaving multiplexing/demultiplexing functions with necessary stuffing and destuffing control. seven in- ternal ds2/g.747 framers are included to support mux/demux purposes. the XRT72L13 contains an integral ds3 framer which provides clear channel ds3 framing and er- ror accumulation in accordance with ansi/itu-t specifications. the XRT72L13 provides the intelligent functions of ds3/ds2 mode control, signaling control, error and alarm reporting and handles the hdlc/lapd data link through internal registers accessible via an 8-bit parallel, memory mapped, processor interface. features ? a fully integrated device that supports: multiplexing/demultiplexing mode clear channel ds3 framer mode high speed hdlc controller mode ? supports multiple loop-back modes ? smooths gapped clock signals ? supports intel or motorola pio p interfaces ? available in a 208 pin pqfp package ? single 3.3v power supply ? 5v tolerant i/o ? operates over the industrial temperature range applications ? m13 multiplexer/demuliplexer applications. ? frame relay systems ? digital access and cross connect systems ? local digital switch ? add/drop multiplexers ? ds3 data/channel service units. ? test equipment f igure 1. b lock d iagram of the XRT72L13 m ultiplexer /f ramer txhdlc controller txhdlc controller rxds1[0:27] rxclk[0:27] m23 demux m23 demux m23 mux m23 mux m12 mux m12 mux clear channel ds3 framer clear channel ds3 framer 32/64 bit de-jitter fifo rxhdlc controller rxhdlc controller rxhdlc[0:7] rxhdlcclk rxidle valid-fcs txds1[0:27] txclk[0:27] txhdlc[0:7] txhdlcclk send_fcs microprocessor interface microprocessor interface txpos txneg txline clk rxpos rxneg rxline clk ds2 or g.747 data streams m12 demux
XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 2 pin out of the 72l13 framer ic rxds1data_4/rxhdlc_data_4 rxds1clk_4 rxds1data_3/rxhdlc_data_3 rxds1clk_3/rxidle rxds1data_2/rxhdlc_data_2 rxds1clk_2/validfcs rxds1data_1/rxhdlc_data_1 rxds1clk_1/rxhdlcclk rxds1data_0/rxhdlc_data_0 vdd rxds1clk_0/txhdlcclk resetb a0 d0 a1 intb* d1 a2 moto gnd d2 a3 rdy_dtck d3 a4 ale_as d4 a5 csb d5 a6 rdb_ds d6 a7 vdd wrb_rw d7 a8 gnd (test mode) nibbleintf txds1data_27/txhdlcdata_7 txds1clk_27/send_msg txds1data_26/txhdlcdata_6 txds1clk_26/send_fcs txds1data_25/txhdlcdata_5 gnd txds1clk_25 txds1data_24/txhdlcdata_4 txds1clk_24 txds1data_23/txhdlcdata_3 txds1clk_23 txds1data_22/txhdlcdata_2 rxds1data_26 rxds1clk_26 rxds1data_25 rxds1clk_25 rxds1data_24 rxds1clk_24 rxds1data_23 rxds1clk_23 rxds1data_22 rxds1clk_22 vdd rxds1data_21 rxds1clk_21 rxds1data_20 rxds1clk_20 rxds1data_19 rxds1clk_19 rxds1data_18 rxds1clk_18 rxds1data_17 rxds1clk_17 rxds1data_16 rxds1clk_16 rxds1data_15 tck tms tdi tdo gnd rxds1clk_15 rxds1data_14 rxds1clk_14 rxds1data_13 rxds1clk_13 rxds1data_12 rxds1clk_12 rxds1data_11 rxds1clk_11 vdd rxds1data_10 rxds1clk_10 rxds1data_9 rxds1clk_9 rxds1data_8 rxds1clk_8 rxds1data_7/rxhdlc_data_7 rxds1clk_7 rxds1data_6/rxhdlc_data_6 gnd rxds1clk_6 rxds1data_5/rxhdlc_data_5 rxds1clk_5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 lead pqfp txframe txinclk txnibframe txohind/txplclkenb txnibclk txnib_0/txser txnib_1 vdd txnib_2 txnib_3 txohins txaisen txohframe txohenable txohclk txoh txneg txpos txlineclk reqb taos gnd encodis txlev rloop lloop dmo rlol extlos vdd rxvcoup rxvcodown rxlineclk rxpos rxneg rxoh rxohenable rxohclk rxohframe rxlos rxnib_3/rxred rxnib_2/rxais rxnib_1/rxoof gnd rxnib_0/rxser rxoutclk rxohind/rxplclkenb rxclk rxframe rxinclk rxds1data_27 rxds1clk_27 txframeref ds2outclk ds2inclk txds1clk_0 txds1data_0 txds1clk_1 txds1data_1 txds1clk_2 txds1data_2 txds1clk_3 gnd txds1data_3 txds1clk_4 txds1data_4 txds1clk_5 txds1data_5 txds1clk_6 txds1data_6 txds1clk_7 vdd txds1data_7 txds1clk_8 txds1data_8 txds1clk_9 txds1data_9 txds1clk_10 txds1data_10 txds1clk_11 gnd txds1data_11 txds1clk_12 txds1data_12 txds1clk_13 txds1data_13 txds1clk_14 txds1data_14 txds1clk_15 txds1data_15 vdd txds1clk_16 txds1data_16 txds1clk_17 txds1data_17 txds1clk_18 txds1data_18 txds1clk_19 txds1data_19 txds1clk_20 txds1data_20/txhdlcdata_0 txds1clk_21 txds1data_21/txhdlcdata_1 txds1clk_22 ordering information p art #p ackage o perating t emperature XRT72L13iq 208 pin pqfp -40c to +85c ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 i table of contents general description .................................................................................................. 1 features ...................................................................................................................... .......................... 1 applications .................................................................................................................. ....................... 1 figure 1. block diagram of the XRT72L13 multiplexer/framer ........................................................... 1 p in out of the 72 l 13 framer ic ............................................................................................................... 2 ordering information .......................................................................................................... ............ 2 electrical characteristics ................................................................................. 39 a bsolute m aximums .............................................................................................................................. .. 39 dc e lectrical c haracteristics ............................................................................................................ 39 ac e lectrical c haracteristics ............................................................................................................ 39 ac e lectrical c haracteristics (c ont .) ............................................................................................... 40 figure 2. timing diagram for transmit payload input interface, when the XRT72L13 is operating in both the ds3 and loop-timing modes ................................................................................ 43 figure 3. timing diagram for the transmit payload input interface, when the XRT72L13 is operating in both the ds3/serial and local-timing modes ................................................................ 44 figure 4. timing diagram for the transmit payload data input interface, when the XRT72L13 is op- erating in both the ds3/nibble and looped-timing modes .............................................. 44 figure 5. timing diagram for the transmit payload data input interface, when the XRT72L13 is op- erating in the ds3/nibble and local-timing modes ........................................................... 45 figure 6. timing diagram for the transmit overhead data input interface (method 1 access) .... 45 figure 7. timing diagram for the transmit overhead data input interface (method 2 access) .... 46 figure 8. transmit liu interface timing - framer is configured to update "txpos" and "txneg" on the rising edge of "txlineclk" ............................................................................................. 46 figure 9. transmit liu interface timing - framer is configured to update "txpos" and "txneg" on the falling edge of "txlineclk" ............................................................................................ 47 figure 10. receive liu interface timing - framer is configured to sample "rxpos" and "rxneg" on the rising edge of "rxlineclk" ....................................................................................... 47 figure 11. receiver liu interface timing - framer is configured to sample "rxpos" and "rxneg" on the falling edge of "rxlineclk" ...................................................................................... 48 figure 12. receive payload data output interface timing (serial mode operation) ...................... 48 figure 13. receive payload data output interface timing (nibble mode operation) ..................... 49 figure 14. receive overhead data output interface timing (method 1 - using rxohclk) ............ 49 figure 15. receive overhead data output interface timing (method 2 - using rxohenable) ..... 50 figure 16. microprocessor interface timing - intel type programmed i/o read operations ........ 50 figure 17. microprocessor interface timing - intel type programmed i/o write operations ....... 51 figure 18. microprocessor interface timing - intel type read burst access operation ............... 51 figure 19. microprocessor interface timing - intel type write burst access operation .............. 52 figure 20. microprocessor interface timing - motorola type programmed i/o read operation .. 52 figure 21. microprocessor interface timing - motorola type programmed i/o write operation .. 53 figure 22. microprocessor interface timing - motorola type read burst access operation ....... 53 figure 23. microprocessor interface timing - motorola type write burst access operation ....... 53 figure 24. microprocessor interface timing - resetb* pulse width ................................................ 53 1.0 system description ........................................................................................................ ........... 54 figure 25. block diagram of the XRT72L13 m13 multiplexer/framer ic .......................................... 54 1.1 XRT72L13 operation while in the multiplexer/de-multiplexer mode ................................. 54 figure 26. functional block diagram of the XRT72L13 m13 multiplexer/framer ic, while operating in the "multiplexer/de-multiplexer mode ............................................................................. 55 1.1.1 in the transmit direction ............................................................................................... ....................... 55 1.1.2 in the receive direction ................................................................................................ ....................... 56 1.1.3 diagnostic resources available for mux/demux mode ..................................................................... 5 6 figure 27. illustration of the XRT72L13 operating in the "ds1/e1 tributary loop-back mode ..... 57 figure 28. illustration of the XRT72L13 operating in the "ds2/itu-t g.747 tributary loop-back XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary ii mode .......................................................................................................................... ............. 58 1.2 XRT72L13 operation while in the "clear channel ds3 framer mode" ................................ 58 figure 29. functional block diagram of the XRT72L13 m13 multiplexer/framer ic, while operating in the clear channel ds3 framer mode ........................................................................... 59 1.2.1 operation of the XRT72L13 while in the "clear channel ds3 framer mode" ..................................... 59 figure 30. illustration of the XRT72L13 m13 multiplexer/framer operating in the "clear channel ds3 framer local loop-back" mode ........................................................................................... 60 figure 31. illustration of the XRT72L13 m13 multiplexer/framer operating in the "clear channel ds3 framer remote loop-back" mode ....................................................................................... 61 1.3 XRT72L13 operation while in the "high speed hdlc controller" mode ............................. 61 figure 32. illustration of the XRT72L13 m13 multiplexer/framer ic, when it has been configured to operate in the "high speed hdlc controller" mode ......................................................... 62 2.0 the microprocessor interface block ........................................................................................ ...... 62 figure 33. simple block diagram of the microprocessor interface block, within the framer ic .. 63 2.1 t he m icroprocessor i nterface b lock s ignal ........................................................................................... 63 t able 1: d escription of the m icroprocessor i nterface s ignals that exhibit constant roles in both the "i ntel " and "m otorola " m odes ...................................................................................... 64 t able 2: p in d escription of m icroprocessor i nterface s ignals - w hile the m icroprocessor i nter - face is o perating in the i ntel m ode ..................................................................................... 64 t able 3: p in d escription of the m icroprocessor i nterface s ignals while the m icroprocessor i n - terface is operating in the m otorola m ode ...................................................................... 65 2.2 i nterfacing the xrt 72l13 ds3 f ramer to the l ocal c/p over via the m icroprocessor i nterface b lock 65 2.2.1 interfacing the xrt 72l13 ds3 framer to the microprocessor over an 8 bit wide bi-directional data bus 65 2.2.2 data access modes ....................................................................................................... ...................... 66 figure 34. behavior of microprocessor interface signals during an "intel-type" programmed i/o read operation ................................................................................................................ ...... 67 figure 35. behavior of the microprocessor interface signals, during an "intel-type" programmed i/ o write operation ............................................................................................................. ..... 68 figure 36. illustration of the behavior of microprocessor interface signals, during a "motorola-type" programmed i/o read operation ......................................................................................... 69 figure 37. illustration of the behavior of the microprocessor interface signal, during a "motorola- type" programmed i/o write operation ............................................................................... 70 figure 38. behavior of the microprocessor interface signals, during the "initial" read operation of a burst cycle (intel type processor) ................................................................................... 72 figure 39. behavior of the microprocessor interface signals, during subsequent "read" operations within the burst i/o cycle .................................................................................................... . 73 figure 40. behavior of the microprocessor interface signals, during the "initial" write operation of a burst cycle (intel-type processor) .................................................................................... 74 figure 41. behavior of the microprocessor interface signals, during subsequent "write" operations within the burst i/o cycle .................................................................................................... . 75 figure 42. behavior of the microprocessor interface signals, during the "initial" read operation of a burst cycle (motorola type processor) ........................................................................... 76 figure 43. behavior the microprocessor interface signals, during subsequent "read" operations within the burst i/o cycle (motorola-type c/p) ............................................................... 77 figure 44. behavior of the microprocessor interface signals, during the "initial" write operation of a burst cycle (motorola-type processor) ............................................................................ 78 figure 45. behavior of the microprocessor interface signals, during subsequent "write" operations with the burst i/o cycle (motorola-type c/p) .................................................................. 79 2.3 o n -c hip r egister o rganization .................................................................................................................. 79 2.3.1 framer register addressing .............................................................................................. .................. 79 2.3.2 m13 mux/framer register description ..................................................................................... ............ 79 t able 4: r egister a ddress m ap ........................................................................................................... 80 o perating m ode r egister (a ddress = 0 x 00) ........................................................................................ 83 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 iii i/o c ontrol r egister (a ddress = 0 x 01) ............................................................................................... 84 p art n umber r egister (a ddress = 0 x 02) ............................................................................................. 85 v ersion n umber r egister (a ddress = 0 x 03) ........................................................................................ 85 b lock i nterrupt enable r egister (a ddress = 0 x 04) .......................................................................... 86 b lock i nterrupt s tatus r egister (a ddress = 0 x 05) ......................................................................... 86 rx f ifo control r egister (a ddress = 0 x 06) ........................................................................................ 87 m23 c onfiguration r egister (a ddress = 0 x 07) ................................................................................. 87 t able 5: ......................................................................................................................... ........................ 89 m23 t x ds2 ais r egister (a ddress = 0 x 08) ....................................................................................... 89 m23 request loopback r egister (a ddress = 0 x 09) ........................................................................... 90 m23 l oopback activation r egister (a ddress = 0 x 0a) ....................................................................... 90 m23 r x ds2 ais r egister (a ddress = 0 x 0b) ...................................................................................... 90 ds3 t est r egister (a ddress = 0 x 0c) .................................................................................................. 91 rx ds 3 configuration and status r egister (a ddress = 0 x 10) ........................................................... 92 rx ds 3 status r egister (a ddress = 0 x 11) ........................................................................................... 93 rx ds 3 interrupt enable r egister (a ddress = 0 x 12) ......................................................................... 94 r x d s 3 i nterrupt s tatus r egister (a ddress = 0 x 13) ........................................................................ 95 r x d s 3 sync detect r egister (a ddress = 0 x 14) ................................................................................. 96 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) .................................................. 97 r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) .............................................................................. 97 r x ds3 lapd s tatus r egister (a ddress = 0 x 19) ................................................................................ 98 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................... 99 m12 ds2 # 2 c onfiguration r egister (a ddress = 0 x 1b) .................................................................. 100 m12 ds2 # 3 c onfiguration r egister (a ddress = 0 x 1c) .................................................................. 100 m12 ds2 # 4 c onfiguration r egister (a ddress = 0 x 1d) .................................................................. 101 m12 ds2 # 5 c onfiguration r egister (a ddress = 0 x 1e) .................................................................. 102 m12 ds2 # 6 c onfiguration r egister (a ddress = 0 x 1f) .................................................................. 103 m12 ds2 # 7 c onfiguration r egister (a ddress = 0 x 20) .................................................................. 104 m12 ds2 # 1 a is r egister (a ddress = 0 x 21) ...................................................................................... 105 m12 ds2 # 2 a is r egister (a ddress = 0 x 22) ...................................................................................... 106 m12 ds2 # 3 a is r egister (a ddress = 0 x 23) ...................................................................................... 107 m12 ds2 # 4 a is r egister (a ddress = 0 x 24) ...................................................................................... 108 m12 ds2 # 5 a is r egister (a ddress = 0 x 25) ...................................................................................... 109 m12 ds2 # 6 a is r egister (a ddress = 0 x 26) ...................................................................................... 110 m12 ds2 # 7 a is r egister (a ddress = 0 x 27) ...................................................................................... 111 m12 ds2 # 1 l oop - back r egister (a ddress = 0 x 28) ......................................................................... 112 m12 ds2 # 2 l oop - back r egister (a ddress = 0 x 29) ......................................................................... 113 m12 ds2 # 3 l oop - back r egister (a ddress = 0 x 2a) ........................................................................ 114 m12 ds2 # 4 l oop - back r egister (a ddress = 0 x 2b) ........................................................................ 116 m12 ds2 # 5 l oop - back r egister (a ddress = 0 x 2c) ........................................................................ 117 m12 ds2 # 6 l oop - back r egister (a ddress = 0 x 2d) ........................................................................ 118 m12 ds2 # 7 l oop - back r egister (a ddress = 0 x 28) ......................................................................... 119 t x ds3 c onfiguration r egister (a ddress = 0 x 30) ........................................................................... 120 t ransmit ds3 c onfiguration & s tatus r egister (a ddress = 0 x 31) ................................................ 121 t x ds3 feac r egiser (a ddress = 0 x 32) ............................................................................................ 122 t x ds3 lapd c onfiguration r egister (a ddress = 0 x 33) .................................................................. 122 t x ds3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 123 t x ds3 m-b it m ask r egister (a ddress = 0 x 35) .................................................................................. 124 t x ds3 f-b it m ask r egister - 1 (a ddress = 0 x 36) ............................................................................. 124 t x ds3 f-b it m ask r egister - 2 (a ddress = 0 x 37) .............................................................................. 125 t x ds3 f-b it m ask r egister - 3 (a ddress = 0 x 38) ............................................................................. 125 t x ds3 f-b it m ask r egister - 4 (a ddress = 0 x 39) .............................................................................. 125 ds2 # 1 f ramer c onfiguration register (a ddress = 0 x 3a) ............................................................ 126 ds2 # 2 f ramer c onfiguration register (a ddress = 0 x 3b) ............................................................ 127 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary iv ds2 # 3 f ramer c onfiguration register (a ddress = 0 x 3c) ............................................................ 128 ds2 # 4 f ramer c onfiguration register (a ddress = 0 x 3d) ............................................................ 129 ds2 # 5 f ramer c onfiguration register (a ddress = 0 x 3e) ............................................................ 130 ds2 # 6 f ramer c onfiguration register (a ddress = 0 x 3f) ............................................................. 131 ds2 # 7 f ramer c onfiguration register (a ddress = 0 x 40) ............................................................. 132 pmon lcv e vent c ount r egister - lsb (a ddress = 0 x 51) .............................................................. 133 pmon f raming b it e rror c ount r egister - msb (a ddress = 0 x 52) ............................................... 133 pmon f raming b it e rror c ount r egister - lsb (a ddress = 0 x 53) ................................................ 133 pmon p-b it e rror c ount r egister - msb (a ddress = 0 x 54) ........................................................... 134 pmon p-b it e rror c ount r egister - lsb (a ddress = 0 x 55) ............................................................ 134 pmon febe e vent c ount r egister - msb (a ddress = 0 x 56) ........................................................... 134 pmon febe e vent c ount r egister - lsb (a ddress = 0 x 57) ............................................................ 134 pmon cp-b it e rror c ount r egister - msb (a ddress = 0 x 58) ........................................................ 135 pmon cp-b it e rror c ount r egister - lsb (a ddress = 0 x 59) ......................................................... 135 pmon ds2 # 1 f raming b it e rror c ount register (a ddress = 0 x 5a) ............................................. 135 pmon ds2 # 2 f raming b it e rror c ount register (a ddress = 0 x 5 b ) ............................................. 135 pmon ds2 # 3 f raming b it e rror c ount register (a ddress = 0 x 5 c ) ............................................. 136 pmon ds2 # 4 f raming b it e rror c ount register (a ddress = 0 x 5 d ) ............................................. 136 pmon ds2 # 5 f raming b it e rror c ount register (a ddress = 0 x 5 e ) ............................................. 136 pmon ds2 # 6 f raming b it e rror c ount register (a ddress = 0 x 5f) ............................................. 136 pmon ds2 # 7 f raming b it e rror c ount register (a ddress = 0 x 60) ............................................. 137 pmon itu-t g.747 # 1 p- b it e rror c ount register (a ddress = 0 x 61) .......................................... 137 pmon itu-t g.747 # 2 p- b it e rror c ount register (a ddress = 0 x 62) .......................................... 137 pmon itu-t g.747 # 3 p- b it e rror c ount register (a ddress = 0 x 63) .......................................... 137 pmon itu-t g.747 # 4 p- b it e rror c ount register (a ddress = 0 x 64) .......................................... 138 pmon itu-t g.747 # 5 p- b it e rror c ount register (a ddress = 0 x 65) .......................................... 138 pmon itu-t g.747 # 6 p- b it e rror c ount register (a ddress = 0 x 66) .......................................... 138 pmon itu-t g.747 # 7 p- b it e rror c ount register (a ddress = 0 x 67) .......................................... 138 pmon h olding r egister (a ddress = 0 x 6c) ........................................................................................ 139 o ne second error status r egister (a ddress = 0 x 6d) ..................................................................... 139 lcv - o ne s econd a ccumulator r egister - msb (a ddress = 0 x 6e) ................................................ 139 lcv - o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 6f) ................................................. 140 p-b it e rrors - o ne s econd a ccumulator r egister - msb (a ddress = 0 x 70) ................................. 140 p- bit e rrors - o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 71) .................................. 140 cp-b it e rrors - o ne s econd a ccumulator r egister - msb (a ddress = 0 x 72) .............................. 140 c p - bit e rrors - o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 73) ................................ 141 l ine i nterface d rive r egister (a ddress = 0 x 80) ............................................................................... 141 l ine i nterface s can r egister (a ddress = 0 x 81) ................................................................................ 143 m23 rxds 2 loop - back request interrupt enable r egister (a ddress = 0 x 90) ................................. 144 m23 rxds 2 c hange in loop - back request s tate - interrupt r egister (a ddress = 0 x 91) ............. 144 m23 rxds 2 loop - back request s tatus - interrupt r egister (a ddress = 0 x 92) ............................ 146 m12 ds2 # 1 loop - back i nterrupt / interrupt e nable r egister (a ddress = 0 x 93) ........................... 147 m12 ds2 # 1 loop - back status r egister (a ddress = 0 x 94) .............................................................. 148 m12 ds2 # 2 loop - back i nterrupt / interrupt e nable r egister (a ddress = 0 x 95) ........................... 148 m12 ds2 # 1 loop - back status r egister (a ddress = 0 x 96) .............................................................. 149 m12 ds2 # 3 loop - back i nterrupt / interrupt e nable r egister (a ddress = 0 x 97) ........................... 150 m12 ds2 # 1 loop - back status r egister (a ddress = 0 x 98) .............................................................. 151 m12 ds2 # 4 loop - back i nterrupt / interrupt e nable r egister (a ddress = 0 x 99) ........................... 152 m12 ds2 # 1 loop - back status r egister (a ddress = 0 x 9a) .............................................................. 153 m12 ds2 # 5 loop - back i nterrupt / interrupt e nable r egister (a ddress = 0 x 9b) .......................... 153 m12 ds2 # 1 loop - back status r egister (a ddress = 0 x 9 c ) .............................................................. 154 m12 ds2 # 6 loop - back i nterrupt / interrupt e nable r egister (a ddress = 0 x 9 d ) .......................... 155 m12 ds2 # 1 loop - back status r egister (a ddress = 0 x 9 e ) .............................................................. 156 m12 ds2 # 7 loop - back i nterrupt / interrupt e nable r egister (a ddress = 0 x 9 f ) ........................... 157 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 v m12 ds2 # 1 loop - back status r egister (a ddress = 0 xa 0) .............................................................. 158 ds2 # 1 f ramer i nterrupt enable r egister (a ddress = 0 xa 1) ......................................................... 158 ds2 # 1 f ramer i nterrupt r egister (a ddress = 0 xa 2) ..................................................................... 159 ds2 # 1 f ramer s tatus r egister (a ddress = 0 xa 3) ......................................................................... 160 ds2 # 2 f ramer i nterrupt enable r egister (a ddress = 0 xa 4) ......................................................... 160 ds2 # 2 f ramer i nterrupt r egister (a ddress = 0 xa 5) ..................................................................... 161 ds2 # 2 f ramer s tatus r egister (a ddress = 0 xa 6) ......................................................................... 162 ds2 # 3 f ramer i nterrupt enable r egister (a ddress = 0 xa 7) ......................................................... 162 ds2 # 3 f ramer i nterrupt r egister (a ddress = 0 xa 8) .................................................................... 163 ds2 # 3 f ramer s tatus r egister (a ddress = 0 xa 9) ......................................................................... 164 ds2 # 4 f ramer i nterrupt enable r egister (a ddress = 0 xa a) ........................................................ 164 ds2 # 4 f ramer i nterrupt enable r egister (a ddress = 0 xa b) ........................................................ 165 ds2 # 4 f ramer s tatus r egister (a ddress = 0 xa c) ........................................................................ 166 ds2 # 5 f ramer i nterrupt enable r egister (a ddress = 0 xa d) ........................................................ 166 ds2 # 5 f ramer i nterrupt enable r egister (a ddress = 0 xa f) ........................................................ 167 ds2 # 5 f ramer s tatus r egister (a ddress = 0 xa f) ......................................................................... 168 ds2 # 6 f ramer i nterrupt enable r egister (a ddress = 0 x b0) ........................................................ 168 ds2 # 6 f ramer i nterrupt r egister (a ddress = 0 x b2) .................................................................... 169 ds2 # 6 f ramer s tatus r egister (a ddress = 0 xb 2) ......................................................................... 170 ds2 # 7 f ramer i nterrupt enable r egister (a ddress = 0 x b3) ........................................................ 170 ds2 # 7 f ramer i nterrupt r egister (a ddress = 0 x b5) .................................................................... 171 ds2 # 7 f ramer s tatus r egister (a ddress = 0 xb 5) ......................................................................... 171 3.0 the microprocessor interface block ........................................................................................ .... 173 figure 46. simple block diagram of the microprocessor interface block, within the framer ic 173 3.1 t he m icroprocessor i nterface b lock s ignal ......................................................................................... 173 t able 6: d escription of the m icroprocessor i nterface s ignals that exhibit constant roles in both the "i ntel " and "m otorola " m odes .................................................................................... 174 t able 7: p in d escription of m icroprocessor i nterface s ignals - w hile the m icroprocessor i nter - face is o perating in the i ntel m ode ................................................................................... 174 t able 8: p in d escription of the m icroprocessor i nterface s ignals while the m icroprocessor i n - terface is operating in the m otorola m ode .................................................................... 175 3.2 i nterfacing the XRT72L13 ds3 f ramer to the l ocal c/p over via the m icroprocessor i nterface b lock 175 3.2.1 interfacing the XRT72L13 ds3 framer to the microprocessor over an 8 bit wide bi-directional data bus 175 3.2.2 data access modes ....................................................................................................... .................... 176 figure 47. behavior of microprocessor interface signals during an "intel-type" programmed i/o read operation ................................................................................................................ ... 177 figure 48. behavior of the microprocessor interface signals, during an "intel-type" programmed i/ o write operation ............................................................................................................. .. 178 figure 49. illustration of the behavior of microprocessor interface signals, during a "motorola-type" programmed i/o read operation ...................................................................................... 179 figure 50. illustration of the behavior of the microprocessor interface signal, during a "motorola- type" programmed i/o write operation ............................................................................ 180 figure 51. behavior of the microprocessor interface signals, during the "initial" read operation of a burst cycle (intel type processor) ................................................................................ 182 figure 52. behavior of the microprocessor interface signals, during subsequent "read" operations within the burst i/o cycle ................................................................................................... 183 figure 53. behavior of the microprocessor interface signals, during the "initial" write operation of a burst cycle (intel-type processor) ................................................................................. 184 figure 54. behavior of the microprocessor interface signals, during subsequent "write" operations within the burst i/o cycle ................................................................................................... 185 figure 55. behavior of the microprocessor interface signals, during the "initial" read operation of a burst cycle (motorola type processor) ......................................................................... 186 figure 56. behavior the microprocessor interface signals, during subsequent "read" operations XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary vi within the burst i/o cycle (motorola-type c/p) ............................................................. 187 figure 57. behavior of the microprocessor interface signals, during the "initial" write operation of a burst cycle (motorola-type processor) .......................................................................... 188 figure 58. behavior of the microprocessor interface signals, during subsequent "write" operations with the burst i/o cycle (motorola-type c/p) ................................................................ 189 3.3 o n -c hip r egister o rganization ................................................................................................................ 189 3.3.1 framer register addressing .............................................................................................. ................ 189 3.3.2 m13 mux/framer register description ..................................................................................... .......... 189 o perating m ode r egister (a ddress = 0 x 00) ...................................................................................... 190 i/o c ontrol r egister (a ddress = 0 x 01) ............................................................................................. 191 p art n umber r egister (a ddress = 0 x 02) ........................................................................................... 192 v ersion n umber r egister (a ddress = 0 x 03) ...................................................................................... 192 b lock i nterrupt enable r egister (a ddress = 0 x 04) ........................................................................ 192 b lock i nterrupt s tatus r egister (a ddress = 0 x 05) ........................................................................ 193 rx f ifo control r egister (a ddress = 0 x 06) ...................................................................................... 194 m23 c onfiguration r egister (a ddress = 0 x 07) ................................................................................ 194 t able 9: ......................................................................................................................... ...................... 196 m23 t x ds2 ais r egister (a ddress = 0 x 08) ...................................................................................... 196 m23 request loopback r egister (a ddress = 0 x 09) .......................................................................... 197 m23 l oopback activation r egister (a ddress = 0 x 0a) ...................................................................... 197 m23 r x ds2 ais r egister (a ddress = 0 x 0b) ..................................................................................... 198 ds3 t est r egister (a ddress = 0 x 0c) ................................................................................................ 198 rx ds 3 configuration and status r egister (a ddress = 0 x 10) ......................................................... 199 rx ds 3 status r egister (a ddress = 0 x 11) ......................................................................................... 200 rx ds 3 interrupt enable r egister (a ddress = 0 x 12) ........................................................................ 201 r x d s 3 i nterrupt s tatus r egister (a ddress = 0 x 13) ...................................................................... 202 r x d s 3 sync detect r egister (a ddress = 0 x 14) ............................................................................... 203 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ................................................ 204 r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) ............................................................................ 205 r x ds3 lapd s tatus r egister (a ddress = 0 x 19) ............................................................................... 205 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 206 m12 ds2 # 2 c onfiguration r egister (a ddress = 0 x 1b) .................................................................. 207 m12 ds2 # 3 c onfiguration r egister (a ddress = 0 x 1c) .................................................................. 208 m12 ds2 # 4 c onfiguration r egister (a ddress = 0 x 1d) .................................................................. 209 m12 ds2 # 5 c onfiguration r egister (a ddress = 0 x 1e) .................................................................. 210 m12 ds2 # 6 c onfiguration r egister (a ddress = 0 x 1f) ................................................................... 211 m12 ds2 # 7 c onfiguration r egister (a ddress = 0 x 20) ................................................................... 212 m12 ds2 # 1 a is r egister (a ddress = 0 x 21) ...................................................................................... 213 m12 ds2 # 2 a is r egister (a ddress = 0 x 21) ...................................................................................... 214 t x ds3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 215 t ransmit ds3 c onfiguration & s tatus r egister (a ddress = 0 x 31) ................................................. 217 t x ds3 feac r egiser (a ddress = 0 x 32) ............................................................................................. 217 t x ds3 lapd c onfiguration r egister (a ddress = 0 x 33) .................................................................. 218 t x ds3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 218 t x ds3 m-b it m ask r egister (a ddress = 0 x 35) ................................................................................... 219 t x ds3 f-b it m ask r egister - 1 (a ddress = 0 x 36) ............................................................................. 220 t x ds3 f-b it m ask r egister - 2 (a ddress = 0 x 37) .............................................................................. 220 t x ds3 f-b it m ask r egister - 3 (a ddress = 0 x 38) ............................................................................. 221 t x ds3 f-b it m ask r egister - 4 (a ddress = 0 x 39) .............................................................................. 221 222 pmon lcv e vent c ount r egister - lsb (a ddress = 0 x 51) .............................................................. 222 pmon f raming b it e rror c ount r egister - msb (a ddress = 0 x 52) ............................................... 222 pmon f raming b it e rror c ount r egister - lsb (a ddress = 0 x 53) ................................................ 223 pmon p-b it e rror c ount r egister - msb (a ddress = 0 x 54) ........................................................... 223 pmon p-b it e rror c ount r egister - lsb (a ddress = 0 x 55) ............................................................ 223 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 vii pmon febe e vent c ount r egister - msb (a ddress = 0 x 56) .......................................................... 224 pmon febe e vent c ount r egister - lsb (a ddress = 0 x 57) ........................................................... 224 pmon cp-b it e rror c ount r egister - msb (a ddress = 0 x 58) ........................................................ 224 pmon cp-b it e rror c ount r egister - lsb (a ddress = 0 x 59) ......................................................... 225 pmon h olding r egister (a ddress = 0 x 6c) ....................................................................................... 225 4.0 clear channel framer operation of the XRT72L13 ................................................... 227 m 23 configuration r egister (a ddress = 0 x 07) .................................................................................. 227 4.1 d escription of the ds3 f rames and a ssociated o verhead b its ........................................................... 227 figure 59. ds3 frame format for c-bit parity ................................................................................. . 228 figure 60. ds3 frame format for m13 .......................................................................................... .... 228 o perating m ode r egister (a ddress = 0 x 00) ..................................................................................... 229 t able 10: t he r elationship between the content of b it 2, (c-b it p arity */m13) within the "f ramer o perating m ode " r egister and the resulting ds3 f raming f ormat ............................. 229 t able 11: c- bit f unctions for the c- bit p arity ds3 f rame f ormat .............................................. 229 4.1.1 frame synchronization bits (applies to both m13 and c-bit parity framing formats) ...................... 230 4.1.2 performance monitoring/error detection bits (parity) .................................................................... .... 230 4.1.3 alarm and signaling-related overhead bits ............................................................................... ...... 230 valid m-bits, f-bits, and p-bits 230 4.1.4 the "data link" related overhead bits ................................................................................... .......... 231 4.2 t he t ransmit s ection of the XRT72L13 (c lear -c hannel f ramer m ode o peration ) ........................... 231 figure 61. a simple illustration of the transmit section, within the XRT72L13; when it has been con- figured to operate in the clear-channel framer mode .................................................... 232 4.2.1 the "transmit payload data input interface" block ....................................................................... .... 232 figure 62. a simple illustration of the transmit payload data input interface block .................. 233 t able 12: l isting and d escription of the pins associated with the "t ransmit p ayload d ata i nput i nterface .............................................................................................................................. . 234 figure 63. illustration of the "terminal equipment" being interfaced to the "transmit payload data input interface" block (of the XRT72L13) for mode 1(serial/loop-timing) operation .. 236 figure 64. behavior of the "terminal interface" signals between the "transmit payload data input interface" block (of the XRT72L13) and the terminal equipment (for mode 1 operation) .. 237 o perating m ode r egister (a ddress = 0 x 00) ..................................................................................... 237 figure 65. illustration of the "terminal equipment" being interfaced to the "transmit payload data input interface" block (of the XRT72L13) for mode 2 (serial/local-timed/frame-slave) op- eration ....................................................................................................................... ........... 238 figure 66. behavior of the "terminal interface" signals between the XRT72L13 and the terminal equipment (mode 2 operation) .......................................................................................... 239 o perating m ode r egister (a ddress = 0 x 00) ..................................................................................... 240 figure 67. illustration of the "terminal equipment" being interfaced to the "transmit payload data input interface" block (of the XRT72L13) for mode 3 (serial/local-timed/frame-master) operation ..................................................................................................................... ........ 241 figure 68. behavior of the terminal interface signals between the XRT72L13 and the terminal equipment (ds3 mode 3 operation) .................................................................................. 242 o perating m ode r egister (a ddress = 0 x 00) ..................................................................................... 242 figure 69. illustration of the "terminal equipment" being interfaced to the "transmit payload data input interface" block (of the XRT72L13) for mode 4 (nibble-parallel/loop-timed) opera- tion .......................................................................................................................... .............. 243 figure 70. behavior of the terminal interface signals between the XRT72L13 and the terminal equipment (mode 4 operation) .......................................................................................... 244 o perating m ode r egister (a ddress = 0 x 00) ..................................................................................... 244 figure 71. illustration of the "terminal equipment" being interfaced to the "transmit payload data input interface" block (of the XRT72L13) for mode 5 (nibble-parallel/local-timed/frame- slave) operation ............................................................................................................. .... 246 figure 72. behavior of the "terminal interface" signals between the XRT72L13 and the terminal equipment (ds3 mode 5 operation) .................................................................................. 247 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary viii o perating m ode r egister (a ddress = 0 x 00) ...................................................................................... 247 figure 73. illustration of the "terminal equipment" being interfaced to the "transmit payload data input interface" block (of the XRT72L13) for mode 6 (nibble-parallel/local-timed/frame- master) operation ............................................................................................................. ... 249 figure 74. behavior of the "terminal interface" signals between the XRT72L13 and the terminal equipment (ds3 mode 6 operation) .................................................................................. 250 o perating m ode r egister (a ddress = 0 x 00) ...................................................................................... 250 4.2.2 the transmit overhead data input interface .............................................................................. ....... 250 figure 75. simple illustration of the "transmit overhead data input interface" block ................ 251 t able 13: a l isting of the o verhead bits within the ds3 frame , and their potential sources , within the XRT72L13 ..................................................................................................................... ... 252 t able 14: d escription of "m ethod 1" t ransmit o verhead i nput i nterface s ignals .................... 253 figure 76. illustration of the "terminal equipment" being interfaced to the "transmit overhead data input interface" (method 1) ................................................................................................. 2 54 t able 15: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since "t x o- hf rame " was last sampled " high ") to the ds3 o verhead b it , that is being processed ...... 255 figure 77. illustration of the signal that must occur between the terminal equipment and the XRT72L13, in order to configure the XRT72L13 to transmit a "yellow alarm" to the "remote terminal equipment" ........................................................................................................... . 257 t able 16: d escription of "m ethod 2" t ransmit o verhead i nput i nterface s ignals .................... 258 figure 78. illustration of the "terminal equipment" being interfaced to the "transmit overhead data input interface" (method 2) ................................................................................................. 2 59 t able 17: t he r elationship between the n umber of t x ohe nable pulses ( since the last occur - rence of the t x ohf rame pulse ) to the ds3 o verhead b it , that is being processed by the XRT72L13 ..................................................................................................................... ... 260 figure 79. behavior of "transmit overhead data input interface" signals between the XRT72L13 and the terminal equipment (for method 2) ............................................................................. 262 4.2.3 the transmit ds3 hdlc controller ........................................................................................ ........... 262 t x ds3 feac r egister (a ddress = 0 x 32) ........................................................................................... 263 t ransmit ds3 feac c onfiguration and s tatus r egister (a ddress = 0 x 31) ................................ 263 t ransmit ds3 feac c onfiguration and s tatus r egister (a ddress = 0 x 31) ................................. 263 figure 80. a flow chart depicting how to transmit a feac message via the feac transmitter 264 figure 81. lapd message frame format ......................................................................................... . 265 t able 18: t he lapd m essage t ype and the c orresponding value of the f irst b yte , within the i n - formation p ayload ............................................................................................................... 266 t ransmit ds3 lapd c onfiguration r egister (a ddress = 0 x 33) ...................................................... 266 t able 19: r elationship between t x lapd m sg l ength and the lapd m essage s ize ................... 266 t ransmit ds3 lapd c onfiguration r egister (a ddress = 0 x 33) ...................................................... 266 t able 20: r elationship between t x lapd m sg l ength and the lapd m essage s ize ................... 267 t ransmit ds3 lapd s tatus /i nterrupt r egister (a ddress = 0 x 34) .................................................. 267 figure 82. flow chart depict how to use the lapd transmitter ..................................................... 269 o perating m ode r egister (a ddress = 0 x 00) ...................................................................................... 269 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ......................................................................... 270 4.2.4 the transmit ds3 framer block ........................................................................................... ............. 270 figure 83. a simple illustration of the transmit ds3 framer block and the associated paths to other functional blocks ............................................................................................................. ... 271 t x ds3 c onfiguration r egister (a ddress = 0 x 30) ............................................................................ 272 t able 21: t he r elationship between the contents of b it 7 (t x y ellow a larm ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction ..... 272 t able 22: t he r elationship between the contents of b it 6 (t x x-b its ) within the t x ds3 c onfigu - ration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction ................... 273 t able 23: t he r elationship between the contents of b it 5 (t x i dle ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer a ction .............................................. 273 t able 24: t he r elationship between the contents of b it 4 (t x ais p attern ) within the t x ds3 c on - ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 ix figuration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction ............ 274 t able 25: t he r elationship between the contents of b it 3 (t x los) within the t x ds3 c onfigura - tion r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction ....................... 274 t x ds3 m-b it m ask r egister , a ddress = 0 x 35 .................................................................................. 275 t x ds3 f-b it m ask 1 r egister , a ddress = 0 x 36 ................................................................................. 275 t x ds3 f-b it m ask 2 r egister , a ddress = 0 x 37 ................................................................................. 276 t x ds3 f-b it m ask 3 r egister , a ddress = 0 x 38 ................................................................................. 276 t x ds3 f-b it m ask 4 r egister , a ddress = 0 x 39 ................................................................................. 276 4.2.5 the transmit ds3 line interface block ................................................................................... .......... 276 figure 84. approach to interfacing the XRT72L13 framer ic device to the xrt7300 ds3/e3/sts-1 transmitter liu ............................................................................................................... ..... 277 figure 85. a simple illustration of the "transmit ds3 liu interface" block .................................. 278 figure 86. the behavior of txpos and txneg signals during data transmission while the transmit ds3 liu interface is operating in the unipolar mode ....................................................... 278 i/o c ontrol r egister (a ddress = 0 x 01) ............................................................................................. 279 t able 26: t he r elationship between the content of b it 3 (u nipolar /b ipolar *) within the uni i/o c ontrol r egister and the t ransmit ds3 f ramer l ine i nterface o utput m ode ........... 279 figure 87. illustration of ami line code ..................................................................................... ...... 280 figure 88. illustration of two examples of b3zs encoding ............................................................. 280 i/o c ontrol r egister (a ddress = 0 x 01) ............................................................................................. 281 t able 27: t he r elationship between b it 4 (ami/b3zs*) within the "i/o c ontrol " r egister and the b ipolar l ine c ode that is output by the t ransmit ds3 liu i nterface b lock ............... 281 ii/o c ontrol r egister (a ddress = 0 x 01) ............................................................................................ 281 t able 28: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the "i/o c ontrol " r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on ....... 281 figure 89. waveform/timing relationship between txlineclk, txpos and txneg - txpos and tx- neg are configured to be updated on the rising edge of txlineclk ............................. 282 figure 90. waveform/timing relationship between txlineclk, txpos and txneg - txpos and tx- neg are configured to be updated on the falling edge of txlineclk ............................. 282 4.2.6 transmit section interrupt processing ................................................................................... ............ 282 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ........................................................................ 283 t ransmit ds3 feac c onfiguration & s tatus r egister (a ddress = 0 x 31) ..................................... 283 t ransmit ds3 feac c onfiguration & s tatus r egister (a ddress = 0 x 31) ..................................... 284 t x ds3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 284 t x ds3 lapd s tatus and i nterrupt r egister (a ddress = 0 x 34) ...................................................... 285 4.3 t he r eceive s ection of the XRT72L13 (ds3 m ode o peration ) .............................................................. 285 figure 91. a simple illustration of the receive section of the XRT72L13, when it has been config- ured to operate in the ds3 mode ....................................................................................... 286 4.3.1 the receive ds3 liu interface block ..................................................................................... .......... 286 figure 92. a simple illustration of the "receive ds3 liu interface" block ................................... 287 figure 93. behavior of the rxpos, rxneg and rxlineclk signals during data reception of unipolar data .......................................................................................................................... ............ 288 ii/o c ontrol r egister (a ddress = 0 x 01) ............................................................................................ 288 t able 29: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the "i/o c ontrol " r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on ....... 288 figure 94. illustration on how the receive ds3 framer (within the XRT72L13 framer ic) being inter- face to thexrt7300 line interface unit, while the framer is operating in bipolar mode .... 289 figure 95. illustration of ami line code ..................................................................................... ...... 289 figure 96. illustration of two examples of b3zs decoding ............................................................. 290 ii/o c ontrol r egister (a ddress = 0 x 01) ............................................................................................ 291 t able 30: t he r elationship between the contents of b it 1 (r x l ine c lk i nv ) of the i/o c ontrol r eg - ister , and the sampling edge of the r x l ine c lk signal .................................................... 291 figure 97. waveform/timing relationship between rxlineclk, rxpos and rxneg - when rxpos and rxneg are to be sampled on the rising edge of rxlineclk .................................... 291 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary x figure 98. waveform/timing relationship between rxlineclk, rxpos and rxneg - when rxpos and rxneg are to be sampled on the falling edge of rxlineclk .................................... 292 4.3.2 the receive ds3 framer block ............................................................................................ ............. 292 figure 99. a simple illustration of the receive ds3 framer block and the associated paths to the other functional blocks ..................................................................................................... 2 92 figure 100. the state machine diagram for the "receive ds3 framer" block's "frame acquisition/ maintenance" algorithm ..................................................................................................... 29 3 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ...................................................... 294 t able 31: t he r elationship between the contents of b it 2 (f raming on p arity ) within the "r x ds3 c onfiguration and s tatus " r egister , and the resulting "f raming a cquisition c riteria ... 294 "r x ds3 c onfiguration and s tatus " r egister , (a ddress = 0 x 10) .................................................... 295 t able 32: t he r elationship between the contents of b it 1 (f-s ync a lgo ) within the r x ds3 c on - figuration and s tatus r egister , and the resulting "f- bit oof d eclaration criteria " used by the "r eceive ds3 f ramer " block ................................................................................... 295 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ...................................................... 295 t able 33: t he r elationship between the contents of b it 0 (m-s ync a lgo ) within the "r x ds3 c on - figuration and s tatus " r egister , and the resulting "m-b it oof d eclaration c riteria " used by the "r eceive ds3 f ramer " block .......................................................................... 295 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ...................................................... 296 i/o c ontrol r egister (a ddress = 0 x 01) ............................................................................................. 296 pmon f raming b it e rror e vent c ount r egister - msb (a ddress = 0 x 52) .................................... 296 pmon f raming b it e rror e vent c ount r egister - lsb (a ddress = 0 x 53) ..................................... 297 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ...................................................... 297 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ...................................................... 298 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ...................................................... 298 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ...................................................... 299 r x ds3 c onfiguration and s tatus r egister , (a ddress = 0 x 10) ...................................................... 299 r x ds3 s tatus r egister (a ddress = 0 x 11) ........................................................................................ 299 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 300 r x ds3 s tatus r egister (a ddress = 0 x 11) ......................................................................................... 300 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ........................................................................ 301 pmon p arity e rror e vent c ount r egister - msb (a ddress = 0 x 54) ............................................. 301 pmon p arity e rror e vent c ount r egister - lsb (a ddress = 0 x 55) .............................................. 301 figure 101. a simple illustration of the locations of the source, mid-network and sink ter- minal equipment (for cp-bit processing) ......................................................................... 302 figure 102. illustration of the presumed configuration of the mid-network terminal equipment . 303 4.3.3 the receive hdlc controller block ....................................................................................... ........... 303 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................... 304 r x ds3 feac r egister (a ddress = 0 x 16) .......................................................................................... 305 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ............................................... 305 figure 103. flow diagram depicting how the receive feac processor functions ..................... 306 figure 104. lapd message frame format ........................................................................................ 307 r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) ........................................................................... 307 r x ds3 lapd s tatus r egister (a ddress = 0 x 19) .............................................................................. 308 t able 34: t he r elationship between r x lapdt ype [1:0] and the resulting lapd m essage type and size .............................................................................................................................. ............ 308 figure 105. flow chart depicting the functionality of the lapd receiver .................................... 310 4.3.4 the receive overhead data output interface .............................................................................. ..... 310 figure 106. a simple illustration of the "receive overhead output interface" block .................. 311 t able 35: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface " b lock .................................................................................................................. 312 figure 107. illustration of how to interface the terminal equipment to the receive overhead data output interface block (for method 1). ............................................................................. 313 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 xi t able 36: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since "r x o- hf rame " was last sampled " high ") to the ds3 o verhead b it , that is being output via the r x oh output pin ............................................................................................................... 314 figure 108. illustration of the signals that are output via the receive overhead output interface (for method 1). .................................................................................................................... ........ 316 t able 37: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface " b lock (m ethod 2) .............................................................................................. 317 figure 109. illustration of how to interface the terminal equipment to the receive overhead data output interface block (for method 2). ............................................................................ 318 t able 38: t he r elationship between the n umber of r x ohe nable output pulses (( since "r x o- hf rame " was last sampled " high ") to the ds3 o verhead b it , that is being output via the r x oh output pin ............................................................................................................... 319 figure 110. illustration of the signals that are output via the receive overhead data output inter- face block (for method 2). ................................................................................................. 3 21 4.3.5 the receive payload data output interface ............................................................................... ...... 321 figure 111. a simple illustration of the "receive payload data output interface" block ............ 322 t able 39: l isting and d escription of the pin associated with the r eceive p ayload d ata o utput i n - terface block ....................................................................................................................... 323 figure 112. illustration of the XRT72L13 ds3/e3 framer ic being interfaced to the "receive" termi- nal equipment (serial mode operation) ............................................................................ 324 figure 113. an illustration of the behavior of the signals between the "receive payload data output interface" block (of the XRT72L13) and the terminal equipment (serial mode operation) 325 figure 114. illustration of the XRT72L13 ds3/e3 framer ic being interfaced to the receive section of the terminal equipment (nibble-mode operation) ...................................................... 326 figure 115. an illustration of the behavior of the signals between the receive payload data output interface block (of the XRT72L13) and the terminal equipment (nibble-mode operation). 327 4.3.6 receive section interrupt processing .................................................................................... ............ 327 b lock i nterrupt e nable r egister (a ddress = 0 x 04) ........................................................................ 328 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 328 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 329 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ............................................................ 329 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 330 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 330 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ............................................................ 330 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 331 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 331 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ............................................................ 332 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 332 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 333 r x ds3 c onfiguration & s tatus r egister (a ddress = 0 x 10) ............................................................ 333 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 334 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 334 r x ds3 s tatus r egister (a ddress = 0 x 11) ......................................................................................... 334 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 335 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 335 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 336 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 336 r x ds3 i nterrupt e nable r egister (a ddress = 0 x 12) ....................................................................... 336 r x ds3 i nterrupt s tatus r egister (a ddress = 0 x 13) ....................................................................... 337 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ................................................ 337 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ................................................ 338 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ................................................ 338 r x ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 17) ................................................ 339 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary xii r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) ............................................................................ 339 r x ds3 lapd c ontrol r egister (a ddress = 0 x 18) ............................................................................ 340 5.0 channelized (m13) mode operation of the XRT72L13 ................................................................ 341 m23 c onfiguration r egister (a ddress = 0 x 07) ................................................................................ 341 5.1 a n o verview of c hannelized o peration ................................................................................................... 341 5.1.1 in north american applications .......................................................................................... ................ 341 figure 116. simple illustration of the overall scheme to mux 28 ds1 signals into a ds3 signal ...... 341 figure 117. simple illustration of the overall scheme to demux a ds3 signal into 28 ds1 signals . 342 5.1.2 .itu-t g.747 applications ............................................................................................... ................... 342 figure 118. simple illustration of the overall scheme to mux 21 e1 signals into a ds3 signal . 342 figure 119. simple illustration of the overall scheme to demux 21 e1 signals from a ds3 signal .. 343 5.1.3 real configuration options offered by the XRT72L13 ...................................................................... 343 5.2 c hannelized o peration in the t ransmit d irection .................................................................................. 343 5.2.1 channelized operation, while the XRT72L13 is operating in the m13 framing format. ................. 343 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 344 figure 120. illustration of m12 mux #1 being configured to operate in the ds1 mode ............. 344 figure 121. illustration of the ds2 framing structure ..................................................................... 34 5 figure 122. the ds2 payload bits ............................................................................................. ......... 345 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 347 m12 ds2 # 1 a is r egister (a ddress = 0 x 21) ...................................................................................... 347 m23 t x ds2 ais r egister (a ddress = 0 x 08) ...................................................................................... 347 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 348 figure 123. illustration of the m12 mux # 1 being configured to operate in the g.747 mode .. 348 figure 124. illustration of the itu-t g.747 framing structure ..................................................... 349 figure 125. the itu-t g.747 payload bits ................................................................................... .. 350 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 351 m12 ds2 # 1 a is r egister (a ddress = 0 x 21) ...................................................................................... 351 m23 t x ds2 ais r egister (a ddress = 0 x 08) ...................................................................................... 351 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 352 5.2.2 channelized operation, while the XRT72L13 is operating in the c-bit parity framing format. ...... 352 5.3 c hannelized o peration in the r eceive d irection .................................................................................... 352 5.3.1 channelized operation, while the XRT72L13 is operating in the m13 framing format. ................. 352 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 352 ds2 # 1 f ramer s tatus r egister (a ddress = 0 xa 3) ......................................................................... 353 ds2 # 1 f ramer s tatus r egister (a ddress = 0 xa 3) ......................................................................... 353 ds2 # 1 f ramer s tatus r egister (a ddress = 0 xa 3) ......................................................................... 354 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 354 m12 ds2 # 1 c onfiguration r egister (a ddress = 0 x 1a) .................................................................. 355 ds2 # 1 f ramer s tatus r egister (a ddress = 0 xa 3) ......................................................................... 355 ds2 # 1 f ramer s tatus r egister (a ddress = 0 xa 3) ......................................................................... 356 ds2 # 1 f ramer s tatus r egister (a ddress = 0 xa 3) ......................................................................... 356 5.3.2 channelized operation, while the XRT72L13 is operating in the c-bit parity framing format. ...... 356 5.4 d iagnostic o perations - c hannelized m ode ............................................................................................ 356 5.4.1 m12 mux (ds1 or e1) loop-backs .......................................................................................... .......... 356 5.4.2 m23 mux (ds2 or g.747) loop-backs ....................................................................................... ....... 356 5.5 c hannelized m ode i nterrupts ................................................................................................................... 356 ordering information .......................................................................................................... ........ 357 package dimensions ............................................................................................... 357 r evisions .............................................................................................................................. ................. 358 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 3 pin descriptions p in #n ame t ype d escription 1rxds1data_26 o receive ds1/e1 data output - channel 26: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_26. 2 rxds1clk_26 o receive ds1/e1 clock output - channel 26: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_26" line, upon the rising edge of this signal. 3rxds1data_25 o receive ds1/e1 data output - channel 25: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_25. 4 rxds1clk_25 o receive ds1/e1 clock output - channel 25: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_25" line, upon the rising edge of this signal. 5rxds1data_24 o receive ds1/e1 data output - channel 24: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_24. 6 rxds1clk_24 o receive ds1/e1 clock output - channel 24: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_24" line, upon the rising edge of this signal. 7rxds1data_23 o receive ds1 data output - channel 23: this pin outputs a ds1 signal from the m12 multiplexer. each bit, within the ds1 data stream is output upon the rising edge of rxds1clk_23. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output the contents of ds2 channel # 6, if m12 mux # 6 is bypassed. 8 rxds1clk_23 o receive ds1/e1 clock output - channel 23: this pin outputs a ds1 (1.544mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_23" line, upon the rising edge of this signal. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output a ds2 rate clock signal (6.312mhz) if m12 # 6 is bypassed. 9rxds1data_22 o receive ds1/e1 data output - channel 22: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_22. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 4 10 rxds1clk_22 o receive ds1/e1 clock output - channel 22: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_22" line, upon the rising edge of this signal. 11 vdd **** power supply pin 12 rxds1data_21 o receive ds1/e1 data output - channel 21 this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_21. 13 rxds1clk_21 o receive ds1/e1 clock output - channel 21: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_21" line, upon the rising edge of this signal. 14 rxds1data_20 o receive ds1/e1 data output - channel 20: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_20. 15 rxds1clk_20 o receive ds1/e1 clock output - channel 20: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_20" line, upon the rising edge of this signal. 16 rxds1data_19 o receive ds1 data output - channel 19: this pin outputs a ds1 signal from the m12 multiplexer. each bit, within the ds1 data stream is output upon the rising edge of rxds1clk_19. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output the contents of ds2 channel # 5, if m12 mux # 5 is bypassed. 17 rxds1clk_19 o receive ds1 clock output - channel 19: this pin outputs a ds1 (1.544mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_19" line, upon the rising edge of this signal. this output pin is inactive if the corresponding m12 demux is de- multiplexing an itu-t g.747 data stream. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output a ds2 rate clock signal (6.312mhz) if m12 # 5 is bypassed. 18 rxds1data_18 o receive ds1/e1 data output - channel 18 this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_18. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 5 19 rxds1clk_18 o receive ds1/e1 clock output - channel 18: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_18" line, upon the rising edge of this signal. 20 rxds1data_17 o receive ds1/e1 data output - channel 17: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_17. 21 rxds1clk_17 o receive ds1/e1 clock output - channel 17: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_17" line, upon the rising edge of this signal. 22 rxds1data_16 o receive ds1/e1 data output - channel 16: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_16. 23 rxds1clk_16 o receive ds1/e1 clock output - channel 16: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_16" line, upon the rising edge of this signal. 24 rxds1data_15 o receive ds1 data output - channel 15: this pin outputs a ds1 signal from the m12 multiplexer. each bit, within the ds1 data stream is output upon the rising edge of rxds1clk_15. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output the contents of ds2 channel # 4, if m12 mux # 4 is bypassed. 25 tck boundary scan pin 26 tms boundary scan pin 27 tdi boundary scan pin 28 tdo boundary scan pin 29 gnd **** ground pin 30 rxds1clk_15 o receive ds1 clock output - channel 15: this pin outputs a ds1 (1.544mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_15" line, upon the rising edge of this signal. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output a ds2 rate clock signal (6.312mhz) if m12 # 4 is bypassed. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 6 31 rxds1data_14 o receive ds1/e1 data output - channel 14: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_14. 32 rxds1clk_14 o receive ds1/e1 clock output - channel 14: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_14" line, upon the rising edge of this signal. 33 rxds1data_13 o receive ds1/e1 data output - channel 13: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_13. 34 rxds1clk_13 o receive ds1/e1 clock output - channel 13: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_13" line, upon the rising edge of this signal. 35 rxds1data_12 o receive ds1/e1 data output - channel 12: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_12. 36 rxds1clk_12 o receive ds1/e1 clock output - channel 12: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_12" line, upon the rising edge of this signal. 37 rxds1data_11 o receive ds1 data output - channel 11: this pin outputs a ds1 signal from the m12 multiplexer. each bit, within the ds1 data stream is output upon the rising edge of rxds1clk_11. this output pin is inactive if the corresponding m12 demux is de- multiplexing an itu-t g.747 data stream. this pin will output the contents of ds2 channel # 3, if m12 mux # 3 is bypassed. 38 rxds1clk_11 o receive ds1 clock output - channel 11: this pin outputs a ds1 (1.544mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_11" line, upon the rising edge of this signal. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output a ds2 rate clock signal (6.312mhz) if m12 # 3 is bypassed. 39 vdd **** power supply pin 40 rxds1data_10 o receive ds1/e1 data output - channel 10: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_10. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 7 41 rxds1clk_10 o receive ds1/e1 clock output - channel 10: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_10" line, upon the rising edge of this signal. 42 rxds1data_9 o receive ds1/e1 data output - channel 9: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_9. 43 rxds1clk_9 o receive ds1/e1 clock output - channel 9: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_9" line, upon the rising edge of this signal. 44 rxds1data_8 o receive ds1/e1 data output - channel 8: this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_8. 45 rxds1clk_8 o receive ds1/e1 clock output - channel 8: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_8" line, upon the rising edge of this signal. 46 rxds1data_7 rxhdlc_data_7 o receive ds1 data output - channel 7/receive hdlc controller block output - bit 7: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1 data output - channel 7: (multiplexer/de-multi- plexer mode): this pin outputs a ds1 signal from the m12 multiplexer. each bit, within the ds1 data stream is output upon the rising edge of rxds1clk_7. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output the contents of ds2 channel # 2, if m12 mux # 2 is bypassed. receive hdlc controller block output - bit 7 (high speed hdlc controller mode) this output pin along with rxhdlc_data[0:6] output the contents of all hdlc frames that have been received (via the ds3 payload) from the remote terminal equipment. the data on this output pin is updated upon the rising edge of "rxh- dlcclk". n ote : this pin is inactive while the receive hdlc controller is receiving the "flag sequence" octet. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 8 47 rxds1clk_7 o receive ds1 clock output - channel 7: this pin outputs a ds1 (1.544mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_7" line, upon the rising edge of this signal. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output a ds2 rate clock signal (6.312mhz) if m12 # 2 is bypassed. 48 rxds1data_6 rxhdlc_data_6 o receive ds1/e1 data output - channel 6/receive hdlc control- ler block output - bit 6: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1/e1 data output - channel 6: (multiplexer/de-multi- plexer mode): this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_6. receive hdlc controller block output - bit 6: (high speed hdlc controller mode) this output pin along with rxhdlc_data[0:5] and rxhdlc_data_7 output the contents of all hdlc frames that have been received (via the ds3 payload) from the remote terminal equipment. the data on this output pin is updated upon the rising edge of "rxh- dlcclk". n ote : this pin is inactive while the receive hdlc controller is receiving the "flag sequence" octet. 49 gnd **** ground pin 50 rxds1clk_6 o receive ds1/e1 clock output - channel 6: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_6" line, upon the rising edge of this signal. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 9 51 rxds1data_5 rxhdlc_data_5 o receive ds1/e1 data output - channel 5/receive hdlc control- ler block output - bit 5: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1/e1 data output - channel 5: (multiplexer/de-multi- plexer mode): this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_5. receive hdlc controller block output - bit 5: (high speed hdlc controller mode) this output pin along with rxhdlc_data[0:4] and rxhdlc_data[6:7] output the contents of all hdlc frames that have been received (via the ds3 payload) from the remote terminal equip- ment. the data on this output pin is updated upon the rising edge of "rxh- dlcclk". n ote : this pin is inactive while the receive hdlc controller is receiving the "flag sequence" octet. 52 rxds1clk_5 o receive ds1/e1 clock output - channel 5: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_5" line, upon the rising edge of this signal. 53 rxds1data_4/ rxhdlc_data_4 o receive ds1/e1 data output - channel 4/receive hdlc control- ler block output - bit 4: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1/e1 data output - channel 4: (multiplexer/de-multi- plexer mode): this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_4. receive hdlc controller block output - bit 4: (high speed hdlc controller mode) this output pin along with rxhdlc_data[0:3] and rxhdlc_data[5:7] output the contents of all hdlc frames that have been received (via the ds3 payload) from the remote terminal equip- ment. the data on this output pin is updated upon the rising edge of "rxh- dlcclk". n ote : this pin is inactive while the receive hdlc controller is receiving the "flag sequence" octet. 54 rxds1clk_4 o receive ds1/e1 clock output - channel 4: this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_4" line, upon the rising edge of this signal. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 10 55 rxds1data_3/ rxhdlc_data_3 o receive ds1 data output - channel 3/receive hdlc controller block output - bit 3 the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1 data output - channe1 3 (multiplexer/de-multi- plexer mode) this pin outputs a ds1 signal from the m12 de-multiplexer. each bit, within the ds1 data stream is output upon the rising edge of rxds1clk_3. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output the contents of ds2 channel # 1, if m12 mux # 1 is bypassed. receive hdlc controller block output - bit 3 (high speed hdlc controller mode) this output pin along with rxhdlc_data[0:2] and rxhdlc_data[4:7] output the contents of all hdlc frames that have been received (via the ds3 payload) from the remote terminal equip- ment. the data on this output pin is updated upon the rising edge of "rxh- dlcclk". n ote : this pin is inactive while the receive hdlc controller is receiving the "flag sequence" octet. 56 rxds1clk_3/ rxidle o receive ds1 clock output - channel 3/receive idle (flag sequence) indicator output: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1 clock output - channel 3 (multiplexer/de-multi- plexer mode): this pin outputs a ds1 (1.544mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_3" line, upon the rising edge of this signal. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output a ds2 rate clock signal (6.312mhz) if m12 # 1 is bypassed. rxidle - receive idle (flag sequence) indicator output (high speed hdlc controller mode): the receive hdlc controller block will drive this output pin "high" any time it is receiving a continuous stream of the "flag sequence" octet (0x7e) via the ds3 payload. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 11 57 rxds1data_2/ rxhdlc_data_2 o receive ds1/e1 data output - channel 2/receive hdlc control- ler block output - bit 2 the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1 data output - channel 2 (multiplexer/de-multiplexer mode) this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_2. receive hdlc controller block output - bit 2 (high speed hdlc controller mode) this output pin along with rxhdlc_data[0:1] and rxhdlc_data[3:7] output the contents of all hdlc frames that have been received (via the ds3 payload) from the remote terminal equip- ment. the data on this output pin is updated upon the rising edge of "rxh- dlcclk". n ote : this pin is inactive while the receive hdlc controller is receiving the "flag sequence" octet. 58 rxds1clk_2/ validfcs o receive ds1/e1 clock output - channel 2/valid fcs indicator output : the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1 clock output - channel 2 (multiplexer/de-multi- plexer mode) this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_2" line, upon the rising edge of this signal. valid fcs indicator output - (high speed hdlc controller mode) this output pin is driven "high" anytime the receive hdlc controller block has received an hdlc frame with a valid fcs value. 59 rxds1data_1/ rxhdlc_data_1 o receive ds1/e1 data output - channel 1/receive hdlc control- ler block output - bit 1: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1 data output - channel 1: (multiplxer/de-multiplexer mode): this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_1. receive hdlc controller block output - bit 1 (high speed hdlc controller mode) this output pin along with rxhdlc_data_0 and rxhdlc_data[2:7] output the contents of all hdlc frames that have been received (via the ds3 payload) from the remote terminal equipment. the data on this output pin is updated upon the rising edge of "rxh- dlcclk". n ote : this pin is inactive while the receive hdlc controller is receiving the "flag sequence" octet. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 12 60 rxds1clk_1/ rxhdlcclk o receive ds1/e1 clock output - channel 0/receive hdlc con- troller clock output: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1/e1 clock output - channel 1 (multiplexer/de-multi- plexer mode): this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_0" line, upon the rising edge of this signal. receive hdlc clock output pin (high speed hdlc controller mode) the contents of the "received" hdlc frames are output via the rxhdlc_data[7:0] bus, upon the rising edge of this input pin. 61 rxds1data_0/ rxhdlc_data_0 o receive ds1/e1 data output - channel 0/receive hdlc control- ler block output - bit 0: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1/e1 data output - channel 0 (multiplexer/de-multi- plexer mode) this pin outputs either a ds1 or e1 signal from the m12 multiplexer. each bit, within the ds1 or e1 data stream is output upon the rising edge of rxds1clk_0. receive hdlc controller block output - bit 0: (high speed hdlc controller mode) this output pin along with rxhdlc_data[1:7] output the contents of all hdlc frames that have been received (via the ds3 payload) from the remote terminal equipment. the data on this output pin is updated upon the rising edge of "rxh- dlcclk". n ote : this pin is inactive while the receive hdlc controller is receiving the "flag sequence" octet. 62 vdd **** power supply pin 63 rxds1clk_0/ txhdlcclk o receive ds1/e1 clock output - channel 0/transmit hdlc con- troller clock output: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. receive ds1/e1 clock output - channel 0 (multiplexer/de-multi- plexer mode): this pin outputs either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_0" line, upon the rising edge of this signal. transmit hdlc controller clock output (high speed hdlc con- troller mode): the data on the "txhdlc_data[7:0] bus, are latched into the "trans- mit hdlc controller" block upon the rising edge of this clock signal. 64 reset i reset input: when this "active-low" signal is asserted, the framer will be asyn- chronously reset. additionally, all outputs will be "tri-stated", and all on-chip registers will be reset to their default values. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 13 65 a0 i address bus input (microprocessor interface) - lsb (least sig- nificant bit) (please see description for a8) 66 d0 i/o bi-directional data bus (microprocessor interface section): please see description for d7 67 a1 i address bus input (microprocessor interface) - lsb (least sig- nificant bit) (please see description for a8) 68 int o interrupt request output: this open-drain, active-low output signal will be asserted when the framer is requesting interrupt service from the local microprocessor. this output pin should typically be connected to the "interrupt request" input of the local microprocessor. 69 d1 i/o bi-directional data bus (microprocessor interface section): please see description for d7 70 a2 i address bus input (microprocessor interface) - lsb (least significant bit) (please see description for a8) 71 moto i motorola/intel processor interface select mode: this input pin allows the user to configure the microprocessor inter- face to interface with either a "motorola-type" or "intel-type" micropro- cessor/microcontroller. tying this input pin to vcc, configures the microprocessor interface to operate in the motorola mode (e.g., the framer can be readily interfaced to a "motorola type" local micropro- cessor). tying this input pin to gnd configures the microprocessor interface to operate in the intel mode (e.g., the framer can be readily interfaced to a intel type" local microprocessor). 72 gnd **** ground pin 73 d2 i/o bi-directional data bus (microprocessor interface section): please see description for d7 74 a3 i address bus input (microprocessor interface) - lsb (least sig- nificant bit) (please see description for a8) pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 14 75 rdy_dtck o ready or dtack: this "active-low" output pin will function as the ready output, when the microprocessor interface is running in the "intel" mode; and will function as the dtack output, when the microprocessor interface is running in the "motorola" mode. "intel" mode - ready output when the framer negates this output pin (e.g., toggles it "low"), it indi- cates (to the mp) that the current read or write cycle is to be extended until this signal is asserted (e.g., toggled "high"). "motorola" mode: - dtack (data transfer acknowledge) output the framer will assert this pin in order to inform the local micropro- cessor that the present read or write cycle is nearly complete. if the framer requires that the current read or write cycle be extended, then the framer will delay its assertion of this signal. the 68000 family of mps requires this signal from its peripheral devices, in order to quickly and properly complete a read or write cycle. 76 d3 i/o bi-directional data bus (microprocessor interface section): please see description for d7 77 a4 i address bus input (microprocessor interface) - lsb (least sig- nificant bit) (please see description for a8) 78 ale_as i address latch enable/address strobe: this input is used to latch the address (present at the microprobessor interface address bus, a[8:0]) into the framer microprocessor inter- face circuitry and to indicate the start of a read/write cycle. this input is active-high in the intel mode (moto = "low") and active-low in the motorola mode (moto = "high"). 79 d4 i/o bi-directional data bus (microprocessor interface section): please see description for d7 80 a5 i address bus input (microprocessor interface) - lsb (least sig- nificant bit): (please see description for a8) 81 cs i chip select input: this active-low input signal selects the microprocessor interface sec- tion of the framer and enables read/write operations between the "local" microprocessor and the framer on-chip registers and ram locations. 82 d5 i/o bi-directional data bus (microprocessor interface section): please see description for d7 83 a6 i address bus input (microprocessor interface) - lsb (least sig- nificant bit): (please see description for a8) pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 15 84 rd _ds i read data strobe (intel mode): if the microprocessor interface is operating in the intel mode, then this input will function as the rd* (read strobe) input signal from the local mp. once this active-low signal is asserted, then the framer will place the contents of the addressed registers (within the framer) on the microprocessor data bus (d[7:0]). when this signal is negated, the data bus will be tri-stated. data strobe (motorola mode): if the microprocessor interface is operating in the motorola mode, then this pin will function as the active-low data strobe signal. 85 d6 i/o bi-directional data bus (microprocessor interface section): please see description for d7 86 a7 i address bus input (microprocessor interface): (please see description for a8) 87 vdd **** power supply pin 88 wr _rw i write data strobe (intel mode) if the microprocessor interface is operating in the intel mode, then this active-low input pin functions as the wr* (write strobe) input signal from the mp. once this active-low signal is asserted, then the framer will latch the contents of the mp data bus, into the addressed register (or ram location) within the framer ic. r/w input pin (motorola mode) when the microprocessor interface section is operating in the "motor- ola mode", then this pin is functionally equivalent to the "r/w*" pin. in the motorola mode, a "read" operation occurs if this pin is at a logic "1". similarly, a write operation occurs if this pin is at a logic "0". 89 d7 i/o msb of bi-directional data bus (microprocessor interface sec- tion): this pin, along with pins d0 - d6, function as the microprocessor interface bi-directional data bus, and is intended to be interfaced to the "local" microprocessor. 90 a8 i address bus input (microprocessor interface) - msb (most sig- nificant bit): this input pin, along with inputs a0 - a7 are used to select the on-chip framer register and ram space for read/write operations with the "local" microprocessor. 91 gnd (test mode) **** ground pin pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 16 92 nibbleintf i nibble interface select input pin this input pin allows the user to configure the transmit payload data input interface and the receive payload data output interface to operate in either the "serial-mode" or the "nibble/parallel-mode". setting this input pin "high" configures the transmit and receive ter- minal interfaces to operate in the "nibble/parallel-mode". in this mode, the transmit payload data input interface block will accept the outbound payload data (from the terminal equipment) in a nib- ble-parallel manner via the txnib[3:0] input pins. further, the receive payload data output interface block will output the inbound payload data (to the terminal equipment) in a nibble-paral- lel manner via the rxnib[3:0] output pin. setting this input pin "low" configures the transmit and receive termi- nal interfaces to operate in the "serial" mode. in this mode, the transmit payload data input interface block will accept the out- bound payload data (from the terminal equipment) in a serial man- ner via the txser input pin. further, the receive payload data output interface block will output the inbound payload data (to the terminal equipment) in a serial manner via the rxser output pin. 93 txds1data_27/ txhdlcdata_7 i transmit ds1 data input - channel 27: this input pin accepts a ds1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_27 signal. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts ds2 data if m12 mux # 7 is bypassed. 94 txds1clk_27/ send_msgi i transmit ds1 clock input - channel 27/send_msg request input: the function of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1 clock input - channel 27 (multiplexer/de-multi- plexer mode): this input pin accepts a ds1 (1.544mhz) clock signal from the termi- nal equipment. the falling edge of this signal is used to sample the data at the "txds1data_27" input pin. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts a ds2 rate clock signal (6.312mhz) if m12 mux # 7 is bypassed. send_msg request input: (high speed hdlc controller mode): setting this input pin "high" indicates that the byte, currently on the txhdlc_data[7:0] bus is the last byte to be included in the hdlc frame (not counting the crc-16 or crc-32 value). pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 17 95 txds1data_26/ txhdlcdata_6 i transmit ds1/e1 data input - channel 26/transmit hdlc control- ler block input - bit 6: the function of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1/e1 data input - channel 26 (multiplexer/de-multi- plexer mode): this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_26 signal. transmit hdlc controller block input - bit 6: (high speed hdlc controller mode) this input pin, along with txhdlc_data[0:5] and txhdlc_data_7 function as the "transmit hdlc controller byte input interface. data that resides on this bus, during the rising edge of "txhdlcclk" is latched into the "transmit hdlc controller block" and will be encap- sulated into a hdlc frame and transmitted to the remote terminal equipment. 96 txds1clk_26/ send_fcs i transmit ds1/e1 clock input - channel 26/send_fcs request input pin: the function of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1/e1 clock input - channel 26 (multiplexer/de-multi- plexer mode): this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_26" input pin. sendfcs request input (high speed hdlc controller mode) setting this input pin "high, at the end of enter data to be transported over the ds3 transport medium via an out-bound hdlc frame, com- mands the transmit hdlc controller to compute fcs value (e.g., either a crc-16 or crc-32 value) and append it to the outbound hdlc frame. 97 txds1data_25/ txhdlcdata_5 i transmit ds1/e1 data input - channel 25/transmit hdlc control- ler block input - bit 5: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1/e1 data input - channel 25 (multiplexer/de-multi- plexer mode): this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_25 signal. transmit hdlc controller block input - bit 5: (high speed hdlc controller mode) this input pin, along with txhdlc_data[0:4] and txhdlc_data[6:7] function as the "transmit hdlc controller byte input interface. data that resides on this bus, during the rising edge of "txhdlcclk" is latched into the "transmit hdlc controller block" and will be encap- sulated into a hdlc frame and transmitted to the remote terminal equipment. 98 gnd **** ground pin pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 18 99 txds1clk_25 i transmit ds1/e1 clock input - channel 25: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_25" input pin. 100 txds1data_24/ txhdlcdata_4 i transmit ds1/e1 data input - channel 24/transmit hdlc control- ler block input - bit 4: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1/e1 data input - channel 24 (multiplexer/de-multi- plexer mode): this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_24 signal. transmit hdlc controller block input - bit 4: (high speed hdlc controller mode) this input pin, along with txhdlc_data[0:3] and txhdlc_data[5:7] function as the "transmit hdlc controller byte input interface. data that resides on this bus, during the rising edge of "txhdlcclk" is latched into the "transmit hdlc controller block" and will be encap- sulated into a hdlc frame and transmitted to the remote terminal equipment. 101 txds1clk_24 i transmit ds1/e1 clock input - channel 24: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_24" input pin. 102 txds1data_23/ txhdlcdata_3 i transmit ds1 data input - channel 23/transmit hdlc controller block input - bit 3: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1 data input - channel 23 (multiplexer/de-multiplexer mode): this input pin accepts a ds1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_1 signal. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts ds2 data if m12 mux # 6 is bypassed. transmit hdlc controller block input - bit 3: (high speed hdlc controller mode) this input pin, along with txhdlc_data[0:2] and txhdlc_data[4:7] function as the "transmit hdlc controller byte input interface. data that resides on this bus, during the rising edge of "txhdlcclk" is latched into the "transmit hdlc controller block" and will be encap- sulated into a hdlc frame and transmitted to the remote terminal equipment. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 19 103 txds1clk_23 i transmit ds1 clock input - channel 23: this input pin accepts a ds1 (1.544mhz) clock signal from the termi- nal equipment. the falling edge of this signal is used to sample the data at the "txds1data_23" input pin. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts a ds2 rate clock signal (6.312mhz) if m12 mux # 6 is bypassed. 104 txds1data_22/ txhdlcdata_2 i transmit ds1/e1 data input - channel 22/transmit hdlc control- ler block input - bit 2: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1/e1 data input - channel 22 (multiplexer/de-multi- plexer mode) this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_22 signal. transmit hdlc controller block input - bit 2: (high speed hdlc controller mode) this input pin, along with txhdlc_data[0:1 and txhdlc_data[3:7] function as the "transmit hdlc controller byte input interface. data that resides on this bus, during the rising edge of "txhdlcclk" is latched into the "transmit hdlc controller block" and will be encap- sulated into a hdlc frame and transmitted to the remote terminal equipment. 105 txds1clk_22 i transmit ds1/e1 clock input - channel 22: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_22" input pin. 106 txds1data_21/ txhdlcdata_1 i transmit ds1/e1 data input - channel 21/transmit hdlc control- ler block input - bit 1: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1/e1 data input - channel 21 (multiplexer/de-multi- plexer mode): this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_21 signal. transmit hdlc controller block input - bit 1: (high speed hdlc controller mode) this input pin, along with txhdlc_data_0 and txhdlc_data[2:7] function as the "transmit hdlc controller byte input interface. data that resides on this bus, during the rising edge of "txhdlcclk" is latched into the "transmit hdlc controller block" and will be encap- sulated into a hdlc frame and transmitted to the remote terminal equipment. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 20 107 txds1clk_21 transmit ds1/e1 clock input - channel 21: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_21" input pin. 108 txds1data_20/ txhdlcdata_0 i transmit ds1/e1 data input - channel 20/transmit hdlc control- ler block input - bit 0: the funtion of this output pin depends upon whether the XRT72L13 is operating in the "multiplexer/de-multiplexer" mode or in the "high speed hdlc controller" mode. transmit ds1/e1 data input - channel 20 (multiplexer/de-multi- plexer mode) this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_20 signal. transmit hdlc controller block input - bit 0: (high speed hdlc controller mode) this input pin, along with txhdlc_data[1:7] function as the "transmit hdlc controller byte input interface. data that resides on this bus, during the rising edge of "txhdlcclk" is latched into the "transmit hdlc controller block" and will be encapsulated into a hdlc frame and transmitted to the remote terminal equipment. 109 txds1clk_20 i transmit ds1 clock input - channel 20: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_20" input pin. 110 txds1data_19 i transmit ds1 data input - channel 19: this input pin accepts a ds1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_19 signal. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts ds2 data if m12 mux # 5 is bypassed. 111 txds1clk_19 i transmit ds1 clock input - channel 19: this input pin accepts a ds1 (1.544mhz) clock signal from the termi- nal equipment. the falling edge of this signal is used to sample the data at the "txds1data_19" input pin. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts a ds2 rate clock signal (6.312mhz) if m12 mux # 5 is bypassed. 112 txds1data_18 i transmit ds1/e1 data input - channel 18: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_18 signal. 113 txds1clk_18 i transmit ds1/e1 clock input - channel 18: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_18" input pin. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 21 114 txds1data_17 i transmit ds1/e1 data input - channel 17: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_17 signal. 115 txds1clk_17 i transmit ds1/e1 clock input - channel 17: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_17" input pin. 116 txds1data_16 i transmit ds1/e1 data input - channel 16: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_16 signal. 117 txds1clk_16 i transmit ds1/e1 clock input - channel 16: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_1" input pin. 118 vdd **** power supply pin 119 txds1data_15 i transmit ds1 data input - channel 15: this input pin accepts a ds1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_15 signal. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts ds2 data if m12 mux # 4 is bypassed. 120 txds1clk_15 i transmit ds1 clock input - channel 15: this input pin accepts a ds1 (1.544mhz) clock signal from the termi- nal equipment. the falling edge of this signal is used to sample the data at the "txds1data_15" input pin. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts a ds2 rate clock signal (6.312mhz) if m12 mux # 4 is bypassed. 121 txds1data_14 i transmit ds1/e1 data input - channel 14: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_14 signal. 122 txds1clk_14 i transmit ds1/e1 clock input - channel 14: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_14" input pin. 123 txds1data_13 i transmit ds1/e1 data input - channel 13: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_13 signal. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 22 124 txds1clk_13 i transmit ds1/e1 clock input - channel 13: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_13" input pin. 125 txds1data_12 i transmit ds1/e1 data input - channel 12: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_12 signal. 126 txds1clk_12 i transmit ds1/e1 clock input - channel 12: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_12" input pin. 127 txds1data_11 i transmit ds1 data input - channel 11: this input pin accepts a ds1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_11 signal. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts ds2 data if m12 mux # 3 is bypassed. 128 gnd **** ground pin 129 txds1clk_11 i transmit ds1 clock input - channel 11: this input pin accepts a ds1 (1.544mhz) clock signal from the termi- nal equipment. the falling edge of this signal is used to sample the data at the "txds1data_11" input pin. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts a ds2 rate clock signal (6.312mhz) if m12 mux # 3 is bypassed. 130 txds1data_10 i transmit ds1/e1 data input - channel 10: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_10 signal. 131 txds1clk_10 i transmit ds1/e1 clock input - channel 10: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_10" input pin. 132 txds1data_9 i transmit ds1/e1 data input - channel 9: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_9 signal. 133 txds1clk_9 i transmit ds1/e1 clock input - channel 9: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_9" input pin. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 23 134 txds1data_8 i transmit ds1/e1 data input - channel 8: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_8 signal. 135 txds1clk_8 i transmit ds1/e1 clock input - channel 8: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_8" input pin. 136 txds1data_7 i transmit ds1 data input - channel 7: this input pin accepts a ds1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_7 signal. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts ds2 data if m12 mux # 2 is bypassed. 137 vdd **** power supply pin 138 txds1clk_7 i transmit ds1 clock input - channel 7: this input pin accepts a ds1 (1.544mhz) clock signal from the termi- nal equipment. the falling edge of this signal is used to sample the data at the "txds1data_7" input pin. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts a ds2 rate clock signal (6.312mhz) if m12 mux # 2 is bypassed. 139 txds1data_6 i transmit ds1/e1 data input - channel 6: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_6 signal. 140 txds1clk_6 i transmit ds1/e1 clock input - channel 6: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_6" input pin. 141 txds1data_5 i transmit ds1/e1 data input - channel 5: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_5 signal. 142 txds1clk_5 i transmit ds1/e1 clock input - channel 5: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_5" input pin. 143 txds1data_4 i transmit ds1/e1 data input - channel 4: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_4 signal. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 24 144 txds1clk_4 i transmit ds1/e1 clock input - channel 4: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_4" input pin. 145 txds1data_3 i transmit ds1 data input - channel 3: this input pin accepts a ds1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_3 signal. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts ds2 data if m12 mux # 1 is bypassed. 146 gnd **** ground pin 147 txds1clk_3 i transmit ds1 clock input - channel 3: this input pin accepts a ds1 (1.544mhz) clock signal from the termi- nal equipment. the falling edge of this signal is used to sample the data at the "txds1data_3" input pin. n otes : 1. this input pin is inactive if the corresponding m12 mux is multiplexing 3 e1's into an itu-t g.747 data stream. 2. this input pin accepts a ds2 rate clock signal (6.312mhz) if m12 mux # 1 is bypassed. 148 txds1data_2 i transmit ds1/e1 data input - channel 2: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_2 signal. 149 txds1clk_2 i transmit ds1/e1 clock input - channel 2: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_2" input pin. 150 txds1data_1 i transmit ds1/e1 data input - channel 1: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_1 signal. 151 txds1clk_1 i transmit ds1/e1 clock input - channel 1: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_1" input pin. 152 txds1data_0 i transmit ds1/e1 data input - channel 1: this input pin accepts either a ds1 or e1 signal from the terminal equipment. this input pin is sampled upon the "falling edge" of the txds1clk_0 signal. 153 txds1clk_0 i transmit ds1/e1 clock input - channel 1: this input pin accepts either a ds1 (1.544mhz) or an e1 (2.048mhz) clock signal from the terminal equipment. the falling edge of this sig- nal is used to sample the data at the "txds1data_0" input pin. 154 ds2inclk i transmit ds2 clock input pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 25 155 ds2outclk o transmit ds2 clock output 156 txframeref i transmit framer reference input: this input pin functions as the "transmit frame generation" reference signal, if the XRT72L13 has been configured to operate in the "local- time/frame slave" mode. if the XRT72L13 has been configured to operate in the "local-time/frame-slave" mode, then the user's termi- nal equipment is expected to apply a pulse (to this input pin) once every 106.4 microseconds. in the "local-time/frame-slave" mode, the transmit section of the XRT72L13 m13 multiplexer/framer ic will initiate its generation of a new "outbound" ds3 frame, upon the rising edge of this signal. n ote : the user can configure the XRT72L13 m13 multiplexer/framer ic to operate in the "local time/frame slave" mode by writing "xxxx xx01" into the "operating mode" register (address = 0x00). 157 txframe o transmit end of ds3 frame indicator: .the transmit section of the XRT72L13 will pulse this output pin "high" (for one bit-period), when the transmit payload data input interface is processing the last bit of a given ds3 frame. the purpose of this output pin is to alert the terminal equipment that it needs to begin transmission of a new ds3 frame to the XRT72L13 (e.g., to permit the XRT72L13 to maintain transmit ds3 framing align- ment control over the terminal equipment). 158 txinclk i transmit framer reference clock input. this input pin functions as the "timing reference" for the transmit section of the "clear channel ds3 framer" block within XRT72L13 m13 multiplexer/framer ic; if the device has been configured to oper- ate in the "local-time" mode. further, if the XRT72L13 m13 multi- plexer/framer ic has been configured to operate in the "local-time" mode, the "transmit payload data input interface will sample the data at the txser input pin, upon the rising edge of "txinclk". n otes : 1. the user should apply a 44.736mhz clock signal to this input pin. 2. the user can configure the XRT72L13 m13 multiplexer/ framer ic to operate in the "local-time" mode by writing "xxxx xx01" or "xxxx xx1x" into the "operating mode" register (address = 0x00). 159 txnibframe o transmit frame boundary indicator - nibble/parallel interface this output pin pulses "high" when the last nibble of a given ds3 frame is expected at the txnib[3:0] input pins. the purpose of this output pin is to alert the terminal equipment that it needs to begin transmission of a new ds3 frame to the XRT72L13. n ote : this pin is only used for clear-channel framer applications. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 26 160 txohind/ txplclkenb o transmit overhead data indicator/transmit payload data clock enable output.. the funtion of this output pin depends upon whether the XRT72L13 is operating in the clear-channel or the high-speed hdlc control- ler mode. clear channel framer mode. this output pin will pulse "high" one-bit period prior to the time that the transmit section of the XRT72L13 will be processing an overhead bit. the purpose of this output pin is to warn the terminal equipment that, during the very next bit-period, the XRT72L13 is going to be pro- cessing an "overhead" bit and will be ignoring any data that is applied to the "txser" input pin. n ote : this output pin is only active if the XRT72L13 is operating in the "serial" mode. this output pin will be pulled "low" if the device is operating in the "nibble-parallel" mode. high speed hdlc controller mode. 161 txnibclk o transmit nibble clock signal if the user opts to operate the XRT72L13 in the nibble-parallel mode, then the XRT72L13 will derive this clock signal from either the txinclk or the rxlineclk signal (depending upon which signal is selected as the timing reference). the user is advised to configure the terminal equipment to output the outbound payload data (to the XRT72L13 framer ic) onto the txnib[3:0] input pins, upon the rising edge of this clock signal. n otes : 1. the XRT72L13 m13/framer ic will output 1176 clock edges (to the terminal equipment) for each outbound ds3 frame. 2. this pin is only active for clear-channel framer applica- tions. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 27 162 txnib_0/ txser i transmit nibble-parallel payload data input -0/transmit serial payload data input pin: the exact function of this pin depends upon whether the XRT72L13 is operating in the "serial" or "nibble-parallel" interface mode. txnib_0 - (nibble parallel interface mode): the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over a ds3 transport medium. the framer ic will take data, applied to this pin (along with txnib1, txnib2, and txnib3), and insert it into an outbound "ds3" frame. the XRT72L13 will sample the data that is at these input pins, upon the rising edge of the "txnibclk" signal. transmit serial payload data input pin - (serial interface mode): the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over a ds3 transport medium. the framer ic will take data, applied to this pin, and insert it into an outbound "ds3" frame. if the XRT72L13 m13 multiplexer/framer ic has been configured to operate in the "local time" mode, then it will sample the data (on this pin) upon the rising edge of "txinclk". if the XRT72L13 m13 multi- plexer/framer ic has been configured to operate in the "loop-time" mode, then it will sample the data (on this pin) upon the rising edge of "rxoutclk". n ote : this input pin is active only if the serial mode has been selected. 163 txnib_1 i transmit nibble-paralle payload data input -1: the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over a ds3 transport medium. the framer ic will take data, applied to this pin, and insert it into an outbound "ds3" frame. the XRT72L13 will sample the data that is at these input pins, upon the rising edge of the "txnibclk" signal. n ote : this input pin is active only if the nibble/parallel mode has been selected. 164 vdd **** power supply pin 165 txnib_2 i transmit nibble-parallel payload data input -2: the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over a ds3 transport medium. the framer ic will take data, applied to this pin, and insert it into an outbound " ds3" frame. the XRT72L13 will sample the data that is at these input pins, upon the rising edge of the "txnibclk" signal. n ote : this input pin is active only if the nibble/parallel mode has been selected. 166 txnib_3 i transmit nibble-parallel payload data input -3: the terminal equipment is expected to input data, that is intended to be transmitted to the remote terminal, over an ds3 transport medium. the framer ic will take data, applied to this pin (along with txnib1, txnib2, and txnib3), and insert it into an outbound ds3" frame. the XRT72L13 will sample the data that is at these input pins, upon the rising edge of the "txnibclk" signal. note: this input pin is active only if the nibble/parallel mode has been selected. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 28 167 txohins i transmit overhead data insert input. asserting this input signal (e.g., setting it "high") enables the transmit overhead data input interface to accept "overhead" data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the "txoh" input pin, on the falling edge of the "txohclk" output signal. conversely, setting this pin "low" configures the "transmit overhead data input interface" to not sample (e.g., ignore) the data at the "txoh" input pin, on the falling edge of the "txohclk" output signal. n otes : 1. if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the "transmit overhead data input interface" (e.g., if the terminal equipment asserts the "txohins" signal, at a time when one of these "non-insert- able" overhead bits are being processed); that particular insertion effort will be ignored. 2. this pin is only used in clear-channel framer applications. 168 txaisen i transmit ais command input: setting this input pin "high" configures the XRT72L13 to transmit an ais (alarm indication signal) pattern to the remote terminal. setting this input pin low configures the transmit section to generate ds3 traffic in a normal manner. 169 txohframe o transmit overhead frame: this output pin pulses "high" when the transmit overhead data input interface block is expecting the first overhead bit, within a ds3 frame to be applied to the txoh input pin. this pin is "high" for one clock period of txohclk. 170 txohenable o transmit overhead frame enable: the XRT72L13 will assert this signal, for one txinclk period, just prior to the instant that the transmit overhead data input interface will be sampling and processing an overhead bit. if the terminal equipment intends to insert its own value for an over- head bit, into the outbound ds3 frame, it is expected to sample the state of this signal, upon the falling edge of txinclk. upon sampling the txohenable high, the terminal equipment should (1) place the desired value of the overhead bit, onto the txoh input pin and (2) assert the txohins input pin. the transmit overhead data input interface block will sample and latch the data on the txoh signal, upon the rising edge of the very next txinclk input signal. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 29 171 txohclk o transmit overhead clock this output signal serves two purposes: 1. the transmit overhead data input interface block will provide a rising clock edge on this signal, one bit-period prior to the start to the instant that the transmit overhead data input interface block is pro- cessing an overhead bit. 2. the transmit overhead data input interface will sample the data at the txoh input pin, on the falling edge of this clock signal (provided that the txohins input pin is high). n ote : the transmit overhead data input interface block will supply a clock edge for all overhead bits within the ds3 frame (via the txo- hclk output signal). this includes those overhead bits that the transmit overhead data input interface will not accept from the ter- minal equipment. 172 txoh o transmit overhead input pin the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the "overhead" bit position within the very next "outbound" ds3 frame. if the "txohins" pin is pulled "high", the transmit overhead data input interface will sample the data at this input pin (txoh), on the falling edge of the "txohclk" output pin. conversely, if the "txohins" pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored 173 txneg o transmit negative polarity pulse: the exact role of this output pin depends upon whether the framer is operating in the unipolar or bipolar mode. unipolar mode: this output signal pulses "high" for one bit period, at the end of each "outbound" ds3 frame. this output signal is at a logic "low" for all of the remaining bit-periods of the "outbound" ds3 frames bipolar mode: this output pin functions as one of the two dual-rail output signals that commands the sequence of pulses to be driven on the line. txpos is the other output pin. this input is typically connected to the tndata input of the external ds3/e3 line interface unit ic. when this output is asserted, it will command the liu to generate a negative polarity pulse on the line. 174 txpos o transmit positive polarity pulse: the exact role of this output pin depends upon whether the framer is operating in the unipolar or bipolar mode. unipolar mode: this output pin functions as the "single-rail" output signal for the "outbound" ds3 data stream. the signal, at this output pin, will be updated on the "user-selected" edge of the txlineclk signal. bipolar mode: this output pin functions as one of the two dual rail output signals that commands the sequence of pulses to be driven on the line. txneg is the other output pin. this input is typically connected to the tpdata input of the external ds3 or e3 line interface unit ic. when this out- put is asserted, it will command the liu to generate a positive polarity pulse on the line. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 30 175 txlineclk o transmit line interface clock: this clock signal is output to the line interface unit, along with the txpos and txneg signals. the purpose of this output clock signal is to provide the liu with timing information that it can use to generate the ami pulses and deliver them over the transmission medium to the far-end receiver. the user can configure the source of this clock to be either the rxlineclk (from the receiver portion of the framer) or the txinclk input. the nominal frequency of this clock signal is 34.368 mhz. 176 req o receive equalization enable/disable select output pin - (to be connected to the xrt7300 ds3/e3 line interface unit ic). this output pin is intended to be connected to the reqb input pin of the xrt7300 ds3/e3 line interface unit ic. the user can control the state of this output pin by writing a '0' or '1' to bit 5 (reqb) within the line interface driver register (address = 0x80). if the user com- mands this signal to toggle "high" then the internal receive equalizer (within the xrt7300) will be disabled. conversely, if the user com- mands this output signal to toggle "low", then the internal receive equalizer (within the xrt7300) will be enabled. for information on the criteria that should be used when deciding whether to bypass the equalization circuitry or not, please consult the "xrt7300 ds3/e3 line interface unit" data sheet. writing a "1" to bit 5 of the line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". note: if the customer is not using the xrt7300 ds3/e3 line inter- face unit ic, then he/she can use this output pin for a variety of other purposes. 177 taos o "transmit all ones signal" (taos) command (for the xrt7300 line interface unit ic). this output pin is intended to be connected to the taos input pin of the xr-t7300 ds3/e3 line interface unit ic. the user can control the state of this output pin by writing a '0' or '1' to bit 4 (taos) of the line interface drive register (address = 0x80). if the user commands this signal to toggle "high" then it will force the xrt7300 line interface unit ic to transmit an "all ones" pattern onto the line. conversely, if the user commands this output signal to toggle "low" then the xr- t7300 ds3/e3 line interface unit ic will proceed to transmit data based upon the pattern that it receives via the txpos and txneg output pins. writing a "1" to bit 4 of the line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". n ote : this output pin can be used for a variety of other purposes if the xrt7300 ds3/e3 liu is not used. 178 gnd **** ground pin pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 31 179 encodis o encoder (hdb3) disable output pin (intended to be connected to the xrt7300 ds3/e3 line interface unit ic). this output pin is intended to be connected to the encodis input pin of the xrt7300 ds3/e3 line interface unit ic. the user can control the state of this output pin by writing a "0" or "1" to bit 3 (encodis) within the line interface driver register (address = 0x80). if the user com- mands this signal to toggle "high" then it will disable the b3zs encoder circuitry within the xrt7300 ic. conversely, if the user com- mands this output signal to toggle "low", then the b3zs encoder cir- cuitry, within the xrt7300 ic will be enabled. writing a "1" to bit 3 of the line interface driver register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". n otes : 1. the user is advised to disable the b3zs encoder (within the xrt7300 ic) if the XRT72L13 m13 multiplexer/framer ic has been configured to operate in the b3zs/hdb3 line code. 2. if the customer is not using the xrt7300 ds3/e3 line inter- face unit ic, then this output pin can be used for a variety of other purposes. 180 txlev o transmit line build-out enable/disable select output (to be con- nected to the xrt7300 ds3/e3 line interface unit ic). this output pin is intended to be connected to the txlev input pin of the xrt7300 ds3/e3 line interface unit ic. the user can control the state of this output pin by writing a "0" or a "1" to bit 2 (txlev) within the line interface driver register (address = 0x80). writing a "1" to bit 2 of the line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". if the user commands this signal to toggle "high" then the "transmit line build-out" circuit (within the xrt7300) will be disabled. in this mode, the xrt7300 will output unshaped (e.g., square) pulses onto the line (via the ttip and tring output pins). conversely, if the user commands this signal to toggle "low" then the "transmit line build-out" circuit (within the xrt7300) will be disabled. in this mode, the xrt7300 will output shaped (e.g., more rounded) pulses onto the line (via the ttip and tring output pins). in order to comply with the "dsx-3 isolated pulse template require- ment" (per bellcore gr-499-core), the user is advised to command this output pin to be "high" if the cable length (between the transmit output of the xrt7300 and the dsx-3 cross connect system) is greater than 225 feet. conversely, the user is advised to command this output pin to be "low" if the cable length (between the transmit output of the xrt7300 and the dsx-3 cross connect system) is less than 225 feet. n ote : this output pin can be used for a variety of other purposes if the xrt7300 ds3/e3 liu is not used. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 32 181 rloop o remote loopback output pin (to the xrt7300 ds3/e3 line inter- face unit ic). this output pin is intended to be connected to the rloop input pin of the xrt7300 ds3/e3 line interface unit ic. the user can command this signal to toggle "high" and, in turn, force the xrt7300 ds3/e3 line interface unit ic into the "remote loopback" mode. conversely, the user can command this signal to toggle "low" and allow the xrt7300 to operate in the normal mode. (for a detailed description of the xr-t7300 ds3/e3 line interface unit ic's operation during remote loopback, please see the xr-t7300 ds3/sts-1/ e3 line interface unit ic's data sheet). writing a "1" to bit 1 of the "line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause the rloop output to toggle "low". n ote : this output pin can be used for a variety of other purposes if the xrt7300 ds3/e3 liu is not used. 182 lloop o local loopback output pin (to the xrt7300 ds3/e3 line inter- face unit ic). this output pin is intended to be connected to the lloop input pin of the xrt7300 liu ic. the user can command this signal to toggle "high" and, in turn, force the liu into the "local loopback" mode. (for a detailed description of the xrt7300 ds3/e3 line interface unit ic's operation during local loopback, please see the xrt7300 ds3/ sts-1/e3 line interface unit ic's data sheet). writing a "1" to bit 1 of the "line interface drive register (address = 0x80) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause the rloop output to toggle "low". n ote : this output pin can be used for a variety of other purposes if the xrt7300 ds3/e3 liu is not used. 183 dmo o "drive monitor output" input (from the xrt7300 ds3 line inter- face unit ic). this input pin is intended to be tied to the dmo output pin of the xrt7300 ds3 line interface unit ic. the user can determine the state of this input pin by reading bit 2 (dmo) within the line interface scan register (address = 0x81). if this input signal is "high", then it means that the drive monitor circuitry (within the xrt7300 ds3 line interface unit ic) has not detected any bipolar signals at the mtip and mring inputs within the last 128 32 bit-periods. if this input signal is "low", then it means that bipolar signals are being detected at the mtip and mring input pins of the xrt7300. n ote : this output pin can be used for a variety of other purposes if the xrt7300 ds3/e3 liu is not used. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 33 184 rlol i receive loss of lock indicator - from the xrt7300 ds3/e3 line interface unit ic. this input pin is intended to be connected to the rlol (receive loss of lock) output pin of the xrt7300 line interface unit ic. the user can monitor the state of this pin by reading the state of bit 1 (rlol) within the line interface scan register (address = 0x81). if this input pin is "low", then it means that the "clock recovery phase- locked-loop" circuitry, within the xrt7300 is properly locked onto the incoming ds3 data-stream; and is properly recovering clock and data from this ds3 data-stream. however, if this input pin is "high", then it means that the phase-locked-loop circuitry, within the xrt7300 has lost lock with the incoming ds3 data-stream, and is not properly recovering clock and data. for more information on the operation of the xrt7300 ds3/e3 line interface unit ic, please consult the "xrt7300 ds3/e3 line interface unit" data sheet. n ote : this output pin can be used for a variety of other purposes if the xrt7300 ds3/e3 liu is not used. 185 extlos i receive los (loss of signal) indicator input (from xrt7300 liu ic). this input pin is intended to be connected to the rlos (receive loss of signal) output pin of the xrt7300 line interface unit ic. the user can monitor the state of this pin by reading the state of bit 0 (rlos) within the line interface scan register (address = 0x81). if this input pin is "low", then it means that the xrt7300 is currently not declaring an "los (loss of signal) condition. however, if this input pin is "high", then it means that the xrt7300 is currently declar- ing an los (loss of signal) condition. for more information on the operation of the xr-t7300 ds3/e3 line receiver ic, please consult the "xrt7300 ds3/sts-1/e3 line inter- face unit ic" data sheet. n ote : asserting the rlos input pin will cause the XRT72L13 m13 multiplexer/framer to declare an "los (loss of signal) condition. therefore, this input pin should not be used as a general purpose input. 186 vdd **** power supply pin 187 rxvcoup o receive vco frequency increase: 188 rxvcodown o receive vco frequency decrease: 189 rxlineclk i receiver liu (recovered) clock: this input signal serves three purposes: the receive framer uses it to sample and "latch" the signals at the rxpos and rxneg input pins (into the receive framer circuitry). this input signal functions as the timing reference for the receive framer block. the transmit framer block can be configured to use this input signal as its timing reference. n ote : this signal is the recovered clock from the external ds3 liu (line interface unit) ic, which is derived from the incoming ds3 data. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 34 190 rxpos i receive positive data input: the exact role of this input pin depends upon whether the framer is operating in the unipolar or bipolar mode. unipolar mode: this input pin functions as the "single-rail" input for the "incoming" ds3 data stream. the signal at this input pin will be sampled and latched (into the receive framer block) on the "user-selected" edge of the rxlineclk signal. bipolar mode: this input functions as one of the dual rail inputs for the incoming ami/b3zs encoded ds3 data that has been received from an exter- nal line interface unit (liu) ic. rxneg functions as the other dual rail input for the framer. when this input pin is asserted, it means that the liu has received a "positive polarity" pulse from the line. 191 rxneg i receive negative data input: the exact role of this input pin depends upon whether the framer is operating in the unipolar or bipolar mode. unipolar mode: this input pin is inactive, and should be pulled ("low" or "high") when the framer is operating in the unipolar mode. bipolar mode: this input pin functions as one of the dual rail inputs for the incoming ami/b3zs encoded ds3 data that has been received from an exter- nal line interface unit (liu) ic. rxpos functions as the other dual rail input for the framer. when this input pin is asserted, it means that the liu has received a "negative polarity" pulse from the line. 192 rxoh o receive overhead output port: all overhead bits, which are received via the "receive section" of the framer ic; will be output via this output pin, upon the rising edge of rxohclk. 193 rxohenable o receive overhead enable indicator: the XRT72L13 will assert this output signal for one rxoutclk period when it is safe for the terminal equipment to sample the data on the rxoh output pin. 194 rxohclk o receive overhead clock: the XRT72L13 will output the overhead bits (within the incoming ds3 frames), via the "rxoh" output pin, upon the falling edge of this clock signal. as a consequence, the "user's data link equipment" should use the rising edge of this clock signal to sample the data on both the "rxoh" and "rxohframe" output pins. n ote : this clock signal is always active. 195 rxohframe o receive overhead frame boundary indicator: this output pin pulses "high" whenever the receive overhead data output interface outputs the first overhead bit (or nibble) of a new ds3 frame. 196 rxlos o receive section - loss of signal output indicator: this pin is asserted when the receive section encounters a string of 180 consecutive 0's via the rxpos and rxneg pins. this pin will be negated once the receive section has detected at least 60 pulses within 180 bit-periods. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 35 197 rxnib_3/ rxred o receive nibble output - bit 3/receive red alarm indicator: the funtion of this output pin depends upon whether the XRT72L13 is operating in the clear-channel framing/nibble-parallel mode or not.. clear channel framer applications - receive nibble output - bit 3 the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin along with rxnib0, rxnib1 and rxnib2. the data at this pin is updated on the rising edge of the rxclk output signal. n ote : this output pin is active only if the nibble-parallel mode has been selected. all other modes - receiver red alarm indicator: the framer asserts this output pin to denote that one of the following events has been detected by the receive framer: ? los - loss of signal condition ? oof - out of frame condition ? ais - alarm indication signal detection 198 rxnib_2/ rxais o receive nibble output - bit 2/receive ais condition indicator: the funtion of this output pin depends upon whether the XRT72L13 is operating in the clear-channel-framing/nibble-parallel modes or not. clear-channel framing/nibble-parallel modes - receive nibble output - bit 2 the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin along with rxnib0, rxnib1 and rxnib2. the data at this pin is updated on the rising edge of the rxclk output signal. all other modes - receive "alarm indication signal" output pin: the framer will assert this pin to indicate that the alarm indication signal (ais) has been identified in the receive ds3 data stream. an "ais" is detected if the payload consists of the recurring pattern of 1010... and this pattern persists for 63 m-frames. an additional requirement for ais indication is that the c-bits are set to 0, and the x- bits are set to 1. this pin will be negated when a sufficient number of frames, not exhibiting the "1010..." pattern in the payload has been detected. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 36 199 rxnib_1/rxoof o receive nibble output - bit 1/receive out-of-frame indicator: the funtion of this output pin depends upon whether the XRT72L13 is operating in the clear-channel-framing/nibble-parallel mode or not. clear-channel framing/nibble-parallel mode - receive nibble output - bit 1: the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin along with rxnib0, rxnib2 and rxnib3. the data at this pin is updated on the rising edge of the rxclk output signal. all other modes - receiver "out of frame" indicator: the receive section of the XRT72L13 m13 multiplexer/framer ic will assert this output signal whenever it has declared an "out of frame" (oof) condition with the incoming ds3 frames. this signal is negated when the framer correctly locates the framing alignment bits or bytes and correctly aligns itself with the incoming ds3 frames. 200 gnd **** ground pin 201 rxnib_0/rxser o receive nibble output -bit 0/receive serial output: the funtion of this output pin depends upon whether the XRT72L13 is operating in the clear-channel-framing/nibble-parallel mode or in the clear-channel-framing/serial modes clear-channel framing/nibble-parallel mode - receive nibble output - bit 0: the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin along with rxnib1, rxnib2 and rxnib3. the data at this pin is updated on the rising edge of the rxclk output signal. n ote : in this case, the rxclk output signal is approximately 11.184mhz clear-channel framing/serial mode receive serial output; the framer ic will output "received data (from the remote terminal) to the local terminal equipment via this pin. the data at this pin is updated on the "selected" edge of the rxclk output pin. n otes : 1. for serial-mode applications, the rxclk output signal is 44.736mhz. 2. if the XRT72L13 is operating in the channelized or high- speed hdlc controller modes, then this output pin is in- active. 202 rxoutclk o receive out clock - transmit terminal interface clock for loop- timing: this clock signal functions as the "terminal interface" clock source, if the XRT72L13 m13 multiplexer/framer ic is operating in the "loop- timing" mode. in this mode, the transmitting terminal equipment is expected to input data to the framer ic, via the txser input pin, upon the rising edge of this clock signal. the XRT72L13 will use the rising edge of this clock signal to sample the data at the txser input. this clock signal is a buffered version of the rxlineclk signal. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 37 203 rxohind/ rxplclkenb o receive overhead bit indicator: this output pin pulses "high" whenever an "overhead" bit is being out- put via the "rxser" output pin, by the "receive payload data output interface" block. the purpose of this output pin is to alert the "receive terminal equip- ment" that an overhead bit is being output via the "rxser" output pin, and that this data should be ignored. 204 rxclk o receive clock output signal for serial and nibble/parallel data interface: the exact behavior of this signal depends upon whether the XRT72L13 is operating in the clear-channel-framing/serial or clear-channel-framing/nibble-parallel modes. clear-channel framing - serial mode operation: in the "serial" mode, this signal is a 44.736mhz clock output signal. the receive payload data output interface will update the data via the rxser output pin, upon the rising edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the "rxser" pin, upon the falling edge of this clock signal. clear-channel framing - nibble-parallel mode operation in this nibble-parallel mode, the XRT72L13 will derive this clock sig- nal, from the rxlineclk signal. the XRT72L13 will pulse this clock signal 1176 times for each "inbound" ds3 frame. the receive pay- load data output interface will update the data, on the "rxnib[3:0]" output pins upon the falling edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the "rxnib[3:0] output pins, upon the rising edge of this clock signal 205 rxframe o receive boundary of ds3 frame output indicator: the funtion of this output pin depends upon whether the XRT72L13 framer ic is operating in the clear-channel-framing/serial or clear-channel-framing/nibble-parallel modes. clear-channel framing - serial mode operation the receive section of the XRT72L13 will pulse this output pin high (for one bit-period) when the receive payload data output interface block is driving the very first bit of a given given ds3 frame, onto the rxser output pin. clear-channel framing -nibble-parallel operation the receive section of the XRT72L13 will pulse this output pin high (for one nibble-period), when the receive payload data output inter- face block is driving the very first nibble of a given ds3 frame, onto the rxnib[3:0] output pins. 206 rxinclk i receive input clock: 207 rxds1data_27 o receive ds1 data output - channel 27: this pin outputs a ds1 signal from the m12 multiplexer. each bit, within the ds1 data stream is output upon the rising edge of rxds1clk_27. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output the contents of ds2 channel # 7, if m12 mux # 7 is bypassed. pin descriptions p in #n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 38 208 rxds1clk_27 o receive ds1 clock output - channel 27: this pin outputs either a ds1 (1.544mhz) clock signal to the terminal equipment. the XRT72L13 will update the data on the "rxds1data_27" line, upon the rising edge of this signal. n otes : 1. this output pin is inactive if the corresponding m12 demux is de-multiplexing an itu-t g.747 data stream. 2. this pin will output a ds2 rate clock signal (6.312mhz) if m12 # 7 is bypassed. pin descriptions p in #n ame t ype d escription ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 39 electrical characteristics absolute maximums a bsolute m aximum r atings : power supply......................................... - 0.5v to +3.465v power dissipation pqfp package........................... ???w storage temperature ...............................-65c to 150c input voltage (any pin) .....................-0.5v to vdd + 0. 5v voltage at any pin .......................... -0.5v to vdd + 0.5v input current (any pin) ...................................... + 100ma dc electrical characteristics test conditions: ta = 25(c, vcc = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions i cc power supply current 180 ma i ll data bus tri-state bus leakage current tbd a v il input low voltage 0.8 v v ih input high voltage 2.0 vcc v v ol output low voltage 0.0 0.4 v v oh output high voltage 2.4 vcc v i oc open drain output leakage current tbd a i ih input high voltage current tbd a v ih = vcc i il input low voltage current tbd a v il = gnd ac electrical characteristics test conditions: ta = 25(c, vcc = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions transmit payload data input interface - loop-timed/serial mode (see figure 2) t 1 payload data (txser) set-up time to rising edge of rxoutclk 6ns t 2 payload data (txser) hold time, from rising edge of rxoutclk 0ns t 3 rxoutclk to txframe output delay 8 ns t 4 rxoutclk to txohind output delay 8 ns transmit payload data input interface - local timed/serial mode (see figure 3) t 5 payload data (txser) set-up time to rising edge of "txinclk" 0ns t 6 payload data (txser) hold time, from rising edge of "txinclk" 2.5 ns t 7 "txframeref" set-up time to rising edge of "txinclk" 0 ns framer ic is "frame slave" XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 40 t 8 "txframeref" hold-time, from rising edge of "txin- clk" 2.3 ns frame ic is "frame slave" t 9 "txinclk" to "txohind" output delay 14 ns t 10 "txinclk" to "txframe" output delay 14 ns transmit payload data input interface - looped-timed/nibble mode (see figure 4) t 11 payload data set-up time to "latching edge" of rxoutclk 6ns transmit payload data input interface - looped-timed/nibble mode (see figure 4) t 12 payload data hold time, from "latching edge" of rxoutclk 0 t 13 txnibclk to txnibframe output delay 8 ns transmit payload data input interface - local-timed/nibble mode (see figure 5) t 14 payload nibble set-up time, to "latching edge" of "txinclk" 0ns t 15 payload nibble hold time, from "latching edge" of "txinclk" 15 ns t 16 txframeref set-up time, to "latching edge" of "txin- clk" 0 ns frame ic is "frame slave" t 17 txframeref hold time, from "latching edge" of "txin- clk" 15 ns frame ic is "frame slave" t 18 "txnibclk" to "txnibframe" output delay time 21 ns ac electrical characteristics test conditions: ta = 25(c, vcc = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions ac electrical characteristics (cont.) test conditions: ta = 25(c, vcc = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions transmit overhead input interface timing - method 1 (see figure 6) t 21 "txohclk" to "txohframe" output delay 0 ns t 22 "txohins" set-up time, to falling edge of "txohclk" 0 ns t 23 "txohins" hold time, from falling edge of "txohclk" 0 ns t 24 "txoh" data set-up time, to falling edge of "txo- hclk" 0ns t 25 "txoh" data hold time, from falling edge of "txo- hclk" 0ns transmit overhead data input interface - method 2 (see figure 7) t 26 txohins to txinclk (rising edge) set-up time 0 ns t 27 txinclk clock rising edge to txohins hold-time 0 ns ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 41 t 28 txoh to txinclk rising edge set-up time 0 ns t 29a txinclk to txohenable 8 ns transmit liu interface timing (see figure 8 and figure 9) t 30 rising edge of "txlineclk" to rising edge of "txpos" or "txneg" output signal. (framer is configured to output data on "txpos" and "txneg" on rising edge of "txlineclk" 0.6 ns t 31 falling edge of "txlineclk" to rising edge of "txpos" or "txneg" (framer is configured to output data via "txpos" and "txneg" on falling edge of "txlineclk") 0.6 ns f txlineclk period of txlineclk clock signal 44.736 mhz t 32 period of txlineclk 22.36 ns receive liu interface timing (see figure 10 and figure 11) t 38 "rxpos" or "rxneg" set-up time to rising edge of "rxlineclk". (framer is configured to sample data on "rxpos" and "rxneg" input pins, on the rising edge of "rxli- neclk") 0ns t 39 "rxpos" or "rxneg" hold time, from rising edge of "rxlineclk" (framer is configured to sample data on "rxpos" and "rxneg" input pins, on the rising edge of "rxli- neclk") 2.4 ns t 40 "rxpos" or "rxneg" set-up time to falling edge of "rxlineclk". (framer is configured to sample data on "rxpos" and "rxneg" input pins, on the falling edge of "rxli- neclk") 0ns t 41 "rxpos" or "rxneg" hold time, from falling edge of "rxlineclk" (framer is configured to sample data on "rxpos" and "rxneg" input pins, on the falling edge of "rxli- neclk") 2.4 ns receive payload data output inteface timing - serial mode operation (see figure 12) t 50 falling edge of rxclk to "payload data" (rxser) out- put delay 0ns t 51 falling edge of "rxclk" to "rxframe" output delay 1.3 ns t 52 falling edge of "rxclk" to "rxohind" output delay. 2.6 ns receive payload data output interface timing - nibble mode operation (see figure 13) t 53 falling edge of rxclk to rising edge of rxframe output delay 22 ns ac electrical characteristics (cont.) test conditions: ta = 25(c, vcc = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 42 t 54 falling edge of rxclk to rising edge of rxnib[3:0] output delay 22 ns receive overhead data output interface timing - method 1 - using rxohenable (see )figure 14 t 59a falling edge of rxohclk to rxframe output 0ns t 59b falling edge of rxohclk to rxoh output delay 21.3 ns receive overhead data output interface timing - method 2 - using rxohenable (see figure 15) t 60 rising edge of "rxoutclk" to rising edge of "rxohenable" delay. 5.5 ns t 60a falling edge of "rxohframe" to rising edge of "rxohenable" delay 0ns t 60b rxoh data valid to rising edge of "rxohenable" delay ns microprocessor interface - intel (see figure 16) t 64 a8 - a0 setup time to ale_as low 1 ns t 65 a8 - a0 hold time from ale_as low. 2 ns intel type read operations (see figure 16) t 66 rds_ds , wrb_rw pulse width 80 ns t 67 data valid from rds_ds low. 20 ns t 68 data bus floating from rds_ds high 1.0 ns t 69 ale to rd time 20 ns t 701 rd time to "not ready" (e.g., rdy_dtck toggling "low") 12 ns t 70 rd to ready time (e.g., rdy_dtck toggling "high") 65 ns intel type read burst operations (see figure 18) t 76 minimum time between read burst access (e.g., the rising edge of rd to falling edge of rd ) 60 ns intel type write operations (see figure 17 and figure 19) t 71 data setup time to wr _rw high 70 ns t 72 data hold time from wr _rw high 10 ns t 73 high time between reads and/or writes 60 ns t 74 ale to wr time 20 ns t 77 min time between write burst access (e.g., the ris- ing edge of wr to the falling edge of wr ) 60 ns t 770 cs assertion to falling edge of wr_rw 40 ns microprocessor interface - motorola read operations (see figure 20) ac electrical characteristics (cont.) test conditions: ta = 25(c, vcc = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 43 t 78 a8 - a0 setup time to falling edge of ale_as 5 ns t 79 a8 - a0 risinfg edge of rd _ds to rising edge of rdy_dtck delay 0ns t 80 rising edge of rdy_dtck to tri-state of d[7:0] 0 ns microprocessor interface - motorola write operations (see figure 21) t 78 a8 -a0 set-up time to falling edge of ale_as 5 t 81 d[7:0] set-up time to falling edge of rd _ds 10 ns t 82 rising edge of rd _ds to rising edge of rdy_dtck 0 ns reset pulse width - both motorola and intel operations (see figure 24) t 90 reset pulse width 200 ns ac electrical characteristics (cont.) test conditions: ta = 25(c, vcc = 3.3v + 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions f igure 2. t iming d iagram for t ransmit p ayload i nput i nterface , when the XRT72L13 is operating in both the ds3 and l oop -t iming m odes XRT72L13 transmit payload data i/f signals rxoutclk txser txframe txoh_ind payload[4702] payload[4703] x-bit payload[0] ds3 frame number n ds3 frame number n + 1 t1 t2 t3 t4 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 44 . f igure 3. t iming d iagram for the t ransmit p ayload i nput i nterface , when the XRT72L13 is operating in both the ds3/s erial and l ocal -t iming m odes XRT72L13 transmit payload data i/f signals txinclk txser txframeref txoh_ind payload[4702] payload[4703] x-bit payload[1] ds3 frame number n ds3 frame number n + 1 t5 t6 t7 t8 t9 t10 f igure 4. t iming d iagram for the t ransmit p ayload d ata i nput i nterface , when the XRT72L13 is oper - ating in both the ds3/n ibble and l ooped -t iming m odes rxoutclk txnibframe txnibclk txnib[3:0] nibble [1175] nibble [0] sampling edge of XRT72L13 device t11 t12 t13 t13a ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 45 f igure 5. t iming d iagram for the t ransmit p ayload d ata i nput i nterface , when the XRT72L13 is oper - ating in the ds3/n ibble and l ocal -t iming m odes ds3 frame number n ds3 frame number n + 1 txinclk txnibframe txnibclk txnib[3:0] nibble [1175] nibble [0] sampling edge of the XRT72L13 device t14 t15 txframeref t16 t17 t18 f igure 6. t iming d iagram for the t ransmit o verhead d ata i nput i nterface (m ethod 1 a ccess ) txohclk txohins txohframe txoh remaining overhead bits with ds3 frame x bit = 0 x bit = 0 t21 t22 t24 t23 t25 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 46 f igure 7. t iming d iagram for the t ransmit o verhead d ata i nput i nterface (m ethod 2 a ccess ) txinclk txohframe txohenable txohins txoh XRT72L13 samples txoh here. txohenable pulse # 8 x bit = 0 x bit = 0 t26 t27 t28 t29 t29a f igure 8. t ransmit liu i nterface t iming - f ramer is configured to update "t x pos" and "t x neg" on the rising edge of "t x l ine c lk " txlineclk txpos txneg t32 t30 t33 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 47 f igure 9. t ransmit liu i nterface t iming - f ramer is configured to update "t x pos" and "t x neg" on the falling edge of "t x l ine c lk " txlineclk txpos txneg t31 t32 t33 f igure 10. r eceive liu i nterface t iming - f ramer is configured to sample "r x pos" and "r x neg" on the rising edge of "r x l ine c lk " rxlineclk rxpos rxneg t40 t41 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 48 f igure 11. r eceiver liu i nterface t iming - f ramer is configured to sample "r x pos" and "r x neg" on the falling edge of "r x l ine c lk " rxlineclk rxpos rxneg t38 t39 t42 f igure 12. r eceive p ayload d ata o utput i nterface t iming (s erial m ode o peration ) XRT72L13 receive payload data i/f signals rxclk rxser rxframe rxoh_ind payload[4702] payload[4703] x-bit payload[0] t50 t51 t52 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 49 f igure 13. r eceive p ayload d ata o utput i nterface t iming (n ibble m ode o peration ) XRT72L13 receive payload data i/f signals ds3 frame number n ds3 frame number n + 1 rxoutclk rxframe rxclk rxnib[3:0] nibble [0] nibble [1] recommended sampling edge of terminal equipment t53 t54 f igure 14. r eceive o verhead d ata o utput i nterface t iming (m ethod 1 - u sing r x ohc lk ) rxohclk rxohframe rxoh x f1 aic f0 feac t59a t59b XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 50 f igure 15. r eceive o verhead d ata o utput i nterface t iming (m ethod 2 - u sing r x ohe nable ) rxoutclk rxohenable rxohframe rxoh udl f1 x1 f1 aic t60 t60a t60b f igure 16. m icroprocessor i nterface t iming - i ntel t ype p rogrammed i/o r ead o perations ale_as rd_ds a[8:0] cs d[15:0] rdy_dtck not valid valid address of target wr_rw t64 t65 t67 t68 t66 t70 t69 t701 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 51 f igure 17. m icroprocessor i nterface t iming - i ntel t ype p rogrammed i/o w rite o perations ale_as a[8:0] cs d[15:0] wr_rw data to be address of target rd_ds t64 t65 t71 t72 t73 t66 t770 f igure 18. m icroprocessor i nterface t iming - i ntel t ype r ead b urst a ccess o peration ale_as rd_ds a[8:0] cs d[15:0] rdy_dtck not valid valid data at offset =0x01 wr_rw not valid valid data at offset =0x02 address of initial target register (offset = 0x00) t70 t76 t68 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 52 f igure 19. m icroprocessor i nterface t iming - i ntel t ype w rite b urst a ccess o peration ale_as a[8:0] cs d[15:0] not valid valid data at offset =0x01 rd_ds not valid valid data at offset =0x02 wr_rw address of initial target register (offset = 0x00) t76 t68 f igure 20. m icroprocessor i nterface t iming - m otorola t ype p rogrammed i/o r ead o peration wr_rw ale_as rd_ds a[8:0] cs d[7:0] rdy_dtck not valid valid data address of target register t78 t79 t80 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 53 f igure 21. m icroprocessor i nterface t iming - m otorola t ype p rogrammed i/o w rite o peration ale_as a[8:0] cs d[7:0] rd_ds rdy_dtck data to be written address of target register wr_rw t78 t82 t81 f igure 22. m icroprocessor i nterface t iming - m otorola t ype r ead b urst a ccess o peration f igure 23. m icroprocessor i nterface t iming - m otorola t ype w rite b urst a ccess o peration f igure 24. m icroprocessor i nterface t iming - r eset b* p ulse w idth reset t90 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 54 1.0 system description the XRT72L13 m13 multiplexer/framer ic can be configured to operate in any of the following modes: ? multiplexer/de-multiplexer mode. ? clear channel ds3 framer mode. ? high speed hdlc controller mode. each of these modes are briefly described below figure 25 presents a simple block diagram of the XRT72L13 m13 multiplexer/framer ic. 1.1 XRT72L13 operation while in the mul- tiplexer/de-multiplexer mode figure 26, presents a function block diagram of the XRT72L13 when it has been configured to operate in the "multiplexer/de-multiplexer mode. f igure 25. b lock d iagram of the XRT72L13 m13 m ultiplexer /f ramer ic clear channel ds3 framer clear channel ds3 framer microprocessor interface microprocessor interface m12 mux m12 demux m23 mux m23 demux txds1[0: 27] txclk[0:27] rxds1[0: 27] rxclk[0:27] ds2 or g.747 data streams rxpos rxneg txpos txneg rxlineclk txlineclk 32/64 bit de-jitter fifo tx hdlc controller tx hdlc controller rx hdlc controller rx hdlc controller txhdlc[0:7] txhdlcclk send_fcs rxhdlc[0:7] rxhdlcclk rxidle valid_fcs ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 55 when the XRT72L13 has been configured to operate in the "multiplexer/de-multiplexer mode, then the chip will function as follows. 1.1.1 in the transmit direction when the XRT72L13 is operating the "multiplexer/de- multiplexer" mode, it consist of the following blocks. ? seven (7) m12 muxes. ? an m23 mux. ? the clear channel ds3 framer block. 1.1.1.1 operation of the m12 mux each m12 mux can be configured to accept either 4 ds1 signals, 3 e1 signals or a ds2 signal. whenever a given m12 mux is configured to operate in the ds1 mode, then it will accept four (4) ds1 signals (via the txds1data_n input pins) and it will multi- plex these ds1 signals into a ds2 signal. whenever a given m12 mux is configured to operate in the itu-t g.747 mode, then it will accept three (3) e1 signals (via 3 out of 4 of the txds1_n input pins) and it will multiplex these e1 signals into an itu-t g.747 signal. finally, whenever a given m12 mux is configured to operate in the ds2 pass-thru mode, then it will ac- cept a ds2 signal (via one of the txds1data_n in- put pins) and will route these signals to the m23 mux. each m12 mux also consists of a transmit ds2 or itu-t g.747 framer block. as the m12 mux out- puts its ds2 or itu-t g.747 data stream to the m23 mux then the transmit ds2/g.747 framer block will do the following. ? encapsulate the composite data stream (derived from 4 ds1 signals) into an outbound ds2 framing structure. ? set the cxx bits to the appropriate values in order to indicate whether or not a bit-stuff event occurred when creating this particular ds2 frame. f igure 26. f unctional b lock d iagram of the XRT72L13 m13 m ultiplexer /f ramer ic, while operating in the "m ultiplexer /d e -m ultiplexer m ode clear channel ds3 framer clear channel ds3 framer microprocessor interface microprocessor interface m12 mux m12 demux m23 mux m23 demux txds1[0: 27] txclk[0:27] rxds1[0: 27] rxclk[0:27] ds2 or g.747 data streams rxpos rxneg txpos txneg rxlineclk txlineclk 32/64 bit de-jitter fifo XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 56 ? set the x bits (within each outbound ds2 frame) to the appropriate value in order to reflect the ds2 ferf indicator when conditions warrant. the XRT72L13 will accept up to 28 ds1 lines or up to 21 e1 lines as inputs to the m12 multiplexer. associ- ated with each of these ds1 or e1 lines is an input clock signal that the device will use to sample and latch into the device. in all, the m12 mux is capable of muxing 28 ds1 lines into 7 ds2 lines. additionally, the m12 mux is also capable of muxing 21 e1 lines into 7 itu-t g.747 lines. 1.1.1.2 operation of the m23 mux the m23 mux, within the XRT72L13 will accept up to 7 ds2 or itu-t g.747 data streams and will mux these signals into a ds3 data stream. afterwards, this ds3 data stream will be routed to the "clear channel ds3 framer" block for further processing. 1.1.1.3 operation of the "clear channel ds3 framer block" once this data is routed to the "clear channel ds3 framer block", the ds3 data stream will be encapsu- lated into a "outbound" ds3 framing structure, and will be transmitted to an off-chip liu ic. the clear channel ds3 framer block is also responsible for a variety of other necessary function, such as: ? transmission of pmdl (path maintenance data link) messages ? transmission of feac (far-end alarm & control) messages ? transmission of the ferf (far-end receive fail- ure) indicator ? transmission of the febe (far-end block error) indicator ? computation of p and cp-bits 1.1.2 in the receive direction when the XRT72L13 is operating in the "multiplexer/ de-multiplexer" mode, the data (in the "receive di- rection") passes through the following block. ? the clear channel ds3 framer block ? an m23 demux ? an m12 demux 1.1.2.1 operation of the clear channel ds3 framer block the purpose of the "clear channel ds3 framer block" is to perform the following functions: ? to verify the p and cp-bits. ? to terminate the pmdl messages. ? to terminate the feac messages ? to terminate and interpret the ferf indicator ? to terminate and interpret the febe indicator. ? to strip off the "overhead" bytes and route the pay- load portion of the "inbound" ds3 frame to the m23 demux 1.1.2.2 operation of the m23 demux the purpose of the m23 demux, within the XRT72L13 is to accept this ds3 data stream and de- multiplex either 7 ds2 or itu-t g.747 data streams. afterwards, these data streams will be routed to the m12 demux. 1.1.2.3 operation of the m12 demux the purpose of the m12 demux, within the XRT72L13 is to accept either the 7 ds2 or itu-t g.747 data streams and to de-multiplex up to 28 ds1 signals or up to 21 e1 signals. 1.1.3 diagnostic resources available for mux/ demux mode in all, the XRT72L13 supports two types of loop-back modes, while it is configured to operate in the "mux/ demux" mode. ? ds1/e1 tributary loop-back ? ds2/itu-t g.747 tributary loop-back each of these loop-back modes are briefly dis- cussed below. 1.1.3.1 ds1/e1 tributary loop-back figure 27 presents an illustration of the XRT72L13 operating in the "ds1/e1 tributary loop-back mode. ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 57 as figure 27 indicates, a given ds1 line can be com- manded into the "ds1/e1 tributary loop-back" mode. when this happens, then a selected ds1 or e1 line, in the receive path, is looped back into the transmit path. it is important to note that the corre- sponding ds1 or e1 clock signal is also looped back. 1.1.3.2 ds2/itu-t g.747 tributary loop-back mode figure 28 presents an illustration of the XRT72L13 operating in the "ds2/itu-t g.747 tributary loop- back" mode. f igure 27. i llustration of the XRT72L13 o perating in the "ds1/e1 t ributary l oop - back m ode clear channel ds3 framer clear channel ds3 framer microprocessor interface microprocessor interface m12 mux m12 demux m23 mux m23 demux txds1[1: 27] txclk[1:27] rxds1[1: 27] rxclk[1:27] ds2 or g.747 data streams rxpos rxneg txpos txneg rxlineclk txlineclk 32/64 bit de-jitter fifo rxclk_0 rxds1_0 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 58 as figure 28 indicates, a given ds2 or itu-t g.747 line can be commanded into the "ds2/itu-t g.747 tributary loop-back" mode. when this happens, then a selected ds2 or itu-t g.747 data stream (in the receive path) is looped back into the transmit path. it is important to note that the corresponding ds2 or itu-t g.747 clock signal is also looped back into the transmit path. 1.2 XRT72L13 operation while in the "clear channel ds3 framer mode" figure 29 presents a functional block diagram of the XRT72L13 when it has been configured to operate in the "clear channel ds3 framer mode". f igure 28. i llustration of the XRT72L13 o perating in the "ds2/itu-t g.747 t ributary l oop -b ack m ode clear channel ds3 framer clear channel ds3 framer microprocessor interface microprocessor interface m12 mux m12 demux m23 mux m23 demux txds1[0: 27] txclk[0:27] rxds1[0: 27] rxclk[0:27] rxpos rxneg txpos txneg rxlineclk txlineclk 32/64 bit de-jitter fifo ds2/g.747 loop-back path (data and clock are both looped back) ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 59 as this mode implies, the "clear channel ds3 framer mode" permits the user to transmit and receive any type of data over the ds3 transport medium. 1.2.1 operation of the XRT72L13 while in the "clear channel ds3 framer mode" to be provided in the next update. 1.2.1.1 diagnostic features when the XRT72L13 is operating in the "clear chan- nel ds3 framer" mode, then the following diagnostic features are available. ? local loop-back mode ? remote loop-back mode ? prbs pattern generation/reception 1.2.1.1.1 local loop-back mode figure 30 presents an illustration of the XRT72L13 operating in the local-loop-back mode. f igure 29. f unctional b lock diagram of the XRT72L13 m13 m ultiplexer /f ramer ic, while o perating in the c lear c hannel ds3 f ramer m ode transmit payload data input interface block transmit ds3 framer block transmit liu interface block receive liu interface block receive ds3 framer block receive payload data output interface block microprocessor interface txser txnib[3:0] txinclk moto d[7:0] a[8:0] intb* csb* rdb_ds wrb_rw rdy_dtck reset* ale_as rxser rxnib[3:0] rxoutclk txpos txneg txlineclk rxpos rxneg rxlineclk tx lapd buffer/ controller rx lapd buffer/ controller transmit overhead input interface block receive overhead output interface block txohclk txohins txohind txoh txohenable txohframe txnibclk txframe rxnibclk rxframe rxohframe rxoh rxohclk rxohenable rxohind XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 60 figure 30 indicates that when the XRT72L13 has been configured to operate in the "clear channel ds3 framer local loop-back" mode, then the follow- ing internal connections are made. ? the txpos output signal is routed into the rxpos input pin. ? the txneg output signal is routed into the rxneg input pin ? the txlineclk output clock signal is routed into the rxlineclk input pin. 1.2.1.1.2 remote loop-back mode figure 31 presents an illustration of the XRT72L13 m13 multiplexer/framer ic operating in the "clear channel ds3 framer remote loop-back" mode. f igure 30. i llustration of the XRT72L13 m13 m ultiplexer /f ramer operating in the "c lear c hannel ds3 f ramer l ocal l oop - back " m ode transmit payload data input interface block transmit ds3 framer block transmit liu interface block receive liu interface block receive ds3 framer block receive payload data output interface block microprocessor interface txser txnib[3:0] txinclk moto d[7:0] a[8:0] intb* csb* rdb_ds wrb_rw rdy_dtck reset* ale_as rxser rxnib[3:0] rxoutclk txpos txneg txlineclk rxpos rxneg rxlineclk tx lapd buffer/ controller rx lapd buffer/ controller transmit overhead input interface block receive overhead output interface block txohclk txohins txohind txoh txohenable txohframe txnibclk txframe rxnibclk rxframe rxohframe rxoh rxohclk rxohenable rxohind local loop-back path ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 61 figure 31 indicates that when the XRT72L13 has been configured to operate in the "clear channel ds3 framer remote loop-back" mode, then the fol- lowing internal connections are made: ? the rxpos input signal is routed to the txpos output pin. ? the rxneg input signal is routed to the txneg output pin. ? the rxlineclk output clock signal is routed to the txlineclk input pin. 1.2.1.1.3 prbs generator/receiver in order to support diagnostic testing of the signal path, the XRT72L13 contains a prbs generator and receiver. this feature can be operated in conjunc- tion with (or not) with the "clear channel ds3 framer local" or "remote" loop-back modes. a more detailed description of this feature will be pre- sented in the next revision of the XRT72L13 data sheet. 1.3 XRT72L13 operation while in the "high speed hdlc controller" mode figure 32 presents a functional block diagram of the XRT72L13 m13 multiplexer/framer ic, when it has been configured to operate in the "high speed hdlc controller mode" f igure 31. i llustration of the XRT72L13 m13 m ultiplexer /f ramer operating in the "c lear c hannel ds3 f ramer r emote l oop - back " m ode transmit payload data input interface block transmit ds3 framer block transmit liu interface block receive liu interface block receive ds3 framer block receive payload data output interface block microprocessor interface txser txnib[3:0] txinclk moto d[7:0] a[8:0] intb* csb* rdb_ds wrb_rw rdy_dtck reset* ale_as rxser rxnib[3:0] rxoutclk txpos txneg txlineclk rxpos rxneg rxlineclk tx lapd buffer/ controller rx lapd buffer/ controller transmit overhead input interface block receive overhead output interface block txohclk txohins txohind txoh txohenable txohframe txnibclk txframe rxnibclk rxframe rxohframe rxoh rxohclk rxohenable rxohind remote loop-back path XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 62 a more detailed description of the "high speed hdlc controller" mode will be presented in the next update of this document. 2.0 the microprocessor interface block the microprocessor interface section supports com- munication between the "local" microprocessor (p) and the framer ic. in particular, the microprocessor interface section supports the following operations between the local microprocessor and the framer. ? the writing of configuration data into the framer on-chip (addressable) registers. ? the writing of an "outbound" pmdl path mainte- nance data link) message into the "transmit lapd message" buffer (within the framer ic). ? the framer ic's generation of an interrupt request to the p. ? the p's servicing of the interrupt request from the framer ic. ? the monitoring of the system's "health" by periodi- cally reading the on-chip performance monitor reg- isters. ? the reading of an "inbound" pmdl message from the "receive lapd" message buffer (within the framer ic). each of these operations (between the local micro- processor and the framer ic) will be discussed in some detail, throughout this data sheet. figure 33 presents a simple block diagram of the mi- croprosser interface block. f igure 32. i llustration of the XRT72L13 m13 m ultiplexer /f ramer ic, when it has been configured to operate in the "h igh s peed hdlc c ontroller " m ode tx hdlc controller block (ds3 payload) tx hdlc controller block (ds3 payload) rx hdlc controller block (ds3 payload) rx hdlc controller block (ds3 payload) clear channel ds3 framer clear channel ds3 framer microprocessor interface microprocessor interface txhdlc_dat[0:7] txhdlcclk send_fcs rxhdlc_dat[0:7] rxhdlcclk rxidle valid_fcs txpos txneg txlineclk rxpos rxneg rxlineclk ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 63 2.1 t he m icroprocessor i nterface b lock s ig - nal the framer ic may be configured into a wide variety of different operating modes and have its perfor- mance monitored by software through a standard (lo- cal "housekeeping") microprocessor, using data, ad- dress and control signals. the local p configures the framer ic (into a desired operating mode) by writing data into specific address- able, on-chip "read/write" registers; or on-chip ram. the microprocessor interface provides the signals which are required for a general purpose micropro- cessor to read or write data into these registers. the microprocessor interface also supports "polled" and interrupt driven environments. these interface sig- nals are described below in table 1, 2, and 3. the microprocessor interface can be configured to oper- ate in the "motorola" mode or in the "intel" mode. when the microprocessor interface is operating in the "motorola" mode, then some of the control signals function in a manner as required by the motorola 68000 family of microprocessors. likewise, when the microprocessor interface is operating in the "intel" mode, then some of these control signals function in a manner as required by the intel 80xx family of mi- croprocessors. table 1 lists and describes those microprocessor in- terface signals whose role is constant across the two modes. table 2 describes the role of some of these signals when the microprocessor interface is operat- ing in the intel mode. likewise, table 3 describes the role of these signals when the microprocessor inter- face is operating in the motorola mode. f igure 33. s imple b lock d iagram of the m icroprocessor i nterface b lock , within the f ramer ic a[8:0] wrb_rw rdb_ds cs ale_as reset int d[7:0] moto rdy_dtck microprocessor interface and programmable registers XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 64 t able 1: d escription of the m icroprocessor i nterface s ignals that exhibit constant roles in both the "i ntel " and "m otorola " m odes p in n ame t ype d escription moto i selection input for intel/motorola p interface. setting this pin to a logic "high" configures the microprocessor interface to operate in the "motor- ola" mode. likewise, setting this pin to a logic "low" configures the microprocessor interface to operate in the "intel" mode. d[7:0] i/o bi-directional data bus for register read or write operations a[8:0] i nine bit address bus input: this nine bit address bus is provided to allow the user to select an on-chip register or on-chip ram location. csb i chip select input. this "active low" signal selects the microprocessor interface of the uni device and enables read/write operations with the on-chip registers/on-chip ram. intb o interrupt request output: this "open-drain/active-low" output signal will inform the local p that the uni has an interrupt condition that needs servicing. t able 2: p in d escription of m icroprocessor i nterface s ignals - w hile the m icroprocessor i nterface is o perating in the i ntel m ode p in n ame e quivalent p in in i ntel environment t ype d escription ale_as ale i address-latch enable: this "active-high" signal is used to latch the contents on the address bus, a[8:0]. the contents of the address bus are latched into the a[8:0] inputs on the falling edge of ale_as. additionally, this signal can be used to indicate the start of a burst cycle. rdb_ds rd* i read signal: this "active-low" input functions as the read signal from the local p . when this signal goes "low", the uni microprocessor interface will place the contents of the addressed register on the data bus pins (d[15:0]). the data bus will be "tri-stated" once this input signal returns "high". wrb_rw wr* i write signal: this "active-low" input functions as the write signal from the local p . the contents of the data bus (d[15:0]) will be written into the addressed reg- ister (via a[8:0]), on the rising edge of this signal. rdy_dtck ready* o ready output: this "active-low" signal is provided by the uni device, and indi- cates that the current read or write cycle is to be extended until this signal is asserted. the local p will typically insert "wait" states until this signal is asserted. this output will toggle "low" when the device is ready for the next read or write cycle. ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 65 2.2 i nterfacing the xrt 72l13 ds3 f ramer to the l ocal c/p over via the m icroproces - sor i nterface b lock the microprocessor interface block, within the fram- er device is very flexible and provides the following options to the user. ? to interface the framer device to a c/p over an 8-bit wide bi-directional data bus. ? to interface the framer to an intel-type or motorola- type c/p. ? to transfer data (between the framer ic and the c/p) via the programmed i/o or burst mode each of the options are discussed in detail below. section 2.2.1 will discussed the issues associated with interfacing the framer to a c/p over an 8-bit bi-directional data bus. afterwards, section 2.2.2 will discuss data access (e.g., programmed i/o and burst) mode when interfaced to both motorola-type and intel-type c/p. 2.2.1 interfacing the xrt 72l13 ds3 framer to the microprocessor over an 8 bit wide bi-direc- tional data bus the xrt 72l13 ds3 framer microprocessor inter- face permits the user to interface it to a c/p over an 8 wide bi-directional data bus. 2.2.1.1 interfacing the framer to the c/p over an 8-bit wide bi-directional data bus. in general, interfacing the framer to an "8-bit" c/p is quite straight-forward. this is because most of the registers, within the framer, are 8-bits wide. further, in this mode, the c/p can read or write data into both even and odd numbered addresses within the framer address space. reading performance monitor (pmon) registers the only issue that the user should be wary of (while operating in the "8-bit" mode) occurs whenever the c/p needs to read the contents of one of the pmon (performance monitor) registers. the xrt 72l13 ds3 framer consists of the following pmon registers. ? pmon lcv event count register ? pmon framing error event count register ? pmon received febe event count register ? pmon parity error event count register ? pmon received single-bit hec error count reg- ister ? pmon received multiple-bit hec error count register ? pmon received idle cell count register ? pmon received valid cell count register ? pmon discarded cell count register ? pmon transmitted idle cell count register ? pmon transmitted valid cell count register. unlike most of the registers within the framer, the pmon registers are "16-bit" registers (or 16-bits wide). table 4 lists each of these pmon registers as consisting of two 8-bit registers. one of these "8-bit" register is labeled "msb" (or most significant byte") t able 3: p in d escription of the m icroprocessor i nterface s ignals while the m icroprocessor i nterface is operating in the m otorola m ode p in n ame e quivalent p in in m otorola environment t ype d escription ale_as as* i address strobe: this "active-low" signal is used to latch the contents on the address bus input pins: a[8:0] into the microprocessor interface circuitry. the contents of the address bus are latched into the uni device on the rising edge of the ale_as signal. this signal can also be used to indicate the start of a burst cycle. rdb_ds ds* i data strobe: this signal latches the contents of the bi-directional data bus pins into the addressed register (within the uni) during a write cycle. wrb_rw r/w* i read/write* input: when this pin is "high", it indicates a read cycle. when this pin is "low", it indicates a write cycle. rdy_dtck dtack* o data transfer acknowledge: the uni device asserts dtack* in order to inform the cpu that the present read or write cycle is nearly complete. the 68000 family of cpus requires this signal from its peripheral devices, in order to quickly and properly complete a read or write cycle. XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 66 and the other register is labeled "lsb" (or least sig- nificant byte). when an "8-bit" pmon register is concatenated with its "companion 8-bit" pmon reg- ister, one obtains the "full 16-bit expression" within that pmon register. the consequence of having these 16-bit registers is that an "8-bit" c/p will have to perform two consec- utive read operations in order to read in the full 16-bit expression contained within a given pmon register. to complicate matters, these pmon registers are "reset-upon-read" registers. more specifically, these pmon register are "reset-upon-read" in the sense that, the entire "16-bit" contents, within a given pmon register is reset, as soon as an "8-bit" c/p reads in either "byte" of this "two-byte" (e.g., 16 bit) expression. for example; consider that an "8-bit" c/p needs to read in the "pmon lcv event count" register. in order to ac- complish this task, the 8-bit c/p is going to have to read in the contents of "pmon lcv event count register - msb" (located at address = 0x40) and the contents of the "pmon lcv event count register - lsb (located at address = 0x41). these two "eight- bit" registers, when concatenated together, make up the "pmon lcv event count" register. if the 8-bit c/p reads in the "pmon lcv event count-lsb" register first; then the entire "pmon lcv event count" register will be reset to 0x0000. as a consequence, if the 8-bit c/p attempts to read in the "pmon lcv event count-msb" register in the very next read cycle, it will read in the value 0x00. the pmon holding register in order to "get-around" this "reset-upon-read" problem, the xrt 72l13 ds3 framer includes a spe- cial register, which permits "8-bit" c/p to read in the full 16-bit contents of these pmon registers. this special register is called the "pmon holding" regis- ter; and is located at 0x56 within the framer address space. the way the pmon holding register works is as fol- lows. whenever an "8-bit" c/p reads in one of the bytes (of the "2-byte" pmon register); the contents of the "unread" (e.g., other) byte will be stored in the pmon holding register. therefore, the "8-bit" c/p must then read in the contents of the pmon holding register in the very next read operation. in summary: whenever an "8-bit" c/p needs to read a pmon register, it must execute the follow- ing steps. step 1: read in the contents of a given "8-bit" pmon register (it does not matter whether the c/p reads in the "-msb" or the "-lsb" register). step 2: read in the contents of the "pmon holding" register (located at address = 0x56). this register will contain the contents of the "other" byte. 2.2.2 data access modes as mentioned earlier, the microprocessor interface block supports data transfer between the framer and the c/p (e.g., "read" and "write" operations) via two modes: the "programmed i/o" and the "burst" modes. each of these "data access" modes are dis- cussed in detail below. 2.2.2.1 data access using programmed i/o "programmed i/o" is the conventional manner in which a microprocessor exchanges data with a pe- ripheral device. however, it is also the slowest meth- od of data exchange between the framer and the c/ p; as will be described in this text. the next two sections present detailed information on programmed i/o access, when the xrt 72l13 ds3 framer is operating in the "intel mode" and in the "motorola mode". 2.2.2.1.1 programmed i/o access in the "intel" mode if the xrt 72l13 ds3 framer is interfaced to an "in- tel-type" c/p (e.g., the 80x86 family, etc.), then it should be configured to operate in the "intel" mode (by tying the "moto" pin to ground). intel-type "read" and "write" operations are described below. 2.2.2.1.1.1 the intel mode read cycle whenever an intel-type c/p wishes to read the contents of a register or some location within the re- ceive lapd message buffer or the receive oam cell buffer, (within the framer device), it should do the fol- lowing. 1. place the address of the "target" register or buffer location (within the framer) on the address bus input pins a[8:0]. 2. while the c/p is placing this address value on the address bus, the address decoding circuitry (within the user's system) should assert the cs* (chip select) pin of the framer, by toggling it "low". this action enables further communication between the c/p and the framer microproces- sor interface block. 3. toggle the ale_as (address latch enable) input pin "high". this step enables the "address bus" input drivers, within the microprocessor interface block of the framer. ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 67 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address" data setup time"), the c/p should toggle the ale_as pin "low". this step causes the framer device to "latch" the contents of the "address bus" into its internal circuitry. at this point, the address of the register or buffer locations (within the framer), has now been selected. 5. next, the c/p should indicates that this current bus cycle is a "read" operation by toggling the rdb_ds (read strobe) input pin "low". this action also enables the bi-directional data bus output drivers of the framer device. at this point, the "bi-directional" data bus output drivers will proceed to drive the contents of the "latched addressed" register (or buffer location) onto the bi-directional data bus, d[7:0]. 6. immediately after the c/p toggles the "read strobe" signal "low", the framer device will toggle the rdy_dtck output pin "low". the framer device does this in order to inform the c/p that the data (to be read from the data bus) is "not ready" to be "latched" into the c/p. 7. after some settling time, the data on the "bi-direc- tional" data bus will stabilize and can be read by the c/p. the xrt 72l13 ds3 framer will indi- cate that this data can be read by toggling the rdy_dtck (ready) signal "high". 8. after the c/p detects the rdy_dtck signal (from the xrt 72l13 ds3 framer), it can then terminate the read cycle by toggling the rdb_ds (read strobe) input pin "high". figure 34 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during an "intel-type" programmed i/o read opera- tion. 2.2.2.1.1.2 the intel mode write cycle whenever an intel-type c/p wishes to write a byte or word of data into a register or buffer location, within the framer, it should do the following. 1. assert the ale_as (address latch enable) input pin by toggling it "high". when the c/p asserts the ale_as input pin, it enables the "address bus input drivers" within the framer chip. 2. place the address of the "target" register or buffer location (within the framer), on the address bus input pins, a[8:0]. 3. while the c/p is placing this address value onto the address bus, the address decoding cir- cuitry (within the user's system) should assert the cs* input pin of the framer device by toggling it "low". this step enables further communication between the c/p and the framer microproces- sor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time); the c/p should toggle the ale_as input pin "low". this step causes the framer device to "latch" the contents of the "address bus" into its internal circuitry. at this point, the address of the register or buffer loca- tion (within the framer), has now been selected. 5. next, the c/p should indicate that this current bus cycle is a "write" operation; by toggling the wrb_rw (write strobe) input pin "low". this action also enables the "bi-directional" data bus input drivers of the framer device. f igure 34. b ehavior of m icroprocessor i nterface signals during an "i ntel - type " p rogrammed i/o r ead o peration ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid address of target register wrb_rw XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 68 6. the c/p should then place the byte or word that it intends to write into the "target" register, on the bi-directional data bus, d[7:0]. 7. after waiting the appropriate amount of time, for the data (on the bi-directional data bus) to settle; the c/p should toggle the wrb_rw (write strobe) input pin "high". this action accom- plishes two things: a. it latches the contents of the bi-directional data bus into the xrt 72l13 ds3 framer micropro- cessor interface block. b. it terminates the write cycle. figure 35 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during an "intel-type" programmed i/o write opera- tion. 2.2.2.1.2 programmed i/o access in the motor- ola mode if the xrt 72l13 ds3 framer is interfaced to a "mo- torola-type" c/p (e.g., the mc680x0 family, etc.); it should be configured to operate in the "motorola" mode (by tying the "moto" pin to vcc). motorola- type programmed i/o "read" and "write" operations are described below. 2.2.2.1.2.1 the motorola mode read cycle whenever a "motorola-type" c/p wishes to read the contents of a register or some location within the receive lapd message or receive oam cell buffer, (within the framer device) it should do the following. 1. assert the ale_as (address-strobe) input pin by toggling it low. this step enables the address bus input drivers, within the microprocessor inter- face block of the framer ic. 2. place the address of the "target" register (or buffer location) within the framer, on the address bus input pins, a[8:0]. 3. at the same time, the address decoding circuitry (within the user's system) should assert the cs* (chip select) input pin of the framer device, by toggling it "low". this action enables further com- munication between the c/p and the framer microprocessor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to latch the contents of the "address bus" into its internal circuitry. at this point, the address of the register or buffer loca- tion (within the framer) has now been selected. 5. further, the c/p should indicate that this cycle is a "read" cycle by setting the wrb_rw (r/w*) input pin "high". 6. next the c/p should initiate the current bus cycle by toggling the rdb_ds (data strobe) input pin "low". this step enables the bi-directional data bus output drivers, within the xrt 72l13 ds3 framer. at this point, the bi-directional data bus output drivers will proceed to driver the con- tents of the "address" register onto the bi-direc- tional data bus, d[7:0]. 7. after some settling time, the data on the "bi-direc- tional" data bus will stabilize and can be read by the c/p. the xrt 72l13 ds3 framer will indi- cate that this data can be read by asserting the rdy_dtck (dtack) signal. 8. after the c/p detects the rdy_dtck signal (from the xrt 72l13 ds3 framer) it will termi- f igure 35. b ehavior of the m icroprocessor i nterface s ignals , during an "i ntel - type " p rogrammed i/ o w rite o peration ale_as a[8:0] cs* d[15:0] wrb_rw data to be written address of target register rdb_ds ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 69 nate the read cycle by toggling the "rdb_ds" (data strobe) input pin "high". figure 36 presents a timing diagram which illustrates the behavior of the microprocessor interface signals during a "motorola-type" programmed i/o read op- eration. 2.2.2.1.2.2 the motorola mode write cycle whenever a motorola-type c/p wishes to write a byte or word of data into a register or buffer location, within the framer, it should do the following. 1. assert the ale_as (address select) input pin by toggling it "low". this step enables the "address bus" input drivers (within the framer chip). 2. place the address of the "target" register or buffer location (within the framer), on the address bus input pins, a[8:0]. 3. while the c/p is placing this address value onto the address bus, the address-decoding cir- cuitry (within the user's system) should assert the cs* (chip select) input pins of the framer by tog- gling it "low". this step enables further communi- cation between the c/p and the framer micro- processor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to "latch" the contents of the "address bus" into its own circuitry. at this point, the address of the register or buffer location (within the framer), has now been selected. 5. further, the c/p should indicate that this cur- rent bus cycle is a "write" operation by toggling the wrb_rw (r/w*) input pin "low". 6. the c/p should then place the byte or word that it intends to write into the "target" register, on the bi-directional data bus, d[7:0]. 7. next, the c/p should initiate the bus cycle by toggling the rdb_ds (data strobe) input pin "low". when the xrt 72l13 ds3 framer senses that the wrb_rw (r/w*) input pin is "high" and that the rdb_ds (data strobe) input pin has tog- gled "low", it will enable the "input drivers" of the bi-directional data bus, d[7:0]. 8. after waiting the appropriate time, for this newly placed data to settle on the bi-directional data bus (e.g., the "data setup" time) the framer will assert the rdy_dtck output signal. 9. after the c/p detects the rdy_dtck signal (from the framer), the c/p should toggle the rdb_ds input pin "high". this action accom- plishes two things. a. it latches the contents of the bi-directional data bus into the XRT72L13 microprocessor interface block. b. it terminates the "write" cycle. figure 37 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during a "motorola-type" programmed i/o write op- eration. f igure 36. i llustration of the b ehavior of m icroprocessor i nterface signals , during a "m otorola - type " p rogrammed i/o r ead o peration ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data address of target register wrb_rw XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 70 2.2.2.2 data access using burst mode i/o burst mode i/o access is a much faster way to trans- fer data between the c/p and the microprocessor interface (of the xrt 72l13 ds3 framer), than pro- grammed i/o. the reason why burst mode i/o is so much faster follows. data is placed upon the address bus input pins a[8:0]; only for the very first access, within a given burst access. the remaining read or write operations (within this burst access) do not require the place- ment of the address data on the address data bus. as a consequence, the user does not have to wait through the "address setup" and "hold" times; for each of these read/write operation, within the "burst" access. it is important to note that there are some limitations associated with burst mode i/o operations. 1. all cycles within the burst access, must be either "all read" or "all write" cycles. no "mixing of "read" and "write" cycles is permitted. 2. a burst access can only be used when "read" or "write" operations are to be employed over a contiguous range of address locations, within the framer device. 3. the very first "read" or "write" cycle, within a burst access, must start at the "lowest" address value, of the range of addresses to be accessed. subsequent operations will automatically be incremented to the very next higher address value. examples of burst mode i/o operations are present- ed below for read and write operations, with both "in- tel-type" and "motorola-type" c/p. 2.2.2.2.1 burst i/o access in the intel mode if the xrt 72l13 ds3 framer is interfaced to an "in- tel-type" c/p (e.g., the 80x86 family, etc.), then it should be configured to operate in the "intel" mode (by tying the "moto" pin to ground). intel-type "read" and "write" burst i/o access operations are described below. 2.2.2.2.1.1 the "intel-mode" read burst access whenever an "intel-type" c/p wishes to read the contents of numerous registers or buffer locations over a "contiguous" range of addresses; then it should do the following. a. perform the initial "read" operation of the burst access. b. perform the remaining "read" operations of the burst access. c. terminate the "burst access" operation. each of these "operations" within the burst access are described below. 2.2.2.2.1.1.1 the initial read operation the initial read operation of an "intel-type" read burst access is accomplished by executing a "programmed i/o" read cycle as summarized below. a.0 execute a single ordinary (programmed i/ o) read cycle, as described in steps a.1 through a.7 below. a.1 place the address of the "initial-target" register or buffer location (within the framer) on the address bus input pins a[8:0]. a.2 while the c/p is placing this address value onto the address bus, the address decoding f igure 37. i llustration of the b ehavior of the m icroprocessor i nterface signal , during a "m otor - ola - type " p rogrammed i/o w rite o peration ale_as a[8:0] cs* d[15:0] rdb_ds rdy_dtck data to be written address of target register wrb_rw ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 71 circuitry (within the user's system) should assert the cs* input pin of the framer, by tog- gling it "low". this step enables further commu- nication between the c/p and the framer microprocessor interface block. a.3 assert the ale_as (address latch enable) pin by toggling it "high". this step enables the "address bus" input drivers, within the micro- processor interface block of the framer. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate "address" data setup time"), the c/p should then tog- gle the ale_as pin "low". this step latches the contents, on the address bus pins, a[8:0], into the xrt 72l13 ds3 framer microproces- sor interface block. at this point, the "initial" address of the burst access has now been selected. n ote : the ale_as input pin should remain "low" for the remainder of this "burst access" operation. a.5 next, the c/p should indicate that this cur- rent bus cycle is a "read" operation by tog- gling the rdb_ds (read strobe) input pin "low". this action also enables the "bi-direc- tional" data bus output drivers of the framer device. at this point, the bi-directional data bus output drivers will proceed to drive the contents of the "addressed" register onto the "bi-direc- tional" data bus, d[7:0]. a.6 immediately after the c/p toggles the "read strobe" signal "low", the framer device will tog- gle the rdy_dtck (ready) output pin "low". the framer device does this in order to inform the c/p that the data (to be read from the data bus) is "not ready" to be latched into the c/p. a.7 after some settling time, the data on the "bi- directional" data bus will stabilize and can be read by the c/p. the xrt 72l13 ds3 framer will indicate that this data is ready to be read, by toggling the rdy_dtck (ready) signal "high". a.8 after the c/p detects the rdy_dtck signal (from the xrt 72l13 ds3 framer ic), it can then will terminate the "read" cycle by toggling the rdb_ds (read strobe) input pin "high". figure 38 presents an illustration of the behavior of the microprocessor interface signals, during the "ini- tial" read operation, within a burst i/o cycle; for an intel-type c/p. XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 72 at the completion of this initial read cycle, the c/p has read in the contents of the first register or buffer location (within the xrt 72l13 ds3 framer) for this particular burst i/o access operation. in order to illus- trate how this "burst access operation" works, the byte (or word) of data, that is being read in figure 38, has been labeled "valid data at offset = 0x00". this label indicates that the c/p is reading the very first register (or buffer location) in this burst access opera- tion. 2.2.2.2.1.1.2 the subsequent read operations the procedure that the c/p must use to perform the remaining read cycles, within this burst access operation, is presented below. b.0 execute each subsequent read cycles, as described in steps 1 through 3 below. b.1 without toggling the ale_as input pin (e.g., keeping it "low"); toggle the rdb_ds input pin "low". this step accomplishes the following. a. the framer will internally increments the "latched address" value (within the microprocessor inter- face circuitry). b. the output drivers of the "bi-directional" data bus, d[7:0] are enabled. at some time later, the regis- ter or buffer location corresponding to the "incre- mented" latched address value will be driven onto the bi-directional data bus. b.2 immediately after the "read strobe" pin toggles "low" the framer ic will toggle the rdy_dtck (ready) output pin "low" to indicate its "not ready" status. b.3 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the xrt 72l13 ds3 framer will indicate that this data is ready to be read by toggling the rdy_dtck (ready) signal "high". b.4 after the c/p detects the rdy_dtck signal (from the xrt 72l13 ds3 framer), it can then f igure 38. b ehavior of the m icroprocessor i nterface s ignals , during the "i nitial " r ead o peration of a b urst c ycle (i ntel t ype p rocessor ) ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data of offset = 0x00 address of initial target register (offset = 0x00) wrb_rw ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 73 terminates the "read" cycle by toggling the rdb_ds (read strobe) input pin "high". for subsequent read operations, within this burst cy- cle, the c/p simply repeats steps 1 through 3, as il- lustrated in figure 39. in addition to the behavior of the microprocessor in- terface signals, figure 39 also illustrates other points regarding the "burst access operation". a. the framer internally increments the address value, from the original "latched" value shown in figure 38. this is illustrated by the data, appear- ing on the data bus, (for the first read access) being labeled "valid data at offset = 0x01"; and that for the second read access being labeled "valid data at offset = 0x02.". b. the framer performs this "address incrementing" process even though there are no changes in the address bus data, a[8:0]. 2.2.2.2.1.1.3 terminating the burst access operation the burst access operation will be terminated upon the rising edge of the ale_as input signal. at this point the framer will cease to internally increment the "latched" address value. further, the c/p is now free to execute either a "programmed i/o" access or to start another "burst access" operation with the xrt 72l13 ds3 framer. 2.2.2.2.1.2 the "intel-mode" write burst access whenever an "intel-type" c/p wishes to write data into a "contiguous" range of addresses, then it should do the following. a. perform the initial "write" operation; of the burst access. b. perform the remaining "write" operations, of the burst access. c. terminate the burst access operation. each of these "operations" within the burst access are described below. 2.2.2.2.1.2.1 the initial write operation the initial write operation of an "intel-type" write burst access is accomplished by executing a "pro- grammed i/o" write cycle as summarized below. a.0 execute a single ordinary (programmed i/ o) write cycle, as described in steps a.1 through a.7 below. a.1 place the address of the "initial" target register (or buffer location) within the framer, on the address bus pins, a[8:0]. a.2 a.2 at the same time, the "address-decoding" circuitry (within the user's system) should assert the cs* (chip select) input pin of the framer, by toggling it "low". this step enables further communication between the c/p and the framer microprocessor interface block. a.3 assert the ale_as (address latch enable) input pin "high". this step enables the address bus input drivers, within the microprocessor interface block of the framer. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time); the c/p should then toggle the ale_as input pin "low". this step latches the f igure 39. b ehavior of the m icroprocessor i nterface s ignals , during subsequent "r ead " o pera - tions within the b urst i/o c ycle ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data at offset =0x01 wrb_rw not valid valid data at offset =0x02 address of initial target register (offset = 0x00) XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 74 contents, on the address bus pins, a[8:0], into the xrt 72l13 ds3 framer microprocessor interface block. at this point, the "initial" address of the "burst access" has now been selected. n ote : the ale_as input pin should remain "low" for the remainder of this "burst i/o access" operation. a.5 next, the c/p should indicate that this cur- rent bus cycle is a "write" operation by keeping the rdb_ds pin "high" and toggling the wrb_rw (write strobe) pin "low". this action also enables the "bi-directional" data bus input drivers of the framer device. a.6 the c/p places the byte (or word) that it intends to write into the "target" register on the "bi-directional data" bus, d[7:0]. a.7 after waiting the appropriate amount of time, for the data (on the bi-directional data bus) to set- tle, the c/p should toggle the wrb_rw (write strobe) input pin "high". this action accomplishes two things. a. it latches the contents of the bi-directional data bus into the xrt 72l13 ds3 framer micropro- cessor interface block. b. it terminates the write cycle. figure 40 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during the "initial" write operation within a burst ac- cess, for an "intel-type" c/p. at the completion of this initial write cycle, the c/p has written a byte or word into the first register or buffer location (within the xrt 72l13 ds3 framer) for this particular burst access operation. in order to il- lustrate this point, the byte (or word) of data, that is being written in figure 40 has been labeled "data to be written (offset = 0x00)". 2.2.2.2.1.2.2 the subsequent write operations the procedure that the c/p must use to perform the remaining write cycles, within this burst access operation, is presented below. b.0 execute each subsequent write cycle, as described in steps b.1 through b.3. b.1 without toggling the ale_as input pin (e.g., keeping it "low"); apply the value of the next f igure 40. b ehavior of the m icroprocessor i nterface signals , during the "i nitial " w rite o peration of a b urst c ycle (i ntel - type p rocessor ) ale_as a[8:0] cs* d[7:0] wrb_rw data to be written (offset = 0x00) address of initial target register (offset = 0x00) rdb_ds ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 75 byte or word (to be written into the framer) to the bi-directional data bus pins, d[7:0]. b.2 toggle the wrb_rw (write strobe) input pin "low". this step accomplishes two things. a. it enables the input drivers of the bi-directional data bus. b. it causes the framer to internally increment the value of the "latched" address. b.3 after waiting the appropriate amount of settling time the data, in the internal data bus, will stabi- lize and is ready to be latched into the framer microprocessor interface block. at this point, the c/p should latch the data into the framer by toggling the wrb_rw input pin "high". for subsequent write operations, within this burst i/o access, the c/p simply repeats steps b.1 through b.3, as illustrated in figure 41. 2.2.2.2.1.2.3 terminating the burst i/o access burst access operation will be terminated upon the rising edge of the ale_as input signal. at this point the framer will cease to internally increment the "latched" address value. further, the c/p is now free to execute either a "programmed i/o" access or to start another "burst access operation" with the xrt 72l13 ds3 framer. 2.2.2.2.2 burst i/o access in the motorola mode if the xrt 72l13 ds3 framer is interfaced to a "mo- torola-type" c/p (e.g., the mc680x0 family, etc.), then it should be configured to operate in the "motor- ola" mode (by tying the "moto" pin to vcc). motoro- la-type "read" and "write" burst i/o access opera- tions are described below. 2.2.2.2.2.1 the "motorola-mode" read burst i/ o access operation whenever a "motorola-type" c/p wishes to read the contents of numerous registers or buffer locations over a "contiguous" range of addresses, then it should do the following. a. perform the initial "read" operation of the burst access. b. perform the remaining "read" operations; in the burst access. c. terminate the "burst access" operation. each of these operations, within the burst access are discussed below. 2.2.2.2.2.1.1 the initial read operation the initial read operation of a "motorola-type" read burst access is accomplished by executing a "pro- grammed i/o read" cycle, as summarized below. a.0 execute a single ordinary (programmed i/ o) read cycle, as described in steps a.1 through a.8 below. a.1 assert the ale_as (as*) input pin by toggling it "low". this step enables the "address bus" input drivers (within the xrt 72l13 ds3 framer) within the framer microprocessor interface block. a.2 place the address of the "initial" target register or buffer location (within the framer), on the address bus input pins, a[8:0]. a.3 at the same time, the address-decoding cir- cuitry (within the user's system) should assert the cs* (chip select) input pins of the framer f igure 41. b ehavior of the m icroprocessor i nterface s ignals , during subsequent "w rite " o pera - tions within the b urst i/o c ycle ale_as wrb_rw a[8:0] cs* d[15:0] rdy_dtck data written at offset =0x01 rdb_ds data written at offset =0x02 address of initial target register (offset = 0x00) XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 76 by toggling it "low". this action enables further communication between the c/p and the framer microprocessor interface block. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to latch the contents of the address bus into its internal circuitry. at this point, the "initial" address of the burst access has now been selected. a.5 further, the c/p should indicate that this cycle is a "read" cycle by setting the wrb_rw (r/w*) input pin "high". a.6 next the c/p should initiate the current bus cycle by toggling the rdb_ds (data strobe) input pin "low". this step will enable the bi- directional data bus output drivers, within the xrt 72l13 ds3 framer. at this point, the bi- directional data bus output drivers will proceed to driver the contents of the "address" register onto the bi-directional data bus. a.7 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the xrt 72l13 ds3 framer will indicate that this data can be read by asserting the rdy_dtck (dtack) signal. a.8 after the c/p detects the rdy_dtck signal (from the xrt 72l13 ds3 framer) it will termi- nate the read cycle by toggling the "rdb_ds" (data strobe) input pin "high". figure 42 presents an illustration of the behavior of the microprocessor interface signals during the "ini- tial" read operation, within a burst i/o cycle; for a motorola-type c/p. at the completion of this initial read cycle, the c/p has read in the contents of the first register or buffer location (within the xrt 72l13 ds3 framer) for this particular burst access operation. in order to illus- trate how this "burst i/o cycle" works, the byte (or word) of data, that is being read in figure 42 has been labeled "valid data at offset = 0x00". this indi- cates that the c/p is reading the very first register (or buffer location) in this burst access. 2.2.2.2.2.1.2 the subsequent read operations the procedure that the c/p must use to perform the remaining read cycles, within this burst access operation, is presented below. b.0 execute each subsequent read cycle, as described in steps b.1 through b.3, below. b.1 without toggling the ale_as input pin (e.g., keeping it "high"); toggle the rdb_ds (data strobe) input pin "low". this step accomplishes the following. a. the framer internally increments the "latched address" value (within the microprocessor inter- face circuitry). b. the output drivers of the "bi-directional" data bus (d[7:0]) are enabled. at some time later, the reg- ister or buffer location corresponding to the "incremented" latched address value will be driven onto the bi-directional data bus. n ote : in order to insure that the xrt 72l13 ds3 framer will interpret this signal as being a "read" signal, the c/ p should keep the wrb_rw input pin "high". f igure 42. b ehavior of the m icroprocessor i nterface s ignals , during the "i nitial " r ead o peration of a b urst c ycle (m otorola t ype p rocessor ) ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data at offset = 0x00 address of initial target register (offset = 0x00) wrb_rw ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 77 b.2 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the xrt 72l13 ds3 framer will indicate that this data is ready to be read by asserting the rdy_dtck (dtack*) sig- nal. b.3 after the c/p detects the rdy_dtck signal (from the xrt 72l13 ds3 framer), it termi- nates the "read" cycle by toggling the rdb_ds (data strobe) input pin "high". for subsequent read operations, within this burst cy- cle, the c/p simply repeats steps b.1 through b.3, as illustrated in figure 43. 2.2.2.2.2.1.3 terminating the burst access operation the burst i/o access will be terminated upon the fall- ing edge of the ale_as input signal. at this point the framer will cease to internally increment the "latched" address value. further, the c/p is now free to exe- cute either a "programmed i/o" access or to start an- other "burst access" operation with the xrt 72l13 ds3 framer. 2.2.2.2.2.2 the "motorola-mode" write burst access whenever a "motorola-type" c/p wishes to write the contents of numerous registers or buffer locations over a "contiguous" range of addresses, then it should do the following. a. perform the initial "write" operation; of the burst access. b. perform the remaining "write" operations, of the burst access. c. terminate the burst access operation. each of these "operations" within the burst access are described below. 2.2.2.2.2.2.1 the initial write operation the initial write operation of a "motorola-type" write burst access is accomplished by executing a "pro- grammed i/o write cycle" as summarized below. a.0 execute a single ordinary (programmed i/ o) write cycle, as described in steps a.1 through a.7 below. a.1 assert the ale_as (address strobe) input pin by toggling it "low". this step enables the address bus input drivers (within the xrt 72l13 ds3 framer). a.2 place the address of the "initial" target register or buffer location (within the framer), on the address bus input pins, a[8:0]. a.3 at the same time, the address-decoding cir- cuitry (within the user's system) should assert the cs* input pin of the framer by toggling it "low". this step enables further communication between the c/p and the framer micropro- cessor interface block. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to "latch" the contents of the "address bus" into its own circuitry. at this point, the "initial" address of the burst access has now been selected. a.5 further, the c/p should indicate that this cur- rent bus cycle is a "write" operation by toggling the wrb_rw (r/w*) input pin "low". f igure 43. b ehavior the m icroprocessor i nterface s ignals , during subsequent "r ead " o perations within the b urst i/o c ycle (m otorola - type c/p) ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data at offset =0x01 wrb_rw not valid valid data at offset =0x02 address of initial target register (offset = 0x00) XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 78 a.6 the c/p should then place the byte or word that it intends to write into the "target" register, on the bi-directional data bus, d[7:0]. a.7 next, the c/p should initiate the bus cycle by toggling the rdb_ds (data strobe) input pin "low". when the xrt 72l13 ds3 framer senses that the wrb_rw input pin is "low", and that the rdb_ds input pin has toggled "low" it will enable the "input drivers" of the bi- directional data bus, d[7:0]. a.8 after waiting the appropriate amount of time, for this newly placed data to settle on the bi-direc- tional data bus( e.g., the "data setup" time) the framer will assert the rdy_dtck (dtack) out- put signal. a.9 after the p/c detects the rdy_dtck signal (from the framer) it should toggle the rdb_ds input pin "high". this action accomplishes two things: a. it latches the contents of the bi-directional data bus into the xrt 72l13 ds3 framer micropro- cessor interface block. b. it terminates the "write" cycle. figure 44 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during the "initial" write operation within a burst ac- cess, for a "motorola-type" c/p. at the completion of this initial write cycle, the c/p has written a byte or word into the first register or buffer location (within the xrt 72l13 ds3 framer) for this particular burst i/o access. in order to illustrate how this "burst i/o cycle" works, the byte (or word) of data, that is being written in figure 44 has been la- beled "data to be written (offset = 0x00)." 2.2.2.2.2.2.2 the subsequent write operations the procedure that the c/p must use to perform the remaining write cycles, within this burst access operation, is presented below. b.0 execute each subsequent write cycle, as described in steps b.1 through b.3 b.1 without toggling the ale_as (address strobe) input pin (e.g., keeping it "high"); apply the value of the next byte or word (to be written into the framer) to the bi-directional data bus pins, d[7:0]. b.2 toggle the rdb_ds (data strobe) input pin "low". this step accomplishes the following. a. the framer internally increments the "latched address" value (within the microprocessor inter- face). b. the input drivers of the bi-directional data bus are enabled. n ote : in order to insure that the xrt 72l13 ds3 framer will interpret this signal as being a "write" signal, the c/ p should keep the wrb_rw input pin "low". b.3 after some settling time, the data, in the inter- nal data bus, will stabilize and is ready to be latched into the framer microprocessor inter- face block. the microprocessor interface block will indicate that this data is ready to be latched by asserting the rdy_dtck (dtack) output sig- nal. at this point, the c/p should latch the data into the framer by toggling the rdb_ds input pin "high". f igure 44. b ehavior of the m icroprocessor i nterface signals , during the "i nitial " w rite o peration of a b urst c ycle (m otorola - type p rocessor ) ale_as a[8:0] cs* d[15:0] rdb_ds rdy_dtck data to be written (offset = 0x00) address of initial target register (offset = 0x00) ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 79 for subsequent write operations, within this burst i/o access, the c/p simply repeats steps b.1 through b.3 as illustrated in figure 45. 2.2.2.2.2.2.3 terminating the burst i/o access the burst i/o access will be terminated upon the fall- ing edge of the ale_as input signal. at this point the framer will cease to internally increment the "latched" address value. further, the c/p is now free to exe- cute either a "programmed i/o" access or to start an- other "burst i/o access" with the XRT72L13 ds3 framer. 2.3 o n -c hip r egister o rganization the microprocessor interface section, within the framer device allows the user to do the following. ? configure the framer into a wide variety of operat- ing modes. ? employ various features of the framer device. ? perform status monitoring ? enable/disable and service interrupt conditions all of these things are accomplished by reading from and writing to the many on-chip registers within the framer device. table 4 lists each of these registers and their corresponding address locations within the framer address space. 2.3.1 framer register addressing the array of on-chip registers consists of a variety of register types. these registers are denoted in table 4, as follows. r/o - read only registers. r/w - read/write registers rur - reset-upon-read registers additionally, some of these registers consists of both "r/o" and "r/w" bit-fields. these registers are de- noted in table 4 as "combination of r/w and r/o". the bit-format and definitions for each of these regis- ters are presented in section 2.3.2 2.3.2 m13 mux/framer register description this section provides a function description of each bit-field within each of the on-chip framer register. n ote : for all on-chip registers, a table containing the bit- format of the register is presented. additionally, these tables also contain the default values for each of these reg- ister bits. finally, the function description, associated with each register bit-field is presented, along with a reference to a section number, within this data sheet, that provides a more in-depth discussion of the functions associated with this register bit-field. f igure 45. b ehavior of the m icroprocessor i nterface s ignals , during subsequent "w rite " o pera - tions with the b urst i/o c ycle (m otorola - type c/p) ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck data written at offset =0x01 wrb_rw data written at offset =0x02 address of initial target register (offset = 0x00) XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 80 2.3.2.1 operating mode register t able 4: r egister a ddress m ap a ddress r egister n ame t ype d efault v alue 0x00 operating mode register r/w 0x2b 0x01 i/o control register r/w & r/o 0xa0 0x02 part number register r/o 0x22 0x03 version number register r/o 0x01 0x04 block interrupt enable register r/w 0x00 0x05 block interrupt status register rur 0x00 0x06 rxfifo control register r/o and r/w 0x00 0x07 m23 configuration register r/w 0x00 0x08 m23 tx ds2 ais register r/w 0x00 0x09 m23 request loop-back register r/w 0x00 0x0a m23 loop-back activation register r/w 0x00 0x0b m23 rx ds2 ais register r/w 0x00 0x0c ds3 test register r/o and r/w 0x00 0x0d - 0x0f reserved 0x10 rxds3 configuration & status register r/o and r/w 0x14 0x11 rxds3 status register r/o 0x00 0x12 rxds3 interrupt enable register r/w 0x00 0x13 rxds3 interrupt status register rur 0x00 0x14 rxds3 sync detect register r/w 0x00 0x15 reserved 0x16 rxds3 feac register r/o 0xff 0x17 rxds3 feac interrupt enable and status register r/w & r/o & rur 0x00 0x18 rxlapd control register r/w & rur 0x00 0x19 rxlapd status register r/o 0x00 0x1a m12 configuration register - 1 r/w 0x08 0x1b m12 configuration register - 2 r/w 0x08 0x1c m12 configuration register - 3 r/w 0x08 0x1d m12 configuration register - 4 r/w 0x08 0x1e m12 configuration register - 5 r/w 0x08 0x1f m12 configuration register - 6 r/w 0x08 0x20 m12 configuration register - 7 r/w 0x08 0x21 m12 ais register - 1 r/w 0x00 0x22 m12 ais register - 2 r/w 0x00 0x23 m12 ais register - 3 r/w 0x00 0x24 m12 ais register - 4 r/w 0x00 0x25 m12 ais register - 5 r/w 0x00 0x26 m12 ais register - 6 r/w 0x00 0x27 m12 ais register - 7 r/w 0x00 0x28 m12 loop-back register - 1 r/w 0x00 0x29 m12 loop-back register - 2 r/w 0x00 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 81 0x2a m12 loop-back register - 3 r/w 0x00 0x2b m12 loop-back register - 4 r/w 0x00 0x2c m12 loop-back register - 5 r/w 0x00 0x2d m12 loop-back register - 6 r/w 0x00 0x2e m12 loop-back register - 7 r/w 0x00 0x2f reserved 0x30 txds3 configuration register r/w 0x07 0x31 txds3 feac configuration & status register r/w & r/o & rur 0x00 0x32 txds3 feac register r/w 0xff 0x33 tx lapd configuration register r/w & r/o 0x08 0x34 txds3 lapd status and interrupt register r/w & r/o & rur 0x00 0x35 txds3 m-bit mask register r/w 0x00 0x36 txds3 f-bit mask register - 1 r/w 0x00 0x37 txds3 f-bit mask register - 2 r/w 0x00 0x38 txds3 f-bit mask register - 3 r/w 0x00 0x39 txds3 f-bit mask register - 4 r/w 0x00 0x3a ds2 framer configuration register -1 r/w 0x00 0x3b ds2 framer configuration register - 2 r/w 0x00 0x3c ds2 framer configuration register - 3 r/w 0x00 0x3d ds2 framer configuration register - 4 r/w 0x00 0x3e ds2 framer configuration register - 5 r/w 0x00 0x3f ds2 framer configuration register - 6 r/w 0x00 0x40 ds2 framer configuration register - 7 r/w 0x00 0x41 - 0x4f reserved 0x50 pmon lcv count register - msb rur 0x00 0x51 pmon lcv count register - lsb rur 0x00 0x52 pmon framing bit error count register - msb rur 0x00 0x53 pmon framing bit error count register - lsb rur 0x00 0x54 pmon p-bit error count register - msb rur 0x00 0x55 pmon p-bit error count register - lsb rur 0x00 0x56 pmon febe event count register - msb rur 0x00 0x57 pmon febe event count register - lsb rur 0x00 0x58 pmon cp-bit error count register - msb rur 0x00 0x59 pmon cp-bit error count register - lsb rur 0x00 0x5a pmon ds2 framing bit error count register - 1 rur 0x00 0x5b pmon ds2 framing bit error count register - 2 rur 0x00 0x5c pmon ds2 framing bit error count register - 3 rur 0x00 0x5d pmon ds2 framing bit error count register - 4 rur 0x00 0x5e pmon ds2 framing bit error count register - 5 rur 0x00 0x5f pmon ds2 framing bit error count register - 6 rur 0x00 0x60 pmon ds2 framing bit error count register - 7 rur 0x00 t able 4: r egister a ddress m ap a ddress r egister n ame t ype d efault v alue XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 82 0x61 pmon g.747 parity bit error count register - 1 rur 0x00 0x62 pmon g.747 parity bit error count register - 2 rur 0x00 0x63 pmon g.747 parity bit error count register - 3 rur 0x00 0x64 pmon g.747 parity bit error count register - 4 rur 0x00 0x65 pmon g.747 parity bit error count register - 5 rur 0x00 0x66 pmon g.747 parity bit error count register - 6 rur 0x00 0x67 pmon g.747 parity bit error count register - 7 rur 0x00 0x68 - 0x6b reserved 0x6c pmon holding register r/o 0x00 0x6d one second error status register r/o 0x00 0x6e one second - lcv accumulation register - msb r/o 0x00 0x6f one second - lcv accumulation register - lsb r/o 0x00 0x70 one second - p-bit error accumulation register - msb r/o 0x00 0x71 one second - p- bit error accumulation register - lsb r/o 0x00 0x72 one second - cp-bit error accumulation register - msb r/o 0x00 0x73 one second - cp-bit error accumulation register - lsb r/o 0x00 0x74 - 0x7f reserved 0x80 line interface drive register r/w 0x00 0x81 line interface scan register r/o 0x00 0x82 - 0x8f reserved 0x90 m23 rxds2 loop-back request interrupt enable register r/w 0x00 0x91 m23 rxds2 loop-back request interrupt register rur 0x00 0x92 m23 rxds2 loop-back request status register r/o 0x00 0x93 m12 loop-back interrupt status/enable register - 1 r/w & rur 0x00 0x94 m12 loop-back status register - 1 r/o 0x00 0x95 m12 loop-back interrupt status/enable register - 2 r/w & rur 0x00 0x96 m12 loop-back status register - 2 r/o 0x00 0x97 m12 loop-back interrupt status/enable register - 3 r/w & rur 0x00 0x98 m12 loop-back status register - 3 r/o 0x00 0x99 m12 loop-back interrupt status/enable register - 4 r/w & rur 0x00 0x9a m12 loop-back status register - 4 r/o 0x00 0x9b m12 loop-back interrupt status/enable register - 5 r/w & rur 0x00 0x9c m12 loop-back status register - 5 r/o 0x00 0x9d m12 loop-back interrupt status/enable register - 6 r/w & rur 0x00 0x9e m12 loop-back status register - 6 r/o 0x00 0x9f m12 loop-back interrupt status/enable register - 7 r/w & rur 0x00 0xa0 m12 loop-back status register - 7 r/o 0x00 0xa1 ds2 framer interrupt enable register - 1 r/w 0x00 0xa2 ds2 framer interrupt register - 1 rur 0x00 0xa3 ds2 framer interrupt status register - 1 r/o 0x00 0xa4 ds2 framer interrupt enable register - 2 r/w 0x00 t able 4: r egister a ddress m ap a ddress r egister n ame t ype d efault v alue ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 83 2.3.2.2 operating mode register bit 7 - local loop-back mode this bit-field permits the user to configure the XRT72L13 m13 device to operate in the local loop- back mode. setting this bit-field to 1 configures the XRT72L13 m13 chip to operate in the local loopback mode. setting this bit-field to 0 configures the XRT72L13 m13 chip to not operate in the local loopback mode. bit 6 - line loopback mode this bit-field permits the user to configure the XRT72L13 m13 device to operate in the line loop- back mode. setting this bit-field to 1 configures the XRT72L13 m13 chip to operate in the line loopback mode. setting this bit-field to 0 configures the XRT72L13 m13 chip to not operate in the line loopback mode. bit 5 - internal los enable this read/write bit-field permits the user to config- ure the XRT72L13 m13 chip to either declare an los (loss of signal) condition, based upon the internal circuits criteria or not. setting this bit-field to 0 configures the XRT72L13 m13 chip to not declare an los condition, based upon its own internal criteria. 0xa5 ds2 framer interrupt register - 2 rur 0x00 0xa6 ds2 framer interrupt status register - 2 r/o 0x00 0xa7 ds2 framer interrupt enable register - 3 r/w 0x00 0xa8 ds2 framer interrupt register - 3 rur 0x00 0xa9 ds2 framer interrupt status register - 3 r/o 0x00 0xaa ds2 framer interrupt enable register - 4 r/w 0x00 0xab ds2 framer interrupt register - 4 rur 0x00 0xac ds2 framer interrupt status register - 4 r/o 0x00 0xad ds2 framer interrupt enable register - 5 r/w 0x00 0xae ds2 framer interrupt register - 5 rur 0x00 0xaf ds2 framer interrupt status register - 5 r/o 0x00 0xb0 ds2 framer interrupt enable register - 6 r/w 0x00 0xb1 ds2 framer interrupt register - 6 rur 0x00 0xb2 ds2 framer interrupt status register - 6 r/o 0x00 0xb3 ds2 framer interrupt enable register - 7 r/w 0x00 0xb4 ds2 framer interrupt register - 7 rur 0x00 0xb5 ds2 framer interrupt status register - 7 r/o 0x00 0xb6 - 0xff reserved 0x100 - 0x157 transmit lapd message buffer (pmdl messages) r/w 0x158 receive lapd message buffer (pmdl messages) r/o t able 4: r egister a ddress m ap a ddress r egister n ame t ype d efault v alue operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00101011 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 84 setting this bit-field to 1 configures the XRT72L13 los condition, based upon its own internal criteria. n otes : 1. the XRT72L13 m13 chip will declare an los condition anytime the rlos input pin is set high independent of the setting of this bit-field. 2. for more information on the XRT72L13 m13 chips internal criteria for loss of signal please see section _. bit 4 - reset this read/write bit-field permits the user to com- mand the XRT72L13 m13 chip into a software reset state. if the XRT72L13 m13 chip is commanded into the reset state, all of its internal register bits will automatically be set to their default condition. the user can configure the XRT72L13 to operate in the reset state by inducing a 0 to 1 transition in this bit-field. bit 3 - interrupt enable reset this read/write bit-field permits the user to config- ure the XRT72L13 m13 chip to automatically disable all interrupts that are activated. setting this bit-field to 0 configures the XRT72L13 m13 chip to not disable the interrupt enable status of any interrupt following their activation. setting this bit-field to 1 configures the XRT72L13 m13 to disable the interrupt enable status of any in- terrupt following their activation. for more information on this feature, please see sec- tion _. bit 2 - frame format select this read/write bit-field permits the user to select the framing format that the XRT72L13 m13 device will be operating in. setting this bit-field to 0 configures the XRT72L13 m13 device to operate in the c-bit parity framing format. setting this bit-field to 1 configures the XRT72L13 m13 device to operate in the m13 framing format. bits 1 and 0 - timrefsel[1:0] - timing reference select these two read/write bit-fields permits the user to select both a framing reference and a timing ref- erence for the transmit section of the XRT72L13. the following table relates the states of the two-fields to the selected framing and timing references. n ote : for more information on framing and timing refer- ences, please see section _. 2.3.2.3 i/o control register bit 7 - disable txloc to be provided in the next update. bit 6 - loc (loss of clock) indicator to be provided in the next update. bit 5 - disable rxloc to be provided in the next update. bit 4 - ami/b3zs* line code select this read/write bit-field pemits the user to config- ure the XRT72L13 m13 device to transmit and re- ceive data via the ami (alternate mark inversion) line code or via the b3zs (bipolar 3 zero substitution) line code. setting this bit-field to 0 configures the XRT72L13 m13 device to transmit and receive data (via the ds3 framer block) via the b3zs format. setting this bit- field to 1 configures the XRT72L13 m13 device to transmit and receive data via the ami line code. bit 3 - single-rail/dual-rail select this read/write bit-field permits the user to config- ure the XRT72L13 m13 device to operate in the sin- gle-rail or dual-rail format. t im r ef s el [1:0] f raming r eference t iming r eference 00 asynchronous rxlineclk input signal 01 txframeref rxlineclk input signal 10 asynchronous txinclk input signal 11 asynchronous txinclk input signal i/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/b3zs* line code single-rail/ dual-rail* txclkinv rxclkinv reframe r/w ro r/w r/w r/w r/w r/w r/w 10100000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 85 setting this bit-field to 0 configures the XRT72L13 to operate in the dual-rail mode. in this mode, the transmit section of the XRT72L13 m13 device will output data to the liu via the txpos and txneg output pins. additionally, the receive section of the device will receive data from the liu via rxpos and rxneg input pins. setting this bit-field to 1 configures the XRT72L13 to operate in the single-rail mode. in this mode, the transmit section of the XRT72L13 m13 device will output data to the liu, in a binary data stream man- ner via the txpos output pin. additionally, the re- ceive section of the device will receive data from the liu, in a binary data stream manner, via the rxpos input pin. bit 2 - txclkinv this read/write bit-field permits the user to config- ure the XRT72L13 m13 device to output data, via the txpos and txneg output pins, upon the rising or falling edge of txlineclk. setting this bit-field to 0 configures the XRT72L13 m13 device to output data via the txpos and tx- neg output pins, on the rising edge of txlineclk. setting this bit-field to 1 configures the XRT72L13 m13 device to output data via the txpos and tx- neg output pins, on the falling edge of txlineclk. bit 1 - rxclkinv this read/write bit-field permits the user to config- ure the XRT72L13 m13 device to latch data on the rxpos and rxneg input pins input pins, into the XRT72L13 m13 device, on the rising or falling edge of rxlineclk. setting this bit-field to 0 configures the XRT72L13 m13 device to latch the data on the rxpos and rxneg input pins, into the device, on the rising edge of rxlineclk. setting this bit-field to 1 configures the XRT72L13 m13 device to latch the data on the rxpos and rxneg input pins, into the device, on the falling edge of rxlineclk. bit 0 - reframe this read/write bit-field permits the user to config- ure the receive section of the XRT72L13 m13 de- vice to start a new frame search. a 0 to 1 transi- tion in this bit-field will force the chip to start a new frame search. 2.3.2.4 part number register the part number register (within the XRT72L13 m13 device) contains the fixed value of 0x22. this part number value permits the user to read out the con- tents of this register and to uniquely identify this de- vice as the XRT72L13 m13 device. 2.3.2.5 version number register the version number register (within the XRT72L13 m13 device) contains a value which corresponds to the revision number. the very first revision of the XRT72L13 (revision a) will contain the fixed value 0x01. the contents of the version number regis- ter will be incremented for subsequent version (if needed). part number register (address = 0x02) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 part number value ro ro ro ro ro ro ro ro 00100010 version number register (address = 0x03) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 version number value ro ro ro ro ro ro ro ro 00000001 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 86 2.3.2.6 block interrupt enable register bit 7 - rx ds3 interrupt enable this read/write bit-field permits the user to enable or disable all receive ds3 framer related interrupts (within the XRT72L13) at the block level. setting this bit-field to 0 disables all receive ds3 framer related interrupts within the XRT72L13 m13 device. setting this bit-field to 1 enables all receive ds3 framer related interrupts (within the XRT72L13 m13 device) at the block level. n ote : setting this bit-field to 1 does not enable all receive ds3 framer related interrupts. each of these interrupts can still be disabled at the source level. how- ever, setting this bit-field to 0 does disable all receive ds3 framer related interrupt. bit 4 - m13 interrupt enable this read/write bit-field permits the user to enable- or disable all m13 multiplexer related interrupts (within the XRT72L13) at the block level. setting this bit-field to 0 disables all m13 multiplex- er related interrupts within the XRT72L13 m13 de- vice. setting this bit-field to 1 disables all m13 multiplex- er related interrupts (within the XRT72L13 m13 de- vice) at the block level. bit 1 - tx ds3 interrupt enable this read/write bit-field permits the user to enable or disable the transmit ds3 framer related inter- rupts (within the XRT72L13) at the block level. setting this bit-field to 0 disables all transmit ds3 framer related interrupts within the XRT72L13 m13 device. setting this bit-field to 1 disables all transmit ds3 framer related interrupts (within the XRT72L13 m13 device) at the block level. bit 0 - one second interrupt enable this read/write bit-field permits the user to enable or disable the one second interrupt, within the XRT72L13. if this interrupt is enabled then the XRT72L13 will generate interrupts to the micropro- cessor/microcontroller at one-second intervals. setting this bit-field to 0 disables the one second interrupt. conversely, setting this bit-field to 1 en- ables the one second interrupt. 2.3.2.7 block interrupt status register bit 7 - rx ds3 interrupt status this read-only bit-field indicates whether or not a receive ds3 framer related interrupt has been re- quested and is awaiting service. if this bit-field is set to 0, then there are no receive ds3 framer related interrupts awaiting service. conversely, if this bit-field is set to 1, then there is at least one receive ds3 framer related interrupt, awaiting service. bit 4 - m13 multiplexer interrupt status block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx ds3 interrupt enable not used not used m13 interrupt enable not used not used tx ds3 interrupt enable] one second interrupt enable] r/w r/o r/o r/w r/o r/o r/w r/w 00000000 block interrupt status register (address = 0x05) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx ds3 interrupt status not used not used m13 interrupt status not used not used tx ds3 interrupt status one second interrupt status r/o r/o r/o r/o r/o r/o r/o rur 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 87 this read-only bit-field indicates whether or not an m13 multiplexer related interrupt has been request- ed and is awaiting service. if this bit-field is set to 0, then there are no m13 multiplexer related interrupts awaiting service. con- versely, if this bit-field is set to 1, then there is at least one m13 multiplexer related interrupt, awaiting service. bit 1 - tx ds3 interrupt status this read-only bit-field indicates whether or not a transmit ds3 framer related interrupt has been re- quested and is awaiting service. if this bit-field is set to 0, then there are no transmit ds3 framer related interrupts awaiting service. conversely, if this bit-field is set to 1, then there is at least one transmit ds3 framer related interrupt, awaiting service. bit 0 - one second interrupt status this reset-upon-read bit-field indicates whether or not a one second interrupt has been requested and is awaiting service. if this bit-field is set to 0, then the one second in- terrupt is not awaiting service. conversely, if this bit- field is set to 1, then the one second interrupt is awaiting service. n ote : this bit-field will be cleared immediately after the microprocessor/microcontroller has read this register. 2.3.2.8 rxfifo control register bit 1 - rxfifo32 - 32/64 operating depth select this read/write bit-field permits the user to config- ure the operating depth of the de-jitter fifo to be ei- ther 32 or 64 bits. setting this bit-field to 0 configures the operating depth of the de-jitter fifo to be 64 bits. setting this bit-field to 1 configures the operating depth of the de-jitter fifo to be 32 bits. n ote : this bit-field is ignored if the de-jitter fifo is dis- abled. bit 0 - rxfif0 enable this read/write bit-field permits the user to enable or disable the de-jitter fifo within the XRT72L13. setting this bit-field to 0 disables the de-jitter fifo. setting this bit-field to 1 enables the de-jitter fifo 2.3.2.9 m23 configuration register bit 6 - payload hdlc controller enable this bit-field along with m13 disable (bit 4) pemits the user to specify whether the XRT72L13 m13 de- vice is to operate in either of the following modes. ? the m13/channelized mode ? the ds3 clear channel framer mode ? the high speed hdlc controller mode. the relationship between these two bit-fields and the resulting operating operating mode of the XRT72L13 m13 device is tabulated below. rxfifo control register (address = 0x06) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used not used not used not used not used not used rxfifo32 rxfifo enable r/o r/o r/o r/o r/o r/o r/w r/w 00000000 m23 configuration register (address = 0x07) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used payload hdlc controller enable rxds1clk gapped (crc-32) m13 disable m13 loopback/ (remote loopback) tributary polarity m23 loopback code[1] m23 loopback code[0] r/o r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 88 bit 5 - rxds1clk gapped (crc-32) select the exact functionality of this bit-field depends upon whether the user is operating the XRT72L13 in the m13-channelized or in the high speed hdlc con- troller mode. m13-channelized mode - rxds1 gapped clock select in the m13-channelized mode, then this bit-field permits the user to either enable or disable the 28 digital pll blocks within the XRT72L13 m13 device. setting this bit-field to 0 enables all 28 of these dig- ital pll blocks. in this mode, all 28 (or 21) of the rxds1clk and rxds1data output signals will be smoothed by an internal digital pll. this permits the user to interface the receive ds1/e1 output inter- face to an external ds1 or e1 liu ic. setting this bit-field to 1 disables all 28 of these dig- ital pll blocks. in this mode, all 28 (or 21) of the rxds1clk and rxds1data output signals will not be smoothed by an internal digital pll, and will con- tain gaps. hdlc controller mode - crc16/32 select in the high speed hdlc controller mode, this bit- field permits the user to configure the XRT72L13 to compute and verify a crc-16 or crc-32 value within the hdlc frame. setting this bit-field to 0 configures the XRT72L13 to compute and verify a crc-16 value in each hdlc frame. setting this bit-field to 1 configures the XRT72L13 to compute and verify a crc-32 value in each hdlc frame. bit 4 - m13 disable this bit-field along with payload hdlc controller en- able (bit 6) pemits the user to specify whether the XRT72L13 m13 device is to operate in either of the following modes. ? the m13/channelized mode ? the ds3 clear channel framer mode ? the high speed hdlc controller mode. the relationship between these two bit-fields and the resulting operating operating mode of the XRT72L13 m13 device is tabulated below. bit 3 - m13 loopback/remote loopback the exact functionality of this bit-field depends upon whether the user is operating the XRT72L13 in the m13-channelized or in the high speed hdlc con- troller mode. m13-channelized mode - m13 loopback select if the XRT72L13 is operating in the m13 channel- ized mode, then this bit-field functions as the m13 loopback select bit-field. setting this bit-field to 0 disables the m13 loop- back mode. in this mode, the receive m13 block will accept data from the rx ds3 framer block (normal operation). setting this bit-field to 1 enables the m13 loop- back mode. in this mode, the receive m13 block ac- cepts data from the transmit m13 block (the trans- mit and receive ds3 framer blocks are bypassed). high speed hdlc controller mode - remote loopback select if the XRT72L13 is operating in the high speed hdlc controller mode, then this bit-field functions as the remote loopback select bit-field. setting this bit-field to 0 disables the remote loop- back mode. p ayload hdlc c ontroller e nable m13 d isable resulting o perating m ode 0 0 m13/ channelized mode 0 1 ds3 clear channel framer mode 1 0 m13/ channelized mode 1 1 high speed hdlc controller mode p ayload hdlc c ontroller e nable m13 d isable resulting o perating m ode 00m13/ channelized mode 0 1 ds3 clear channel framer mode 10m13/ channelized mode 1 1 high speed hdlc controller mode ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 89 setting this bit-field to 1 enables the remote loop- back mode. bit 2 - tributary polarity this read/write bit-field permits the user to select the clock edge at which (a) the XRT72L13 m13 de- vice will sample and latch the transmit ds1/e1 and transmit hdlc data, and (b) the XRT72L13 will out- put the receive ds1/e1 and receive hdlc data. setting this bit-field to 0 configures the XRT72L13 m13 device to (a) sample and latch the transmit ds1/e1 and transmit hdlc data on the rising edge of the appropriate clock signal; and (b) to output the receive ds1/e1 and receive hdlc data on the rising edge of the appropriate clock signal. setting this bit-field to 1 configures the XRT72L13 m13 device to (a) sample and latch the transmit ds1/e1 and transmit hdlc data on the falling edge of the appropriate clock signal; and (b) to output the receive ds1/e1 and receive hdlc data on the falling edge of the appropriate clock signal. bits 1 and 0 - m23lbcode[1, 0] n otes : these two read/write bits permit the user to define which c-bit pattern (in the inbound ds3 data stream) will function as the loopback command. these reg- ister bits are only used if the XRT72L13 m13 device is oper- ating in the m13 framing format. these register bits are ignored if the XRT72L13 m13 device is operating in the c- bit parity framing format. the following table related the contents of these two bit-fields to the m23 loopback code. a more detailed description of these loopback codes will be presented in section _. 2.3.2.10 m23 ds3 ais register bits 6 thru 0 - txds2 ais channel[6:0] these seven (7) read/write bit-fields permits the user to specify which outbound ds2 channel will transmit an ais (all ones) pattern. for example, setting bit 5 (within this register) to 1 configures the XRT72L13 m13 device to transmit an ais pattern via the outbound (transmit) ds2 chan- nel 5. in this mode, the content of the lower tributary txds1/e1 signals will be over-written by this ais pattern. setting bit 5 to 0 configures the transmit ds2 channel 5 to carry normal traffic (as determined by the lower ds1 or e1 tributaries). t able 5: m23l b c ode [1] m23 lb c ode [0] resulting m 23 loopback code 0 0 cj1 = cj2 = *cj3 0 1 cj1 = *cj2 = cj3 1 0 *cj1 = cj2 = cj3 1 1 cj1 = cj2 = *cj3 m23 tx ds2 ais register (address = 0x08) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txds2 ais channel 6 txds2 ais channel 5 txds2 ais channel 4 txds2 ais channel 3 txds2 ais channel 2 txds2 ais channel 1 txds2 ais channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 90 2.3.2.11 m23 request loopback register bits 6 thru 0 - ds2 loopback request channel [6:0] these seven (7) read/write bit-field permits the us- er to request that the remote terminal equipment configure one of their ds2 channels to operate in the remote loopback mode. setting any one of these bit-fields to 1 will cause the XRT72L13 m13 device to insert a ds2 remote loopback command request (for the corresponding ds2 channel) to be inserted into the outbound ds3 data stream. the remote terminal equipment should respond by executing the appropriate loop- back command. for example, setting bit 5 (within this register) will cause the XRT72L13 m13 device to insert the chan- nel 5 ds2 remote loopback command register in- to the outbound ds3 data stream. the remote ter- minal equipment will be expected to respond by con- figuring ds2 channel 5, into the remote loopback mode. n ote : this registert is only active if the XRT72L13 m13 device has been configured to operate in the m13/chan- nelized mode. 2.3.2.12 m23 loopback activation register bits 6 thru 0 - ds2 loopback activation channel [6:0] these seven (7) read/write bit-fields permit the us- er to configure any of the seven ds2 channels into the remote loopback mode. setting any one of these bit-fields to 1 will cause the corresponding ds2 channel to operate in the re- mote loopback mode. setting any one of these bit-fields to 0 will cause the corresponding ds2 channel to terminate remote loopback mode operation. 2.3.2.13 m23 rxais register m23 request loopback register (address = 0x09) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ds2 loopback request channel 6 ds2 loopback request channel 5 ds2 loopback request channel 4 ds2 loopback request channel 3 ds2 loopback request channel 2 ds2 loopback request channel 1 ds2 loopback request channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 m23 loopback activation register (address = 0x0a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ds2 loopback activation channel 6 ds2 loopback activation channel 5 ds2 loopback activation channel 4 ds2 loopback activation channel 3 ds2 loopback activation channel 2 ds2 loopback activation channel 1 ds2 loopback activation channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 m23 rx ds2 ais register (address = 0x0b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxds2 ais channel 6 rxds2 ais channel 5 rxds2 ais channel 4 rxds2 ais channel 3 rxds2 ais channel 2 rxds2 ais channel 1 rxds2 ais channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 91 bits 6 thru 0 - rxds2 ais channel [6:0] these seven (7) read/write bit-fields permits the user to specify which inbound ds2 channel (which is demultiplexed from the inbound ds3 channel) will carry an ais (all ones) pattern. for example, setting bit 5 (within this register) to 1 configures the XRT72L13 m13 device to overwrite the contents of the de-multiplexed ds2 channel (corre- sponding to channel 5) with the ais (all ones) pat- tern. setting bit 5 to 0 configures the receive ds2 channel 5 to carry normal traffic (as de-multiplexed from the inbound ds3 data stream). 2.3.2.14 ds3 test register bit 6 - rx payload clock enable this read/write bit-field permits the user to config- ure the receive payload data output interface (of the XRT72L13 m13 device) to generate either (a) a gapped-serial clock signal or (b) an ungapped-serial clock, along with an rxohind output signal. setting this bit-field to 0 configures the XRT72L13 to generate an ungapped (44.736mhz) clock sjgnal via the rxclk output pin, and to pulse the rxohind output pin, coincident with an overhead bit being out- put via the rxser output pin. setting this bit-field to 1 configures the XRT72L13 to generate a gapped clock signal (e.g., a clock edge for each payload bit) via the rxohind output pin. n ote : this feature is only applicable if the XRT72L13 has been configured to operate in the ds3 clear channel framer mode. bit 5 - tx payload clock enable this read/write bit-field permits the user to config- ure the transmit payload data input interface (or the XRT72L13 m13 device) to generate either (a) a gapped-serial clock signal or (b) an ungapped-serial clock, along with the txohind output signal. setting this bit-field to 0 configurese the XRT72L13 to accept an ungapped clock (44.736mhz) signal via the txinclk input pin (or to output an ungapped clock signal via the rxoutclk output pin). further, in this mode, the XRT72L13 will pulse the txohind output pin one bit period prior to the processing of an overhead bit. setting this bit-field to 1 configures the XRT72L13 to generate a gapped clock signal (e.g., a clock edge for each payload bit) via the txohind output pin. n ote : this feature is only applicable if the XRT72L13 has been configured to operate in the ds3 clear channel framer mode. bit 4 - rx prbs lock indicator this read-only bit-field indicates whether or not the prbs checker/receiver has acquired prbs lock with the payload portion of the inbound ds3 data stream. if this bit-field is set to 0 then the prbs checker/ receiver has not acquired prbs lock with the payload portion of the inbound ds3 data stream. conversely, if this bit-field is set to 1, then the prbs checker/receiver has acquired prbs lock (or pattern sync) with the payload portion of the in- bound ds3 data stream. n ote : the contents of this bit-field are valid only if the prbs checker/receiver is enabled. bit 3 - rx prbs enable this read/write bit-field permits the user to enable the prbs checker/receiver block within the XRT72L13 m13 device. setting this bit-field to 0 disables the prbs check- er/receiver block. setting this bit-field to 1 enables the prbs check- er/receiver block. bit 2 - tx prbs enable this read/write bit-field permits the user to enable or disable the prbs generator/transmitter block within the XRT72L13 m13 device. setting this bit-field to 0 disables the prbs gener- ator/transmitter block. setting this bit-field to 1 enables the prbs genera- tor/transmitter block. ds3 test register (address = 0x0c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx payload clock enable tx payload clock enable rx prbs lock indicator rx prbs enable tx prbs enable rx ds3 bypass tx ds3 bypass r/o r/w r/w r/o r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 92 bit 1 - rxds3 bypass to be defined in the next revision bit 0 - txds3 bypass to be defined in the next revision 2.3.2.15 rx ds3 configuration and status reg- siter bit 7 - rx ais (receive ais pattern) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is currently receiving an ais pattern or not. the XRT72L13 will set this bit-field to 0 if it is not currently detecting an ais pattern in the incoming da- ta stream. conversely, the XRT72L13 will set this bit- field to 1 if it is currently receiving an ais pattern in the incoming data stream. n ote : for a detailed discussion on the ais pattern please see section _. bit 6 - rx los (receive los condition) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is currently declaring an los (loss of signal) condition of the incoming ds3 data stream. if this bit-field is set to 0, then the receive ds3 framer block (within the chip) is currently not declar- ing an los condition. if this bit-field is set to 1, then the receive ds3 framer block (within the chip) is currently declaring an los condition. n ote : for more information on the los declaration crite- ria, please see section _. bit 5 - rx idle (receive idle pattern) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is currently detecting the idle pattern in the incoming ds3 data stream. if this bit-field is set to 0, then the receive ds3 framer block (within the chip) is currently not detect- ing the idle pattern. if this bit-field is set to 1, then the receive ds3 framer block (within the chip) is currently detecting the idle pattern. n ote : for more information about the idle pattern, please see section _. bit 4 - rx oof (receive out-of-frame) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is currently declaring an oof (out of frame) condition. if this bit-field is set to 0, then the receive ds3 framer block (of the chip) is currently not declaring the oof condition. if this bit-field is set to 1, then the receive ds3 framer block is currently declaring the oof condi- tion. n ote : for more information on the oof and in-frame declaration criteria (for ds3) please see section _. bit 2 - framing on parity on/off select this read/write bit-field permits the user to require that the receive ds3 framer block include p-bit verification as a condition for declaring itself in- frame, during frame acquisition. this feature also imposes an additional frame main- tenance requirement on the receive ds3 framer block. in particular, if this additional requirement is implemented, the receive ds3 framer block will perform a frame search if it detects p-bit errors in at least 2 out of 5 ds3 frames. setting this bit-field to 1 imposes this additional re- quirement. conversely, setting this bit-field to 0 configures the receive ds3 framer block to waive this require- ment. n ote : for more information on framing with parity, please see section _. bit 1 - fsync algo(rithm) select this read/write bit-field, in conjunction with bits 0 and 2 of this register, allows the user to completely define the frame maintenance criteria of the re- ceive ds3 framer block (within the chip). this par- rx ds3 configuration and status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx ais rx los rx idle rx oof reserved framing on parity fsync algo msync algo r/o r/o r/o r/o r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 93 ticular bit-field permits the user to define the frame maintenance criteria, as it applies to f-bits. setting this bit-field to 0 configures the receive ds3 framer block to declare an oof (out of frame condition) if it determines that 6 out of the last 16 f-bits are in error. setting this bit-field to 1 configures the receive ds3 framer block to declare an oof (out of frame condition) if it determines that 3 out of the last 16 f-bits are in error. bit 0 - msync algo(rithm) select this read/write bit-field, in conjunction with bits 1 and 2 of this register, allows the user to completely define the frame maintenance criteria of the re- ceive ds3 framer block (within the chip). this par- ticular bit-field permits the user to define the frame maintenance criteria, as it applies to m-bits. setting this bit-field to 0 configures the receive ds3 framer block to ignore the occurrence of m-bit errors. setting this bit-field to 1 configures the receive ds3 framer block to declare an oof condition if it determines that 3 out of 4 m-bits are in error. 2.3.2.16 rxds3 status register bit 4 - rxferf (far-end receive failure) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is declaring a ferf (far-end receive failure) condition. if this bit-field is set to 0, then the receive ds3 framer block (of the chip) is currently not declaring a ferf condition. conversely, if this bit-field is set to 1, then the re- ceive ds3 framer block is currently declaring a ferf condition. n ote : for more information how the receive ds3 framer block declares a ferf condition, please see section _. bit 3 - rxaic (application identification channel) indicator this read-only bit-field reflects the value of the aic bit-field, within the most recently received ds3 frames, as detected by the receive ds3 framer block. this bit-field is set to 1 if the incoming ds3 data stream is determined to be in the c-bit parity format (aic bit = 1) for at least 63 consecutive frames. this bit-field is set to 0 if the incoming ds3 data stream is determined to be in the m13 format (aic bit = 0). bits 2 thru 0 - rxfebe[2:0] these read-only bit-fields reflect the febe (far- end block error) value, within the most recently re- ceived ds3 frame. if these bit-fields are set to 111, then it indicates that the remote receiving terminal is receiving ds3 frames in an un-erred manner. conversely, if these bit-fields are set to any value oth- er than 111, then it indicates that the remote re- ceiving terminal has detected framing or parity bit errors in the ds3 frames that it is receiving. n ote : for more information on febe (far-end-block error), please see section _. rx ds3 status register (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used not used not used rxferf rxaic rxfebe[2] rxfebe[1] rxfebe[0] r/o r/w r/w r/o r/o r/o r/o r/o 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 94 2.3.2.17 rxds3 interrupt enable register bit 7 - detection of cp-bit error interrupt enable this read/write bit-field permits the user to enable or disable the detection of cp-bit error interrupt. setting this bit-field to 0 disables the detection of cp-bit error interrupt. setting this bit-field to 1 enables the detection of cp-bit error interrupt. bit 6 - change in los condition interrupt enable this read/write bit-field permits the user to enable or disable the change in los condition interrupt. setting this bit-field to 0 disables the change in los condition interrupt. setting this bit-field to 1 enables the change in los condition interrupt. bit 5 - change in ais condition interrupt enable this read/write bit-field permits the user to enable or disable the change in ais condition interrupt. setting this bit-field to 0 disables the change in ais condition interrupt. setting this bit-field to 1 enables the change in ais condition interrupt. bit 4 - change in idle pattern condition interrupt enable this read/write bit-field permits the user to enable or disable the change in idle pattern condition in- terrupt. setting this bit-field to 0 disables the change in idle pattern condition interrupt. setting this bit-field to 1 enables the change in idle pattern condition interrupt. bit 3 - change in ferf condition interrupt enable this read/write bit-field permits the user to enable or disable the change in ferf condition interrupt. setting this bit-field to 0 disables the change in ferf condition interrupt. setting this bit-field to 1 enables the change in ferf condition interrupt. bit 2 - change in aic state interrupt enable this read/write bit-field permits the user to enable or disable the change in aic state interrupt. setting this bit-field to 0 disables the change in aic state interrupt. setting this bit-field to 1 enables the change in aic state interrupt. bit 1 - change in oof condition interrupt enable this read/write bit-field permits the user to enable or disable the change in oof condition interrupt. setting this bit-field to 0 disables the change in oof condition interrupt. setting this bit-field to 1 enables the change in oof condition interrupt. bit 0 - detection of p-bit error interrupt enable this read/write bit-field permits the user to enable or disable the detection of p-bit error interrupt. setting this bit-field to 0 disables the detection of p-bit error interrupt. setting this bit-field to 1 enables the detection of p- bit error interrupt. rx ds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 detection of cp-bit error interrupt enable change in los condition interrupt enable change in ais condition interrupt enable change in idle pattern interrupt enable change in ferf condition interrupt enable change in aic state interrupt enable change in oof condition interrupt enable detection of p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 95 2.3.2.18 rxds3 interrupt status register bit 7 - detection of cp-bit error interrupt status this reset-upon-read bit-field indicates whether or not the receive ds3 framer block has detected a cp-bit error in the inbound ds3 data stream, since the last time this register was read. this bit-field will be 0 if the detection of cp-bit er- ror interrupt has not occured since the last read of this register. this bit-field will be 1 if the interrupt has occurred since the last read of this register. bit 6 - change in los (loss of signal) condition interrupt status this reset-upon-read bit-field will be set to 1 if the receive ds3 framer block has detected a change in los condition, since the last time this register was read. if the change in los condition interrupt is enabled, then this bit-field will be asserted under either of the following conditions. a. when the receive ds3 framer block detects the occurrence of an los condition (e.g., the occurrence of 180 consecutive spaces in the incoming ds3 data stream), and b. when the receive ds3 framer block detects the end of an los condition (e.g., when the receive ds3 framer block detects at least 60 mark pulses in the last 180 bit periods). the microprocessor/microcontroller can determine the state of the los condition by reading bit 6, within the rx ds3 configuration and status register (ad- dress location = 0x10). n ote : for more information about the los condition please see section _. bit 5 - change in ais (alarm indication signal) condition interrupt status this reset-upon-read bit-field will be set to 1 if the receive ds3 framer block has detected a change in ais condition, since the last time this reg- ister was read. if the change in ais condition inter- rupt is enabled, then this bit-field will be asserted un- der either of the following conditions. a. when the receive ds3 framer block first detects an ais condition in the inbound ds3 data stream. b. when the receive ds3 framer block has detected the end of an ais condition. the microprocessor/microcontroller can determine the state of the ais condition by reading bit 7, within the rx ds3 configuration and status register (ad- dress location = 0x10). n ote : for more information about the ais condition please see section _. bit 4 - change in idle pattern condition interrupt status this reset-upon-read bit-field is set to 1 when the receive ds3 framer block detects a change in idle condition in the incoming ds3 data stream. specifi- cally, the receive ds3 framer block will assert this bit-field under either of the following two conditions. a. when the receive ds3 framer block initially detects the idle pattern in the inbound ds3 data stream. b. when the receive ds3 framer block ceases to detect the idle pattern in the inbound ds3 data stream. the microprocessor/microcontroller can determine the state of the idle pattern condition by reading bit 5, within the rx ds3 configuration and status regis- ter (address location = 0x10). n ote : for more information about the idle pattern please see section _. bit 3 - change in ferf condition interrupt status this reset-upon-read bit-field is set to 1 if the receive ds3 framer block (within the XRT72L13 m13 device) has detected a change in the ferf condition, since the last time this register was read. rx ds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 detection of cp-bit error interrupt status change in los condition interrupt status change in ais condition interrupt status change in idle pattern condition interrupt status change in ferf condition interrupt status change in aic state interrupt status change in oof condition interrupt status detection of p-bit error interrupt status rurrurrurrurrurrurrurrur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 96 this bit-field will be asserted under either of the fol- lowing conditions. a. when the receive ds3 framer block first detects the occurrence of a ferf condition in the inbound ds3 data stream (e.g., all x-bits are set to 0). b. when the receive ds3 framer block no longer detects the ferf condition in the inbound ds3 data stream (e.g., all x-bits are set to 1). the microprocessor/microcontroller can determine the state of the of the ferf condition by reading bit 4 within the rx ds3 status register (address loca- tion = 0x11). n ote : for more information about the ferf condition, please see section _. bit 2 - change in aic state interrupt status this reset-upon-read bit-field is set to 1 if the aic bit-field, within the incoming ds3 data stream, has changed state since the last read of this register. the microprocessor/microcontroller can determine the state of the aic bit-field by reading bit 3, within the rx ds3 status register (address location = 0x11). n ote : for more information on this interrupt condition, please see section _. bit 1 - change in oof condition interrupt status the reset-upon-read bit-field is set to 1 if the receive ds3 framer block (within the XRT72L13) has detected a change in the out-of-frame (oof) condition, since the last time this register was read. this bit-field will be asserted under either of the fol- lowing conditions. a. when the receive ds3 framer block has detected the appropriate condition to declare an oof condition. b. when the receive ds3 framer block has tran- sitioned from the oof condition (frame acquisi- tion mode). the microprocessor/microcontroller can detemine the state of the oof condition by reading bit 4 within the rx ds3 configuration and status register (ad- dress location = 0x10). n ote : for more information about the oof condition, please see section _. bit 0 - detection of p-bit error interrupt status this reset-upon-read bit-field indicates whether or not the detection of p-bit error interrupt has oc- curred since the last read of this register. this bit-field will be 0 if the receive ds3 framer block (within the XRT72L13 m13 device) has not de- tected a p-bit error since the last read of this register. conversely, this bit-field will be 1 if the receive ds3 framer block (within the XRT72L13 m13 de- vice) has detected a p-bit error since the last read of this register. 2.3.2.19 rxds3 sync detect register bit 1 - f algorithm to be provided in the next revision. bit 0 - one and only one to be provided in the next revision. 2.3.2.20 rxds3 feac register this "read/write" register contains the latest 6-bit feac code that has been "validated" by the receive feac processor. the contents of this register will be cleared if the previously "validated" code has been "removed" by the feac processor. rx ds3 sync detect register (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used not used not used reserved reserved reserved f algorithm one and only one r/o r/o r/o r/o r/o r/o r/w r/w 00000000 rxds3 feac register (address = 0x16) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxfeac[5:0] not used r/o r/o r/o r/o r/o r/o r/o r/o 01111110 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 97 2.3.2.21 rxds3 feac interrupt enable/status register bit 4 - feac valid this "read only" bit is set to "1" when an incoming feac message code has been validated by the re- ceive ds3 framer. this bit is cleared to "0" when the feac code is removed. n ote : for more information on the role of this bit-field and the receive feac processor, please see section _. bit 3 - rxfeac remove interrupt enable this "read/write" bit-field allows the user to enable/ disable the "rxfeac removal" interrupt. writing a "1" to this bit enables this interrupt. likewise, writing a "0" to this bit-field disables this interrupt. n ote : for more information on the role of this bit-field and the receive feac processor, please see section _. bit 2 - rxfeac remove interrupt status a "1" in this "read only" bit-field indicates that the last "validated" feac message has now been re- moved by the receive feac processor. the re- ceive feac processor will remove a validated feac message if 3 out of the last 10 received feac mes- sages differ from the latest valid feac message. n ote : for more information on this bit-field and the receive feac processor, please see section _. bit 1 - rxfeac valid interrupt enable this "read/write" bit-field allows the user to enable/ disable the "rx feac valid" interrupt. writing a "1" to this bit-field enables this interrupt. whereas, writing a "0" disables this interrupt. the value of this bit-field is "0" following power up or reset. n ote : for more information on this bit-field and the receive feac processor, please see section _. bit 0 - rxfeac valid interrupt status a "1" in this "read only" bit-field indicates that a new- ly received feac message has been validated by the receive feac processor. n ote : for more information on this bit-field and the receive feac processor, please see section _. 2.3.2.22 rxds3 lapd control register bit 3 rxlapd any to be provided in the next revision. bit 2 rxlapd enable this "read/write" bit-field allows the user to enable or disable the lapd receiver. the lapd receiver must be enabled before it can begin to receive and process any lapd message frames from the incom- ing ds3 data stream. writing a "0" to this bit-field disables the lapd re- ceiver (the default condition). writing a "1" to this bit- field enables the lapd receiver. bit 1 rxlapd (message frame reception com- plete) interrupt enable this "read/write" bit-field allows the user to enable or disable the "lapd message frame reception complete" interrupt. if this interrupt is enabled, then the uni will generate this interrupt to the local p, once the last bit of a lapd message frame has been rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status r/o r/o r/o r/o r/w rur r/w rur 00000000 rxds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd any rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 98 received and the pmdl message has been extracted and written into the "receive lapd message" buffer. writing a "0" to this bit-field disables this interrupt (the default condition). writing a "1" to this bit-field en- ables this interrupt. bit 0 rxlapd (message reception complete) in- terrupt status this "read-only" bit field indicates whether or not the "lapd message reception complete" interrupt has occurred since the last read of this register. the "lapd message reception complete" interrupt will occur once the lapd receiver has received the last bit of a complete lapd message frame, extracted the pmdl message from this lapd message frame and has written this (pmdl) message frame into the "re- ceive lapd message" buffer. the purpose of this in- terrupt is to notify the local p that the "receive lapd message" buffer contains a new pmdl mes- sage, that needs to be read and/or processed. a "0" in this bit-field indicates that the "lapd mes- sage reception complete" interrupt has not oc- curred since the last read of this register. a "1" in this bit-field indicates that the "lapd message reception complete" interrupt has occurred since the last read of this register. n ote : for more information on the lapd receiver, please see section _. 2.3.2.23 rxds3 lapd status register bit 6 - rxabort (receive abort sequence) this "read-only" bit-field indicates whether or not the lapd receiver has detected the occurrence of an "abort sequence" (e.g., a string of seven or more consecutive "1s") from the "far-end" lapd transmit- ter. a "0" in this bit-field indicates that no "abort-se- quence" has been detected. a "1" in this bit-field indi- cates that the "abort-sequence" has been detected. n ote : for more information on the lapd receiver, please see section _. bits, 5 and 4 - rxlapdtype[1, 0] these two "read only" bit-fields combine to indicate the "type" of lapd message frame that has been re- ceived by the lapd receiver. the relationship be- tween these two bit-fields and the lapd message type follows: bit 3 - rxcr (command/response) type this "read only" bit field indicates the value of the c/ r (command/response) bit-field of the latest re- ceived lapd message. bit 2 - rx fcs (frame check sequence) error this "read-only" bit-field indicates whether or not the lapd receiver has detected a "frame check se- quence" (fcs) error in the newly received lapd message frame. a "0" in this bit-field indicates that the fcs for the latest received lapd message frame is correct. a "1" in this bit-field indicates that the fcs for the latest received lapd message frame is incor- rect. n ote : for more information on the lapd receiver, please see section _. bit 1 - end of message this "read-only" bit-field indicates whether or not the lapd receiver has completed its reception of the lat- est incoming lapd message frame. the local p can poll the progress of the lapd receiver by peri- odically reading this bit-field. a "0" in this bit-field indicates that the lapd receiver is still receiving the latest message from the "far end" lapd transmitter. a "1" in this bit-field indicates that the lapd receiver has finished receiving the com- plete lapd message frame. rxds3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0} rxcr type rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000000 b it 5b it 4m essage t ype m essage length test signal identification 76 bytes 0 1 idle signal identification 76 bytes cl path identification 76 bytes itu-t path identification 82 bytes ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 99 bit 0 - flag present this "read-only" bit-field indicates whether or not the lapd receiver has detected the occurrence of the flag sequence byte (0x7e). a "0" in this bit-field indi- cates that the lapd receiver does not detect the oc- currence of the flag sequence byte. a "1" in this bit- field indicates that the lapd receiver does detect the occurrence of the flag sequence byte. n ote : for more information on the lapd receiver, please see section _. 2.3.2.24 m12 ds2 # 1 configuration register) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 1. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk3 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_3 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk3 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 1 via the rxds1data3 output pin. setting this bit-field to 1 configures m12 mux # 1 and m12 demux # 1 to be bypassed. setting this bit-field to 0 enables m12 mux # 1 and m12 demux # 1. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 1 and demux # 1 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 1 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data0 thru txds1data3) and will muitiplex these signals into a ds2 signal. like- wise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multiplex this signal into 4 ds1 signals. these four ds1 sig- nals will be output via the rxds1data0 thru rxds1data3 output pins. setting this bit-field to 1 configures m12 # 1 to support itu-t g.747. in this mode, the m12 mux will accept 3 e1 signals (via txds1data0 thru txds1data2) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data0 thru rxds1data2 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 1 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 100 2.3.2.25 m12 ds2 # 2 configuration register) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 1. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk7 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_7 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk7 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 2 via the rxds1data7 output pin. setting this bit-field to 1 configures m12 mux # 1 and m12 demux # 2 to be bypassed. setting this bit-field to 0 enables m12 mux # 1 and m12 demux # 2. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 2 and demux # 2 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 1 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data0 thru txds1data3) and will muitiplex these signals into a ds2 signal. like- wise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multiplex this signal into 4 ds1 signals. these four ds1 sig- nals will be output via the rxds1data0 thru rxds1data3 output pins. setting this bit-field to 1 configures m12 # 2 to support itu-t g.747. in this mode, the m12 mux will accept 3 e1 signals (via txds1data4 thru txds1data6) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data4 thru rxds1data6 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 2 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 2.3.2.26 m12 ds2 # 3 configuration register ) m12 ds2 # 2 configuration register (address = 0x1b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 m12 ds2 # 3 configuration register (address = 0x1c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 101 bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 3. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk11 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_11 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk11 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 2 via the rxds1data11 output pin. setting this bit-field to 1 configures m12 mux # 3 and m12 demux # 3 to be bypassed. setting this bit-field to 0 enables m12 mux # 3 and m12 demux # 3. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 3 and demux # 3 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 3 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data8 thru txds1data11) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data8 thru rxds1data11 output pins. setting this bit-field to 1 configures m12 # 3 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data8 thru txds1data10) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data8 thru rxds1data10 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 3 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 2.3.2.27 m12 ds2 # 4 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 4. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk15 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_15 input pin m12 ds2 # 4 configuration register (address = 0x1d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 102 in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk15 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 4 via the rxds1data15 output pin. setting this bit-field to 1 configures m12 mux # 4 and m12 demux # 4 to be bypassed. setting this bit-field to 0 enables m12 mux # 4 and m12 demux # 4. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 4 and demux # 4 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 4 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data12 thru txds1data15) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data12 thru rxds1data15 output pins. setting this bit-field to 1 configures m12 # 4 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data12 thru txds1data14) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data12 thru rxds1data14 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 4 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 2.3.2.28 m12 ds2 # 5 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 5. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk19 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_19 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk19 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 2 via the rxds1data19 output pin. setting this bit-field to 1 configures m12 mux # 5 and m12 demux # 5 to be bypassed. setting this bit-field to 0 enables m12 mux # 5 and m12 demux # 5. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 5 and demux # 5 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 5 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data16 thru txds1data19) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming m12 ds2 # 5 configuration register (address = 0x1e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 103 ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data16 thru rxds1data19 output pins. setting this bit-field to 1 configures m12 # 5 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data16 thru txds1data18) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data16 thru rxds1data18 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 5 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 2.3.2.29 m12 ds2 # 6 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 6. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk23 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_23 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk23 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 6 via the rxds1data23 output pin. setting this bit-field to 1 configures m12 mux # 6 and m12 demux # 6 to be bypassed. setting this bit-field to 0 enables m12 mux # 6 and m12 demux # 6. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 6 and demux # 6 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 6 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data20 thru txds1data23) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data20 thru rxds1data23 output pins. setting this bit-field to 1 configures m12 # 6 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data20 thru txds1data22) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data20 thru rxds1data22 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 6 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). m12 ds2 # 6 configuration register (address = 0x1f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 104 setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 2.3.2.30 m12 ds2 # 7 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 6. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk23 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_23 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk23 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 6 via the rxds1data23 output pin. setting this bit-field to 1 configures m12 mux # 6 and m12 demux # 6 to be bypassed. setting this bit-field to 0 enables m12 mux # 6 and m12 demux # 6. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 6 and demux # 6 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 6 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data20 thru txds1data23) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data20 thru rxds1data23 output pins. setting this bit-field to 1 configures m12 # 6 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data20 thru txds1data22) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data20 thru rxds1data22 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 6 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] m12 ds2 # 7 configuration register (address = 0x20) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 105 2.3.2.31 m12 ds2 # 1 ais register ) bit 7 - insert ais rx ds1 channel 3 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 3 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data3 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 6 - insert ais rx ds1 channel 2 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 2 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data2 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 5 - insert ais rx ds1 channel 1 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 1 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data1 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 4 - insert ais rx ds1 channel 0 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 0 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data0 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 3 - insert ais tx ds1 channel 3 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 3 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 3 to be transmitted as received (via the txds1data3 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 2 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 3 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 2 to be transmitted as received (via the txds1data2 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 1 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 1 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 1 to be transmitted as received (via the txds1data1 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 0 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 0 to be overwritten with an all ones pattern. m12 ds2 # 1 ais register (address = 0x21) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 3 insert ais rx ds1 channel 2 insert ais rx ds1 channel 1 insert ais rx ds1 channel 0 insert ais tx ds1 channel 3 insert ais tx ds1 channel 2 insert ais tx ds1 channel 1 insert ais tx ds1 channel 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 106 setting this bit-field to 0 permits the contents of ds1 channel 0 to be transmitted as received (via the txds1data0 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 2.3.2.32 m12 ds2 # 2 ais register ) bit 7 - insert ais rx ds1 channel 7 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 7 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data7 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 6 - insert ais rx ds1 channel 6 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 6 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data6 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 5 - insert ais rx ds1 channel 5 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 5 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data5 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 4 - insert ais rx ds1 channel 4 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 4 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data4 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 3 - insert ais tx ds1 channel 7 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 7 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 7 to be transmitted as received (via the txds1data7 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 6 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 6 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 6 to be transmitted as received (via the txds1data2 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 5 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 5 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 5 to be transmitted as received (via the txds1data5 input pin). m12 ds2 # 2 ais register (address = 0x22) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 7 insert ais rx ds1 channel 6 insert ais rx ds1 channel 5 insert ais rx ds1 channel 4 insert ais tx ds1 channel 7 insert ais tx ds1 channel 6 insert ais tx ds1 channel 5 insert ais tx ds1 channel 4 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 107 setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 4 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 4 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 4 to be transmitted as received (via the txds1data4 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 2.3.2.33 m12 ds2 # 3 ais register ) bit 7 - insert ais rx ds1 channel 11 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 11 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data11 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 6 - insert ais rx ds1 channel 10 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 10 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data10 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 5 - insert ais rx ds1 channel 9 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 9 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data9 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 4 - insert ais rx ds1 channel 8 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 8 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data8 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 3 - insert ais tx ds1 channel 11 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 11 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 11 to be transmitted as received (via the txds1data11 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 10 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 10 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 10 to be transmitted as received (via the txds1data10 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 9 m12 ds2 # 3 ais register (address = 0x23) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 11 insert ais rx ds1 channel 10 insert ais rx ds1 channel 9 insert ais rx ds1 channel 8 insert ais tx ds1 channel 11 insert ais tx ds1 channel 10 insert ais tx ds1 channel 9 insert ais tx ds1 channel 8 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 108 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 9 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 8 to be transmitted as received (via the txds1data9 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 8 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 8 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 8 to be transmitted as received (via the txds1data8 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 2.3.2.34 m12 ds2 # 4 ais register ) bit 7 - insert ais rx ds1 channel 15 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 15 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data15 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 6 - insert ais rx ds1 channel 14 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 14 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data14 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 5 - insert ais rx ds1 channel 13 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 13 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data13 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 4 - insert ais rx ds1 channel 12 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 12 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data12 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 3 - insert ais tx ds1 channel 15 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 15 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 15 to be transmitted as received (via the txds1data15 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 14 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 14 to be overwritten with an all ones pattern. m12 ds2 # 4 ais register (address = 0x24) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 15 insert ais rx ds1 channel 14 insert ais rx ds1 channel 13 insert ais rx ds1 channel 12 insert ais tx ds1 channel 15 insert ais tx ds1 channel 14 insert ais tx ds1 channel 13 insert ais tx ds1 channel 12 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 109 setting this bit-field to 0 permits the contents of ds1 channel 14 to be transmitted as received (via the txds1data14 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 13 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 13 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 13 to be transmitted as received (via the txds1data13 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 12 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 12 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 12 to be transmitted as received (via the txds1data12 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 2.3.2.35 m12 ds2 # 5 ais register ) bit 7 - insert ais rx ds1 channel 19 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 19 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data19 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 6 - insert ais rx ds1 channel 18 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 18 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data18 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). m12 ds2 # 5 ais register (address = 0x25) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 19 insert ais rx ds1 channel 18 insert ais rx ds1 channel 17 insert ais rx ds1 channel 16 insert ais tx ds1 channel 19 insert ais tx ds1 channel 18 insert ais tx ds1 channel 17 insert ais tx ds1 channel 16 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 110 bit 5 - insert ais rx ds1 channel 17 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 17 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data17 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 4 - insert ais rx ds1 channel 16 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 16 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data16 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 3 - insert ais tx ds1 channel 19 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 19 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 19 to be transmitted as received (via the txds1data19 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 18 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 18 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 18 to be transmitted as received (via the txds1data18 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 17 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 17 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 17 to be transmitted as received (via the txds1data17 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 16 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 16 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 16 to be transmitted as received (via the txds1data16 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 2.3.2.36 m12 ds2 # 6 ais register ) bit 7 - insert ais rx ds1 channel 23 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 23 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data23 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 6 - insert ais rx ds1 channel 22 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 22 to be overwritten with an all ones pattern. m12 ds2 # 6 ais register (address = 0x26) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 23 insert ais rx ds1 channel 22 insert ais rx ds1 channel 21 insert ais rx ds1 channel 20 insert ais tx ds1 channel 23 insert ais tx ds1 channel 22 insert ais tx ds1 channel 21 insert ais tx ds1 channel 20 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 111 setting this bit-field to 0 permits data to be output (via the rxds1data22 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. bit 5 - insert ais rx ds1 channel 21 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 21 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data21 output pin), as demultiplexed via the inbound ds2 and ds3 data streams. bit 4 - insert ais rx ds1 channel 20 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 20 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data20 output pin), as demultiplexed via the inbound ds2 and ds3 data streams. bit 3 - insert ais tx ds1 channel 23 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 23 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 23 to be transmitted as received (via the txds1data23 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 22 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 22 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 22 to be transmitted as received (via the txds1data22 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 21 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 21 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 21 to be transmitted as received (via the txds1data21 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 20 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 20 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 20 to be transmitted as received (via the txds1data20 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 2.3.2.37 m12 ds2 # 7 ais register ) bit 7 - insert ais rx ds1 channel 27 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 27 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data27 output pin), as demultiplexed via the inbound ds2 and ds3 data streams. bit 6 - insert ais rx ds1 channel 26 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 26 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data26 output pin), as demultiplexed via the inbound ds2 and ds3 data streams. m12 ds2 # 7 ais register (address = 0x27) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 27 insert ais rx ds1 channel 26 insert ais rx ds1 channel 25 insert ais rx ds1 channel 24 insert ais tx ds1 channel 27 insert ais tx ds1 channel 26 insert ais tx ds1 channel 25 insert ais tx ds1 channel 24 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 112 bit 5 - insert ais rx ds1 channel 25 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 25 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data25 output pin), as demultiplexed via the inbound ds2 and ds3 data streams. bit 4 - insert ais rx ds1 channel 24 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 24 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data24 output pin), as demultiplexed via the inbound ds2 and ds3 data streams. bit 3 - insert ais tx ds1 channel 27 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 27 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 27 to be transmitted as received (via the txds1data27 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 26 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 26 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 26 to be transmitted as received (via the txds1data26 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 25 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 25 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 25 to be transmitted as received (via the txds1data25 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 24 this read/write bit-field permits the user to config- ure the contents of the outbound ds1 channel 24 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 24 to be transmitted as received (via the txds1data24 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 2.3.2.38 m12 ds2 # 1 loopback request regis- ter ) bit 7 - loop-back activation - ds1 channel 3 this read/write bit-field permits the user to config- ure ds1 channel 3 into remote loop-back mode. when this loop-back is configured, then the rxds1data_3 signal will internally be looped-back into the txds1data_3 path. further, the rxds1clock_3 clock signal will also be internally looped back into the rxds1clock_3 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 6 - loop-back activation - ds1 channel 2 this read/write bit-field permits the user to config- ure ds1 channel 2 into remote loop-back mode. when this loop-back is configured, then the rxds1data_2 signal will internally be looped-back into the txds1data_2 path. further, the rxds1clock_2 clock signal will also be internally looped back into the rxds1clock_2 signal path. m12 ds2 # 1 loop-back register (address = 0x28) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 loop-back activation ds1 channel 3 loop-back activation ds1 channel 2 loop-back activation ds1 channel 1 loop-back activation ds1 channel 0 loop-back request ds1 channel 3 loop-back request ds1 channel 2 loop-back request ds1 channel 1 loop-back request ds1 channel 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 113 setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 5 - loop-back activation - ds1 channel 1 this read/write bit-field permits the user to config- ure ds1 channel 1 into remote loop-back mode. when this loop-back is configured, then the rxds1data_1 signal will internally be looped-back into the txds1data_1 path. further, the rxds1clock_1 clock signal will also be internally looped back into the rxds1clock_1 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 4 - loop-back activation - ds1 channel 0 this read/write bit-field permits the user to config- ure ds1 channel 0 into remote loop-back mode. when this loop-back is configured, then the rxds1data_0 signal will internally be looped-back into the txds1data_0 path. further, the rxds1clock_0 clock signal will also be internally looped back into the rxds1clock_0 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 3 - loop-back request - ds1 channel 3 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 3 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 3 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 2 - loop-back request - ds1 channel 2 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 2 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 2 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 1 - loop-back request - ds1 channel 1 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 1 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 1 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 0 - loop-back request - ds1 channel 0 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 0 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 0 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.39 m12 ds2 # 2 loopback request regis- ter ) bit 7 - loop-back activation - ds1 channel 7 this read/write bit-field permits the user to config- ure ds1 channel 7 into remote loop-back mode. when this loop-back is configured, then the rxds1data_7 signal will internally be looped-back into the txds1data_7 path. further, the rxds1clock_7 clock signal will also be internally looped back into the rxds1clock_7 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. m12 ds2 # 2 loop-back register (address = 0x29) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 loop-back activation ds1 channel 7 loop-back activation ds1 channel 6 loop-back activation ds1 channel 5 loop-back activation ds1 channel 4 loop-back request ds1 channel 7 loop-back request ds1 channel 6 loop-back request ds1 channel 5 loop-back request ds1 channel 4 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 114 bit 6 - loop-back activation - ds1 channel 6 this read/write bit-field permits the user to config- ure ds1 channel 6 into remote loop-back mode. when this loop-back is configured, then the rxds1data_6 signal will internally be looped-back into the txds1data_6 path. further, the rxds1clock_6 clock signal will also be internally looped back into the rxds1clock_6 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 5 - loop-back activation - ds1 channel 5 this read/write bit-field permits the user to config- ure ds1 channel 5 into remote loop-back mode. when this loop-back is configured, then the rxds1data_5 signal will internally be looped-back into the txds1data_5 path. further, the rxds1clock_5 clock signal will also be internally looped back into the rxds1clock_5 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 4 - loop-back activation - ds1 channel 4 this read/write bit-field permits the user to config- ure ds1 channel 4 into remote loop-back mode. when this loop-back is configured, then the rxds1data_4 signal will internally be looped-back into the txds1data_4 path. further, the rxds1clock_4 clock signal will also be internally looped back into the rxds1clock_4 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 3 - loop-back request - ds1 channel 7 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 7 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 7 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 2 - loop-back request - ds1 channel 6 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 6 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 6 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 1 - loop-back request - ds1 channel 5 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 5 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 5 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 0 - loop-back request - ds1 channel 4 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 4 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 4 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.40 m12 ds2 # 3 loopback request regis- ter ) bit 7 - loop-back activation - ds1 channel 11 this read/write bit-field permits the user to config- ure ds1 channel 11 into remote loop-back mode. m12 ds2 # 3 loop-back register (address = 0x2a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 loop-back activation ds1 channel 11 loop-back activation ds1 channel 10 loop-back activation ds1 channel 9 loop-back activation ds1 channel 8 loop-back request ds1 channel 11 loop-back request ds1 channel 10 loop-back request ds1 channel 9 loop-back request ds1 channel 8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 115 when this loop-back is configured, then the rxds1data_11 signal will internally be looped- back into the txds1data_11 path. further, the rxds1clock_11 clock signal will also be internally looped back into the rxds1clock_11 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 6 - loop-back activation - ds1 channel 10 this read/write bit-field permits the user to config- ure ds1 channel 10 into remote loop-back mode. when this loop-back is configured, then the rxds1data_10 signal will internally be looped- back into the txds1data_10 path. further, the rxds1clock_10 clock signal will also be internally looped back into the rxds1clock_10 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 5 - loop-back activation - ds1 channel 9 this read/write bit-field permits the user to config- ure ds1 channel 9 into remote loop-back mode. when this loop-back is configured, then the rxds1data_9 signal will internally be looped-back into the txds1data_9 path. further, the rxds1clock_9 clock signal will also be internally looped back into the rxds1clock_9 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 4 - loop-back activation - ds1 channel 8 this read/write bit-field permits the user to config- ure ds1 channel 8 into remote loop-back mode. when this loop-back is configured, then the rxds1data_8 signal will internally be looped-back into the txds1data_8 path. further, the rxds1clock_8 clock signal will also be internally looped back into the rxds1clock_8 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 3 - loop-back request - ds1 channel 11 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 11 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 11 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 2 - loop-back request - ds1 channel 10 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 10 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 10 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 1 - loop-back request - ds1 channel 9 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 9 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 9 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 0 - loop-back request - ds1 channel 8 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 8 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 8 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.41 m12 ds2 # 4 loop-back request regis- ter XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 116 ) bit 7 - loop-back activation - ds1 channel 15 this read/write bit-field permits the user to config- ure ds1 channel 15 into remote loop-back mode. when this loop-back is configured, then the rxds1data_15 signal will internally be looped- back into the txds1data_15 path. further, the rxds1clock_15 clock signal will also be internally looped back into the rxds1clock_15 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 6 - loop-back activation - ds1 channel 14 this read/write bit-field permits the user to config- ure ds1 channel 14 into remote loop-back mode. when this loop-back is configured, then the rxds1data_14 signal will internally be looped- back into the txds1data_14 path. further, the rxds1clock_14 clock signal will also be internally looped back into the rxds1clock_14 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 5 - loop-back activation - ds1 channel 13 this read/write bit-field permits the user to config- ure ds1 channel 13 into remote loop-back mode. when this loop-back is configured, then the rxds1data_13 signal will internally be looped- back into the txds1data_13 path. further, the rxds1clock_13 clock signal will also be internally looped back into the rxds1clock_13 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 4 - loop-back activation - ds1 channel 12 this read/write bit-field permits the user to config- ure ds1 channel 12 into remote loop-back mode. when this loop-back is configured, then the rxds1data_12 signal will internally be looped- back into the txds1data_12 path. further, the rxds1clock_12 clock signal will also be internally looped back into the rxds1clock_12 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 3 - loop-back request - ds1 channel 15 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 15 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 15 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 2 - loop-back request - ds1 channel 14 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 14 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 14 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 1 - loop-back request - ds1 channel 13 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 13 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 13 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 0 - loop-back request - ds1 channel 12 m12 ds2 # 4 loop-back register (address = 0x2b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 loop-back activation ds1 channel 15 loop-back activation ds1 channel 14 loop-back activation ds1 channel 13 loop-back activation ds1 channel 12 loop-back request ds1 channel 15 loop-back request ds1 channel 14 loop-back request ds1 channel 13 loop-back request ds1 channel 12 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 117 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 12 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 12 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.42 m12 ds2 # 5 loopback request regis- ter ) bit 7 - loop-back activation - ds1 channel 19 this read/write bit-field permits the user to config- ure ds1 channel 19 into remote loop-back mode. when this loop-back is configured, then the rxds1data_19 signal will internally be looped- back into the txds1data_19 path. further, the rxds1clock_19 clock signal will also be internally looped back into the rxds1clock_19 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 6 - loop-back activation - ds1 channel 18 this read/write bit-field permits the user to config- ure ds1 channel 18 into remote loop-back mode. when this loop-back is configured, then the rxds1data_18 signal will internally be looped- back into the txds1data_18 path. further, the rxds1clock_18 clock signal will also be internally looped back into the rxds1clock_18 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 5 - loop-back activation - ds1 channel 17 this read/write bit-field permits the user to config- ure ds1 channel 17 into remote loop-back mode. when this loop-back is configured, then the rxds1data_17 signal will internally be looped- back into the txds1data_17 path. further, the rxds1clock_17 clock signal will also be internally looped back into the rxds1clock_17 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 4 - loop-back activation - ds1 channel 16 this read/write bit-field permits the user to config- ure ds1 channel 16 into remote loop-back mode. when this loop-back is configured, then the rxds1data_16 signal will internally be looped- back into the txds1data_16 path. further, the rxds1clock_16 clock signal will also be internally looped back into the rxds1clock_16 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 3 - loop-back request - ds1 channel 19 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 19 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 19 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 2 - loop-back request - ds1 channel 18 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 18 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 18 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. m12 ds2 # 5 loop-back register (address = 0x2c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 loop-back activation ds1 channel 19 loop-back activation ds1 channel 18 loop-back activation ds1 channel 17 loop-back activation ds1 channel 16 loop-back request ds1 channel 19 loop-back request ds1 channel 18 loop-back request ds1 channel 17 loop-back request ds1 channel 16 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 118 bit 1 - loop-back request - ds1 channel 17 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 17 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 17 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 0 - loop-back request - ds1 channel 16 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 16 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 16 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.43 m12 ds2 # 6 loopback request regis- ter ) bit 7 - loop-back activation - ds1 channel 23 this read/write bit-field permits the user to config- ure ds1 channel 23 into remote loop-back mode. when this loop-back is configured, then the rxds1data_23 signal will internally be looped- back into the txds1data_23 path. further, the rxds1clock_23 clock signal will also be internally looped back into the rxds1clock_23 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 6 - loop-back activation - ds1 channel 22 this read/write bit-field permits the user to config- ure ds1 channel 22 into remote loop-back mode. when this loop-back is configured, then the rxds1data_22 signal will internally be looped- back into the txds1data_22 path. further, the rxds1clock_22 clock signal will also be internally looped back into the rxds1clock_22 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 5 - loop-back activation - ds1 channel 21 this read/write bit-field permits the user to config- ure ds1 channel 21 into remote loop-back mode. when this loop-back is configured, then the rxds1data_21 signal will internally be looped- back into the txds1data_21 path. further, the rxds1clock_21 clock signal will also be internally looped back into the rxds1clock_21 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 4 - loop-back activation - ds1 channel 20 this read/write bit-field permits the user to config- ure ds1 channel 20 into remote loop-back mode. when this loop-back is configured, then the rxds1data_20 signal will internally be looped- back into the txds1data_20 path. further, the rxds1clock_20 clock signal will also be internally looped back into the rxds1clock_20 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 3 - loop-back request - ds1 channel 23 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 23 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 23 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 2 - loop-back request - ds1 channel 22 m12 ds2 # 6 loop-back register (address = 0x2d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 loop-back activation ds1 channel 23 loop-back activation ds1 channel 22 loop-back activation ds1 channel 21 loop-back activation ds1 channel 20 loop-back request ds1 channel 23 loop-back request ds1 channel 22 loop-back request ds1 channel 21 loop-back request ds1 channel 20 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 119 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 22 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 22 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 1 - loop-back request - ds1 channel 21 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 21 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 21 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 0 - loop-back request - ds1 channel 20 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 20 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 20 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.44 m12 ds2 # 7 loopback request regis- ter ) bit 7 - loop-back activation - ds1 channel 27 this read/write bit-field permits the user to config- ure ds1 channel 27 into remote loop-back mode. when this loop-back is configured, then the rxds1data_27 signal will internally be looped- back into the txds1data_27 path. further, the rxds1clock_27 clock signal will also be internally looped back into the rxds1clock_27 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 6 - loop-back activation - ds1 channel 26 this read/write bit-field permits the user to config- ure ds1 channel 26 into remote loop-back mode. when this loop-back is configured, then the rxds1data_26 signal will internally be looped- back into the txds1data_26 path. further, the rxds1clock_26 clock signal will also be internally looped back into the rxds1clock_26 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 5 - loop-back activation - ds1 channel 25 this read/write bit-field permits the user to config- ure ds1 channel 25 into remote loop-back mode. when this loop-back is configured, then the rxds1data_25 signal will internally be looped- back into the txds1data_25 path. further, the rxds1clock_25 clock signal will also be internally looped back into the rxds1clock_25 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 4 - loop-back activation - ds1 channel 24 this read/write bit-field permits the user to config- ure ds1 channel 24 into remote loop-back mode. when this loop-back is configured, then the rxds1data_24 signal will internally be looped- back into the txds1data_24 path. further, the rxds1clock_24 clock signal will also be internally looped back into the rxds1clock_24 signal path. setting this bit-field to 1 enables this loop-back mode. conversely, setting this bit-field to 0 disables this loop-back mode. bit 3 - loop-back request - ds1 channel 27 m12 ds2 # 7 loop-back register (address = 0x28) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 loop-back activation ds1 channel 27 loop-back activation ds1 channel 26 loop-back activation ds1 channel 25 loop-back activation ds1 channel 24 loop-back request ds1 channel 27 loop-back request ds1 channel 26 loop-back request ds1 channel 25 loop-back request ds1 channel 24 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 120 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 27 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 27 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 2 - loop-back request - ds1 channel 26 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 26 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 26 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 1 - loop-back request - ds1 channel 25 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 25 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 25 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. bit 0 - loop-back request - ds1 channel 24 this read/write bit-field permits the user to config- ure the XRT72L13 to transmit a ds1 channel 24 - loop-back request signal to the remote terminal equipment. when the remote terminal equipment receives this request, it is expected to respond by configuring its own ds1 channel 24 signal into loop- back mode. n ote : this bit-field is ignored if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.45 tx ds3 configuration register ) bit 7 - tx yellow alarm this "read/write" bit-field allows the local p to com- mand the transmit ds3 framer to transmit a "yellow alarm" (e.g., x bits are all "0") in the outgoing ds3 data stream. writing a "0" to this bit-field disables this feature (the default condition). in this condition, the x-bits in the out-bound ds3 frame, are internally generated (based upon receiver conditions). writing a "1" to this bit-field invokes this command. in this condition, the transmit ds3 framer will override the internally-generated x-bits and force all of the x- bits of each outbound ds3 frame to "0". n ote : for more information in this feature, please see sec- tion _. n ote : this bit-setting is ignored if bits 3, 4 or 5 (within this register) are set to "1". bit 6 - tx x-bit (force x bits to "1") this "read/write" bit-field allows the user to com- mand the transmit ds3 framer to force all of the x- bits, in the outbound ds3 frames, to "1". writing a "0" to this bit-field disables this feature (the default condition). in this case, the transmit ds3 framer will generate x-bits based upon the receive conditions. writing a "1" to this bit-field invokes this command. in this case, the transmit ds3 framer will overwrite the internally-generated x-bits and set them all to "1". n ote : for more information on this feature, please see section _. n ote : this bit-setting is ignored if bits 3, 4, 5, or 7 (within this register) are set to "1". bit 5 - tx idle (pattern) this "read/write" bit-field allows the user to com- mand the transmit ds3 framer to transmit the "idle condition" pattern. if the user invokes this com- mand, then the transmit ds3 framer will force the outbound ds3 frames to have the following patterns. ? valid m-bits, f-bits and p-bits ? the three cp-bits (f-frame #3) are "0" ? the x-bits are set to "1" ? a repeating "1100..." pattern in written into the pay- load portion of the ds3 frames. tx ds3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx yellow alarm tx x bits tx idle tx ais tx los ferf on los ferf on oof ferf on ais r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 121 writing a "1" to this bit-field invokes this command. writing a "0" allows the transmit ds3 framer to func- tion normally (e.g., the transmit ds3 framer will transmit its payload and internally generated over- head bits). n ote : for more information on this feature, please see section _. n ote : this bit-setting is ignored if bits 3 or 4 (within this register) are set to "1". bit 4 - tx ais (pattern) this "read/write" bit-field allows the user to com- mand the transmit ds3 framer to transmit an "ais" pattern. if the user invokes this command, then the transmit ds3 framer will force the outbound ds3 frames to have the following patterns. ? valid m-bits, f-bits, and p-bits ? all c-bits are set to '0' ? all x-bits are set to '1' ? a repeating '1010...' pattern is written into the pay- load of the ds3 frames. writing a "1' to this bit-field invokes this command. writing a "0" allows the transmit ds3 framer to func- tion normally (e.g., the transmit ds3 framer will transmit its payload and internally generated over- head bits). n ote : for more information on this feature, please see section _. bit 3 - tx los (loss of signal) this "read/write" bit-field allows the user to com- mand the transmit ds3 framer to simulate an "los condition". if the user invokes this command, then the transmit ds3 framer will stop sending "mark" pulses out on the line; and will transmit an all-zero pattern. writing a '0' to this bit-field disables (or shuts off) this feature, thereby allowing internally generated ds3 frames to be generated and transmitted over the line. writing a '1' to this bit-field invokes this command, causing the transmit ds3 framing to generate an all '0' pattern. n ote : for more information on this feature, please see section _. bit 2 - ferf on los this "read/write" bit-field allows the user to config- ure the transmit ds3 framer to generate a "yellow alarm" if the near-end receive ds3 framer detects a "los" (loss of signal) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section _. bit 1 - ferf on oof this "read/write" bit-field allows the user to config- ure the transmit ds3 framer to generate a "yellow alarm" if the near-end receive ds3 framer detects an "oof (out-of-frame) condition". writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section _. bit 0 - ferf on ais this "read/write" bit-field allows the user to config- ure the transmit ds3 framer to generate a "yellow alarm" if the near-end receive ds3 framer detects an ais (alarm indication signal) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section _. 2.3.2.46 txds3 feac configuration and status register ) bit 4 - tx feac interrupt enable this read-write bit-field permits the user to enable or disable the transmit feac interrupt. setting this bit-field to 0 disables this interrupt. conversely, setting this bit-field to 1 enables this in- terrupt. bit 3 - txfeac interrupt status transmit ds3 configuration & status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used tx feac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w rur r/w r/w ro 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 122 this "read-only" bit-field indicates whether or not the "feac message transmission complete" interrupt has occurred since the last read of this register. this interrupt will occur once the transmit feac proces- sor has finished its 10th transmission of the 16 bit feac message (6 bit feac code word + 10 framing bits). the purpose of this interrupt is to let the local p know that the transmit feac processor has com- pleted its transmission of its latest feac message and is now ready to transmit another feac message. if this bit-field is "0", then the "feac message trans- mission complete" interrupt has not occurred since the last read of this register. if this bit-field is "1", then the "feac message trans- mission complete" interrupt has occurred since the last read of this register. n ote : for more information on the transmit feac proces- sor, please see section _. bit 2 - txfeac enable this "read/write" bit-field allows the user to enable or disable the transmit feac processor. the trans- mit feac processor will not function until it has been enabled. writing a "0" to this bit-field disables the transmit feac processor. writing a "1" to this bit-field en- ables the transmit feac processor. bit 1 - txfeac go this bit-field allows the user to invoke the "transmit feac message" command. once this command has been invoked, the transmit feac processor will do the following: ? encapsulate the 6 bit feac code word, from the tx ds3 feac register (address = 0x1d) into a 16 bit feac message ? serially transmit this 16-bit feac message to the far-end receiver via the "outbound" ds3 data- stream, 10 consecutive times. n ote : for more information on the transmit feac proces- sor, please see section _. bit 0 - txfeac busy this "read-only" bit-field allows the local p to "poll" and determine if the transmit feac processor has completed its 10th transmission of the 16-bit feac message. this bit-field will contain a "1", if the trans- mit feac processor is still transmitting the feac message. this bit-field will toggle to "0", once the transmit feac processor has completed its 10th transmission of the feac message. n ote : for more information on the transmit feac proces- sor, please see section _. 2.3.2.47 txds3 feac register ) this register contains a six (6) bit "read/write" field that allows the user to write in the six-bit feac code word, that he/she wishes to transmit to the "far end receive feac processor", via the outgoing ds3 data stream. the transmit feac processor will encapsu- late this six-bit code into a 16-bit feac message, and will proceed to transmit this message to the "far end receiver" via the feac bit-field within each out-going ds3 frame. n ote : for more information on the operation of the trans- mit feac processor, please see section _. 2.3.2.48 txds3 lapd configuration register ) bit 3 - auto retransmit this "read/write" bit-field allows the user to config- ure the lapd transmitter to either transmit the lapd tx ds3 feac regiser (address = 0x32) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txfeac[5:0] not used ro r/wr/wr/wr/wr/wr/w ro 01111110 txds3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable ro r/wr/wr/wr/wr/wr/wr/w 00001000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 123 message frame only once; or repeatedly at one-sec- ond intervals. writing a "0" to this bit-field configures the lapd transmitter to transmit the lapd message frame once. afterwards, the lapd transmitter will halt transmission, until it has commanded to transmit an- other lapd message frame. writing a "1" to this bit-field configures the lapd transmitter to transmit the lapd message frame re- peatedly at one second intervals. in this configura- tion, the lapd transmitter will repeat its transmission of the lapd message frame until it has been dis- abled. bit 1 - txlapd message length select this "read/write" bit-field permits the user to select the length of the "outbound" lapd message frame. setting this bit-field to "0" configures the "outbound" lapd message frame to be 76 bytes in length. set- ting this bit-field to "1" configures the "outbound" lapd message frame to be 82 bytes in length. bit 0 - txlapd enable this "read/write" bit-field allows the user to enable or disable the lapd transmitter. the lapd trans- mitter must be enabled before it can be commanded to transmit a lapd message frame (containing a pm- dl message) via the outbound ds3 frames, to the "far-end" terminal. writing a "0" disables the lapd transmitter (default condition). writing a "1" enables the lapd transmit- ter. n ote : for information on the lapd transmitter, please see section _. 2.3.2.49 txds3 lapd status/interrupt register) bit 3 - txdl start this "read/write" bit-field allows the user to invoke the "transmit lapd message" command. once the user invokes this command, the lapd transmitter will do the following: ? read in the pmdl message from the "transmit lapd message" buffer. ? encapsulate the pmdl message into a complete lapd message frame by including the necessary header and trailer bytes (e.g., flag sequence bytes, sapi, cr, ea values, etc.). ? compute the frame check sequence word (16 bit value) ? insert the frame check sequence value into the 2 octet slot after the payload section of the message. ? proceed to transmit the lapd message frame to the "far end" terminal via the outgoing ds3 frames. writing a "1" to this bit-field start the transmission of the lapd message frame, via the lapd transmitter. n ote : for more information on the lapd transmitter, please see section _. bit 2 - txdl busy this "read-only" bit-field allows the local p to "poll" and determine if the lapd transmitter has completed its transmission of the lapd message frame. this bit-field will contain a "1", if the lapd transmitter is still transmitting the lapd message frame to the "far- end" terminal. this bit-field will toggle to "0", once the lapd transmitter has completed its transmission of the lapd message frame. n ote : for more information on the lapd transmitter, please see section _. bit 1 - txlapd interrupt enable this "read/write" bit-field allows the user to enable or disable the "lapd message frame transmission complete" interrupt. writing a "0" to this bit-field disables this interrupt. writing a "1" to this bit-field enables this interrupt. bit 0 - txlapd interrupt status this "reset upon read" bit-field indicates whether or not the "lapd message frame transmission com- plete" interrupt has occurred since the last read of this register. the purpose of this interrupt is to let the local p know that the lapd transmitter has com- pleted its transmission of the lapd message frame (containing the latest pmdl message); and is now ready to transmit another lapd message frame. a "0" in this bit-field indicates that the "lapd mes- sage frame transmission complete" interrupt has not txds3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 124 occurred since the read of this register. a "1" in this bit-field indicates that this interrupt has occurred since the last read of this register. n ote : for more information on the lapd transmitter, please see section _. 2.3.2.50 txds3 m-bit mask register ) bit 7 - 5: txfebedat[2:0] these three (3) "read/write" bit-fields, along with bit 4 of this register, allows the user to configure and trans- mit his/her choice for febe bits in each outgoing ds3 frame. the user will write his/her value for the febe bits into these bit-fields. the transmit ds3 framer will insert these values into the febe bit-fields of each outgoing ds3 frame, once the user has written a "1" to bit 4 (febe register enable). n ote : for more information on this feature, please see section _. bit 4 - febe register enable this "read/write" bit-field allows the user to config- ure the transmit ds3 framer to insert the contents of txfebedat[2:0] into the febe bit-fields each outgo- ing ds3 frame. writing a "0" to this bit-field disables this feature (e.g., the transmit ds3 framer will transmit the internally generated febe bits). writing a "1" to this bit-field enables this features (e.g., the internally generated febe bits are overwritten by the contents of the txfebedat[2:0] bit-field). n ote : for more information on this feature, please see section _. bit 3 - transmit erred p-bit this "read/write bit-field allows the user to insert er- rors into the p-bits of the outgoing ds3 frames (via the transmit ds3 framer block). if the user enables this feature, then the transmit ds3 framer will pro- ceed to invert each and every p-bit, from its comput- ed value, prior to transmission to the "far-end" termi- nal. writing a "0" to this bit-field (the default condition) dis- ables this feature (e.g., the correct p-bits are sent). writing a "1" to this bit-field enables this feature (e.g., the incorrect p-bits are sent). n ote : for more information on this feature, please see section _. bit 2 - 0 m-bit mask[2:0] these "read/write" bit-fields allow the user to insert errors in the m-bits for test and diagnostic purposes. the transmit ds3 framer automatically performs an xor operation on the actual contents of the m-bit fields to these register bit-fields. therefore, for every '1' that exists in these bit-fields, will result in a change of state of the corresponding m-bit, prior to being transmitted to the far end receive ds3 framer. if the user wishes to operate the transmit ds3 fram- er in the normal mode (e.g., when no errors are being injected into the m-bit fields of the outbound ds3 frame), then he/she must ensure that these bit-fields are all '0'. 2.3.2.51 tx ds3 f-bit mask1 register ) bits 3 - 0 f-bit mask[27:24] these "read/write" bit-fields allow the user to insert errors into the first four f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3 framer block (within the chip) automatically performs an xor operation on the actual contents of these f- bit fields to these register bit-fields. therefore, for ev- ery "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to txds3 m-bit mask register (address = 0x35) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txfebedat[2:0] febe reg enable tx error p-bit mbit mask[2] mbit mask[1] mbit mask[0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 tx ds3 f-bit mask register - 1 (address = 0x36) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used fbit mask[27] fbit mask[26] fbit mask[25] fbit mask[24] ro ro ro ro r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 125 being transmitted to the far-end receive ds3 fram- er. if the user wishes to operate the transmit ds3 fram- er block in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then he/she must ensure that all of these bit-fields are "0s". 2.3.2.52 txds3 f-bit mask2 register ) bits 7 - 0 f-bit mask[23:16] these "read/write" bit-fields allow the user to insert errors into the fifth through twelfth f-bits of a ds3 m- frame, for test and diagnostic purposes. the trans- mit ds3 framer block automatically performs an xor operation on the actual contents of these f-bit fields to these register bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the remote receive ds3 fram- er.if the user wishes to operate the transmit ds3 framer block in the normal mode (e.g., when no er- rors are being injected into these f-bit fields of the outbound ds3 frames), then he/she must ensure that all of these bit-fields are "0s". 2.3.2.53 txds3 f-bit mask3 register ) bits 7 - 0 f-bit mask[15:8] these "read/write" bit-fields allow the user to insert errors into the thirteenth through twentieth f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3 framer automatically performs an xor operation on the actual contents of these f-bit fields to these register bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the far-end receive ds3 fram- er. if the user wishes to operate the transmit ds3 fram- er in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then he/she must ensure that all of these bit- fields are "0s". 2.3.2.54 txds3 f-bit mask4 register ) bits 7 - 0 f-bit mask[7:0] these "read/write" bit-fields allow the user to insert errors into the last eight f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3 framer automatically performs an xor operation on the actual contents of these f-bit fields to these regis- ter bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the far-end receive ds3 framer. if the user wishes to operate the transmit ds3 fram- er in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 txds3 f-bit mask register - 2 (address = 0x37) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[23] fbit mask[22] fbit mask[21] fbit mask[20] fbit mask[19] fbit mask[18] fbit mask[17] fbit mask[16] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 tx ds3 f-bit mask register - 3 (address = 0x38) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[15] fbit mask[14] fbit mask[13] fbit mask[12] fbit mask[11] fbit mask[10] fbit mask[9] fbit mask[8] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txds3 f-bit mask register - 4 (address = 0x39) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[7] fbit mask[6] fbit mask[5] fbit mask[4] fbit mask[3] fbit mask[2] fbit mask[1] fbit mask[0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 126 2.3.2.55 ds2 # 1 framer configuration register ) bit 6 - one and only bit 5 - ds2 msync - algo this read/write bit-field permits the user to define the m-bit sync declaration criteria for receive ds2 framer - channel 1. setting this bit-field to 0 configures the receive ds2 framer (for channel 1) to declare m-sync if it receives 4 consecutive, correct m-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 1) to declare m-sync if it re- ceives 8 consecutive, correct m-bits. bit 4 - ds2 fsync - algo this read/write bit-field permits the user to define the f-bit sync declaration criteria for receive ds2 framer - channel 1. setting this bit-field to 0 configures the receive ds2 framer (for channel 1) to declare f-sync if it re- ceives 8 consecutive, correct f-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 1) to declare f-sync if it re- ceives 16 consecutive, correct f-bits. bit 3 - ds2 foof - algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 1. setting this bit-field to 1 configures the receive ds2 framer (for channel 1) to declare an oof (out-of- frame) condition when 2 out of the last 5 received f- bits are errored. setting this bit-field to 0 configures the receive ds2 framer (for channel 1) to declare an oof (out-of- frame) condition when 2 out of the last 4 received f- bits are errored. bit 2 - ds2 moof algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 1. setting this bit-field to 1 configures the receive ds2 framer (for channel 1) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 3 out of the last 4 received ds2 frames. setting this bit-field to 0 configures the receive ds2 framer (for channel 1) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 2 out of the last 4 received ds2 frames. n ote : this bit-field is ignored if bit 1 (within this register is set to 1. bit 1 - ds2 moof disable this read/write bit-field permits the user to config- ure receive ds2 framer # 1 to evaluate m-bits as a part of the receive ds2 out-of frame declaration criteria. setting this bit-field to 0 configures receive ds2 framer # 1 to check for m-bit errors and declare an oof condition, per the settings within the ds2 moof algo bit-field (bit 2, within this register). setting this bit-field to 1 configures receive ds2 framer # 1 to not check for m-bits errors, as a part of the receive ds2 out-of frame declaration crite- ria. bit 0 - ds2 reframe this read/write bit-field permits the user to force (via software) receive ds2 framer # 1 to execute a re-frame procedure. a 0 to 1 transition, within this bit-field will cause receive ds2 framer # 1 to execute a re-frame op- eration. ds2 # 1 framer configuration register (address = 0x3a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused one and only ds2 msync algo ds2 fsync algo ds2 foof algo ds2 moof algo ds2 moof disable ds2 reframe] r/o r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 127 2.3.2.56 ds2 # 2 framer configuration regis- ter) bit 6 - one and only bit 5 - ds2 msync - algo this read/write bit-field permits the user to define the m-bit sync declaration criteria for receive ds2 framer - channel 2. setting this bit-field to 0 configures the receive ds2 framer (for channel 2) to declare m-sync if it receives 4 consecutive, correct m-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 2) to declare m-sync if it re- ceives 8 consecutive, correct m-bits. bit 4 - ds2 fsync - algo this read/write bit-field permits the user to define the f-bit sync declaration criteria for receive ds2 framer - channel 2. setting this bit-field to 0 configures the receive ds2 framer (for channel 2) to declare f-sync if it re- ceives 8 consecutive, correct f-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 2) to declare f-sync if it re- ceives 16 consecutive, correct f-bits. bit 3 - ds2 foof - algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 2. setting this bit-field to 1 configures the receive ds2 framer (for channel 2) to declare an oof (out-of- frame) condition when 2 out of the last 5 received f- bits are errored. setting this bit-field to 0 configures the receive ds2 framer (for channel 2) to declare an oof (out-of- frame) condition when 2 out of the last 4 received f- bits are errored. bit 2 - ds2 moof algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 2. setting this bit-field to 1 configures the receive ds2 framer (for channel 2) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 3 out of the last 4 received ds2 frames. setting this bit-field to 0 configures the receive ds2 framer (for channel 2) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 2 out of the last 4 received ds2 frames. n ote : this bit-field is ignored if bit 1 (within this register is set to 1. bit 1 - ds2 moof disable this read/write bit-field permits the user to config- ure receive ds2 framer # 2 to evaluate m-bits as a part of the receive ds2 out-of frame declaration criteria. setting this bit-field to 0 configures receive ds2 framer # 2 to check for m-bit errors and declare an oof condition, per the settings within the ds2 moof algo bit-field (bit 2, within this register). setting this bit-field to 1 configures receive ds2 framer # 2 to not check for m-bits errors, as a part of the receive ds2 out-of frame declaration crite- ria. bit 0 - ds2 reframe this read/write bit-field permits the user to force (via software) receive ds2 framer # 2 to execute a re-frame procedure. a 0 to 1 transition, within this bit-field will cause receive ds2 framer # 2 to execute a re-frame op- eration. ds2 # 2 framer configuration register (address = 0x3b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused one and only ds2 msync algo ds2 fsync algo ds2 foof algo ds2 moof algo ds2 moof disable ds2 reframe] r/o r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 128 2.3.2.57 ds2 # 3 framer configuration register ) bit 6 - one and only bit 5 - ds2 msync - algo this read/write bit-field permits the user to define the m-bit sync declaration criteria for receive ds2 framer - channel 3. setting this bit-field to 0 configures the receive ds2 framer (for channel 3) to declare m-sync if it receives 4 consecutive, correct m-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 3) to declare m-sync if it re- ceives 8 consecutive, correct m-bits. bit 4 - ds2 fsync - algo this read/write bit-field permits the user to define the f-bit sync declaration criteria for receive ds2 framer - channel 3. setting this bit-field to 0 configures the receive ds2 framer (for channel 3) to declare f-sync if it re- ceives 8 consecutive, correct f-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 3) to declare f-sync if it re- ceives 16 consecutive, correct f-bits. bit 3 - ds2 foof - algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 3. setting this bit-field to 1 configures the receive ds2 framer (for channel 3) to declare an oof (out-of- frame) condition when 2 out of the last 5 received f- bits are errored. setting this bit-field to 0 configures the receive ds2 framer (for channel 3) to declare an oof (out-of- frame) condition when 2 out of the last 4 received f- bits are errored. bit 2 - ds2 moof algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 3. setting this bit-field to 1 configures the receive ds2 framer (for channel 3) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 3 out of the last 4 received ds2 frames. setting this bit-field to 0 configures the receive ds2 framer (for channel 3) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 2 out of the last 4 received ds2 frames. n ote : this bit-field is ignored if bit 1 (within this register is set to 1. bit 1 - ds2 moof disable this read/write bit-field permits the user to config- ure receive ds2 framer # 3 to evaluate m-bits as a part of the receive ds2 out-of frame declaration criteria. setting this bit-field to 0 configures receive ds2 framer # 3 to check for m-bit errors and declare an oof condition, per the settings within the ds2 moof algo bit-field (bit 2, within this register). setting this bit-field to 1 configures receive ds2 framer # 3 to not check for m-bits errors, as a part of the receive ds2 out-of frame declaration crite- ria. bit 0 - ds2 reframe this read/write bit-field permits the user to force (via software) receive ds2 framer # 3 to execute a re-frame procedure. a 0 to 1 transition, within this bit-field will cause receive ds2 framer # 3 to execute a re-frame op- eration. ds2 # 3 framer configuration register (address = 0x3c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused one and only ds2 msync algo ds2 fsync algo ds2 foof algo ds2 moof algo ds2 moof disable ds2 reframe] r/o r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 129 2.3.2.58 ds2 # 4 framer configuration register ) bit 6 - one and only bit 5 - ds2 msync - algo this read/write bit-field permits the user to define the m-bit sync declaration criteria for receive ds2 framer - channel 4. setting this bit-field to 0 configures the receive ds2 framer (for channel 4) to declare m-sync if it receives 4 consecutive, correct m-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 4) to declare m-sync if it re- ceives 8 consecutive, correct m-bits. bit 4 - ds2 fsync - algo this read/write bit-field permits the user to define the f-bit sync declaration criteria for receive ds2 framer - channel 4. setting this bit-field to 0 configures the receive ds2 framer (for channel 4) to declare f-sync if it re- ceives 8 consecutive, correct f-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 4) to declare f-sync if it re- ceives 16 consecutive, correct f-bits. bit 3 - ds2 foof - algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 4. setting this bit-field to 1 configures the receive ds2 framer (for channel 4) to declare an oof (out-of- frame) condition when 2 out of the last 5 received f- bits are errored. setting this bit-field to 0 configures the receive ds2 framer (for channel 4) to declare an oof (out-of- frame) condition when 2 out of the last 4 received f- bits are errored. bit 2 - ds2 moof algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 4. setting this bit-field to 1 configures the receive ds2 framer (for channel 4) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 3 out of the last 4 received ds2 frames. setting this bit-field to 0 configures the receive ds2 framer (for channel 4) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 2 out of the last 4 received ds2 frames. n ote : this bit-field is ignored if bit 1 (within this register is set to 1. bit 1 - ds2 moof disable this read/write bit-field permits the user to config- ure receive ds2 framer # 4 to evaluate m-bits as a part of the receive ds2 out-of frame declaration criteria. setting this bit-field to 0 configures receive ds2 framer # 4 to check for m-bit errors and declare an oof condition, per the settings within the ds2 moof algo bit-field (bit 2, within this register). setting this bit-field to 1 configures receive ds2 framer # 4 to not check for m-bits errors, as a part of the receive ds2 out-of frame declaration crite- ria. bit 0 - ds2 reframe this read/write bit-field permits the user to force (via software) receive ds2 framer # 4 to execute a re-frame procedure. a 0 to 1 transition, within this bit-field will cause receive ds2 framer # 4 to execute a re-frame op- eration. ds2 # 4 framer configuration register (address = 0x3d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused one and only ds2 msync algo ds2 fsync algo ds2 foof algo ds2 moof algo ds2 moof disable ds2 reframe] r/o r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 130 2.3.2.59 ds2 # 5 framer configuration register ) bit 6 - one and only bit 5 - ds2 msync - algo this read/write bit-field permits the user to define the m-bit sync declaration criteria for receive ds2 framer - channel 5. setting this bit-field to 0 configures the receive ds2 framer (for channel 5) to declare m-sync if it receives 4 consecutive, correct m-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 5) to declare m-sync if it re- ceives 8 consecutive, correct m-bits. bit 4 - ds2 fsync - algo this read/write bit-field permits the user to define the f-bit sync declaration criteria for receive ds2 framer - channel 5. setting this bit-field to 0 configures the receive ds2 framer (for channel 5) to declare f-sync if it re- ceives 8 consecutive, correct f-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 5) to declare f-sync if it re- ceives 16 consecutive, correct f-bits. bit 3 - ds2 foof - algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 5. setting this bit-field to 1 configures the receive ds2 framer (for channel 5) to declare an oof (out-of- frame) condition when 2 out of the last 5 received f- bits are errored. setting this bit-field to 0 configures the receive ds2 framer (for channel 5) to declare an oof (out-of- frame) condition when 2 out of the last 4 received f- bits are errored. bit 2 - ds2 moof algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 5. setting this bit-field to 1 configures the receive ds2 framer (for channel 5) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 3 out of the last 4 received ds2 frames. setting this bit-field to 0 configures the receive ds2 framer (for channel 5) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 2 out of the last 4 received ds2 frames. n ote : this bit-field is ignored if bit 1 (within this register is set to 1. bit 1 - ds2 moof disable this read/write bit-field permits the user to config- ure receive ds2 framer # 5 to evaluate m-bits as a part of the receive ds2 out-of frame declaration criteria. setting this bit-field to 0 configures receive ds2 framer # 5 to check for m-bit errors and declare an oof condition, per the settings within the ds2 moof algo bit-field (bit 2, within this register). setting this bit-field to 1 configures receive ds2 framer # 5 to not check for m-bits errors, as a part of the receive ds2 out-of frame declaration crite- ria. bit 0 - ds2 reframe this read/write bit-field permits the user to force (via software) receive ds2 framer # 5 to execute a re-frame procedure. a 0 to 1 transition, within this bit-field will cause receive ds2 framer # 5 to execute a re-frame op- eration. ds2 # 5 framer configuration register (address = 0x3e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused one and only ds2 msync algo ds2 fsync algo ds2 foof algo ds2 moof algo ds2 moof disable ds2 reframe] r/o r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 131 2.3.2.60 ds2 # 6 framer configuration register ) bit 6 - one and only bit 5 - ds2 msync - algo this read/write bit-field permits the user to define the m-bit sync declaration criteria for receive ds2 framer - channel 6. setting this bit-field to 0 configures the receive ds2 framer (for channel 6) to declare m-sync if it receives 4 consecutive, correct m-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 6) to declare m-sync if it re- ceives 8 consecutive, correct m-bits. bit 4 - ds2 fsync - algo this read/write bit-field permits the user to define the f-bit sync declaration criteria for receive ds2 framer - channel 6. setting this bit-field to 0 configures the receive ds2 framer (for channel 6) to declare f-sync if it re- ceives 8 consecutive, correct f-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 6) to declare f-sync if it re- ceives 16 consecutive, correct f-bits. bit 3 - ds2 foof - algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 6. setting this bit-field to 1 configures the receive ds2 framer (for channel 6) to declare an oof (out-of- frame) condition when 2 out of the last 5 received f- bits are errored. setting this bit-field to 0 configures the receive ds2 framer (for channel 6) to declare an oof (out-of- frame) condition when 2 out of the last 4 received f- bits are errored. bit 2 - ds2 moof algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 6. setting this bit-field to 1 configures the receive ds2 framer (for channel 6) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 3 out of the last 4 received ds2 frames. setting this bit-field to 0 configures the receive ds2 framer (for channel 6) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 2 out of the last 4 received ds2 frames. n ote : this bit-field is ignored if bit 1 (within this register is set to 1. bit 1 - ds2 moof disable this read/write bit-field permits the user to config- ure receive ds2 framer # 6 to evaluate m-bits as a part of the receive ds2 out-of frame declaration criteria. setting this bit-field to 0 configures receive ds2 framer # 6 to check for m-bit errors and declare an oof condition, per the settings within the ds2 moof algo bit-field (bit 2, within this register). setting this bit-field to 1 configures receive ds2 framer # 6 to not check for m-bits errors, as a part of the receive ds2 out-of frame declaration crite- ria. bit 0 - ds2 reframe this read/write bit-field permits the user to force (via software) receive ds2 framer # 6 to execute a re-frame procedure. a 0 to 1 transition, within this bit-field will cause receive ds2 framer # 6 to execute a re-frame op- eration. ds2 # 6 framer configuration register (address = 0x3f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused one and only ds2 msync algo ds2 fsync algo ds2 foof algo ds2 moof algo ds2 moof disable ds2 reframe] r/o r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 132 2.3.2.61 ds2 # 7 framer configuration register ) bit 6 - one and only bit 5 - ds2 msync - algo this read/write bit-field permits the user to define the m-bit sync declaration criteria for receive ds2 framer - channel 7. setting this bit-field to 0 configures the receive ds2 framer (for channel 7) to declare m-sync if it receives 4 consecutive, correct m-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 7) to declare m-sync if it re- ceives 8 consecutive, correct m-bits. bit 4 - ds2 fsync - algo this read/write bit-field permits the user to define the f-bit sync declaration criteria for receive ds2 framer - channel 7. setting this bit-field to 0 configures the receive ds2 framer (for channel 7) to declare f-sync if it re- ceives 8 consecutive, correct f-bits. setting this bit-field to 1 configures the receive ds2 framer (for channel 7) to declare f-sync if it re- ceives 16 consecutive, correct f-bits. bit 3 - ds2 foof - algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 7. setting this bit-field to 1 configures the receive ds2 framer (for channel 7) to declare an oof (out-of- frame) condition when 2 out of the last 5 received f- bits are errored. setting this bit-field to 0 configures the receive ds2 framer (for channel 7) to declare an oof (out-of- frame) condition when 2 out of the last 4 received f- bits are errored. bit 2 - ds2 moof algo this read/write bit-field permits the user to define the receive ds2 out-of-frame declaration criteria, for ds2 channel 7. setting this bit-field to 1 configures the receive ds2 framer (for channel 7) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 3 out of the last 4 received ds2 frames. setting this bit-field to 0 configures the receive ds2 framer (for channel 7) to declare an oof (out-of- frame) condition when at least one m-bit error is de- tected within 2 out of the last 4 received ds2 frames. n ote : this bit-field is ignored if bit 1 (within this register is set to 1. bit 1 - ds2 moof disable this read/write bit-field permits the user to config- ure receive ds2 framer # 7 to evaluate m-bits as a part of the receive ds2 out-of frame declaration criteria. setting this bit-field to 0 configures receive ds2 framer # 7 to check for m-bit errors and declare an oof condition, per the settings within the ds2 moof algo bit-field (bit 2, within this register). setting this bit-field to 1 configures receive ds2 framer # 7 to not check for m-bits errors, as a part of the receive ds2 out-of frame declaration crite- ria. bit 0 - ds2 reframe this read/write bit-field permits the user to force (via software) receive ds2 framer # 7 to execute a re-frame procedure. a 0 to 1 transition, within this bit-field will cause receive ds2 framer # 7 to execute a re-frame op- eration. ds2 # 7 framer configuration register (address = 0x40) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused one and only ds2 msync algo ds2 fsync algo ds2 foof algo ds2 moof algo ds2 moof disable ds2 reframe] r/o r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 133 2.3.2.62 pmon lcv event count register - msb this "reset-upon-read" register, along with the "pmon lcv event count register - lsb" (address = 0x51) contains a 16-bit representation of the number of "line code violations" that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expres- sion. 2.3.2.63 pmon lcv event count register - lsb this "reset-upon-read" register, along with the "pmon lcv event count register - lsb" (address = 0x50) contains a 16-bit representation of the number of "line code violations" that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expres- sion. 2.3.2.64 pmon framing bit error event count register - msb this "reset-upon-read" register, along with the "pmon framing bit error count register - lsb" (ad- dress = 0x53) contains a 16-bit representation of the number of "framing bit errors" that have been de- tected by the receive ds3 framer block (within the chip), since the last read of these registers. this reg- ister contains the msb (or upper-byte) value of this 16 bit expression. 2.3.2.65 pmon framing bit error event count register - lsb this "reset-upon-read" register, along with the "pmon framing bit error count register - msb" (ad- dress = 0x52) contains a 16-bit representation of the number of "framing bit errors" that have been detect- pmon lcv event count register - msb (address = 0x50) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv count - high byte rur rur rur rur rur rur rur rur 00000000 pmon lcv event count register - lsb (address = 0x51) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv count - low byte rur rur rur rur rur rur rur rur 00000000 pmon framing bit error count register - msb (address = 0x52) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit error count - high byte rur rur rur rur rur rur rur rur 00000000 pmon framing bit error count register - lsb (address = 0x53) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit error count - low byte rur rur rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 134 ed by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. 2.3.2.66 pmon p-bit error event count regis- ter - msb this "reset-upon-read" register, along with the "pmon p-bit error count register - lsb" (address = 0x55) contains a 16-bit representation of the number of "p-bit errors that have been detected by the re- ceive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 2.3.2.67 pmon p-bit error event count regis- ter - lsb this "reset-upon-read" register, along with the "pmon p-bit error count register - msb" (address = 0x54) contains a 16-bit representation of the number of "p-bit errors that have been detected by the re- ceive ds3 framer block (within the chip), since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. 2.3.2.68 pmon febe event count register - msb this "reset-upon-read" register, along with the "pmon febe event count register - lsb" (address = 0x57) contains a 16-bit representation of the num- ber of "febe events that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 2.3.2.69 pmon febe event count register - lsb this "reset-upon-read" register, along with the "pmon febe event count register - msb" (address = 0x56) contains a 16-bit representation of the num- ber of "febe events that have been detected by the receive ds3 framer block (within the chip), since the pmon p-bit error count register - msb (address = 0x54) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 p-bit error count - high byte rurrurrurrurrurrurrurrur 00000000 pmon p-bit error count register - lsb (address = 0x55) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 p-bit error count - low byte rurrurrurrurrurrurrurrur 00000000 pmon febe event count register - msb (address = 0x56) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 febe event count - high byte rurrurrurrurrurrurrurrur 00000000 pmon febe event count register - lsb (address = 0x57) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 febe event count - low byte rurrurrurrurrurrurrurrur 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 135 last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. 2.3.2.70 pmon cp-bit error event count regis- ter - msb this "reset-upon-read" register, along with the "pmon cp-bit error count register - lsb" (address = 0x59) contains a 16-bit representation of the num- ber of "cp-bit errors that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 2.3.2.71 pmon cp-bit error event count regis- ter - lsb this "reset-upon-read" register, along with the "pmon cp-bit error count register - msb" (address = 0x58) contains a 16-bit representation of the num- ber of "cp-bit errors that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 2.3.2.72 pmon ds2 # 1 framing bit error count register this reset-upon read register contains an 8-bit representation of the number of f or m- bit errors that have been detected by receive ds2 framer # 1 (within the chip), since the last read of this register. 2.3.2.73 pmon ds2 # 2 framing bit error count register this reset-upon read register contains an 8-bit representation of the number of f or m- bit errors that have been detected by receive ds2 framer # 2 (within the chip), since the last read of this register. pmon cp-bit error count register - msb (address = 0x58) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error count - high byte rur rur rur rur rur rur rur rur 00000000 pmon cp-bit error count register - lsb (address = 0x59) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error count - low byte rur rur rur rur rur rur rur rur 00000000 pmon ds2 # 1 framing bit error count register (address = 0x5a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds2 # 1 framing-bit error count rur rur rur rur rur rur rur rur 00000000 pmon ds2 # 2 framing bit error count register (address = 0x5b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds2 # 2 framing-bit error count rur rur rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 136 2.3.2.74 pmon ds2 # 3 framing bit error count register this reset-upon read register contains an 8-bit representation of the number of f or m- bit errors that have been detected by receive ds2 framer # 3 (within the chip), since the last read of this register. 2.3.2.75 pmon ds2 # 4 framing bit error count register this reset-upon read register contains an 8-bit representation of the number of f or m- bit errors that have been detected by receive ds2 framer # 4 (within the chip), since the last read of this register. 2.3.2.76 pmon ds2 # 5 framing bit error count register this reset-upon read register contains an 8-bit representation of the number of f or m- bit errors that have been detected by receive ds2 framer # 5 (within the chip), since the last read of this register. 2.3.2.77 pmon ds2 # 6 framing bit error count register this reset-upon read register contains an 8-bit representation of the number of f or m- bit errors that have been detected by receive ds2 framer # 6 (within the chip), since the last read of this register. pmon ds2 # 3 framing bit error count register (address = 0x5c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds2 # 3 framing-bit error count rurrurrurrurrurrurrurrur 00000000 pmon ds2 # 4 framing bit error count register (address = 0x5d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds2 # 4 framing-bit error count rurrurrurrurrurrurrurrur 00000000 pmon ds2 # 5 framing bit error count register (address = 0x5e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds2 # 5 framing-bit error count rurrurrurrurrurrurrurrur 00000000 pmon ds2 # 6 framing bit error count register (address = 0x5f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds2 # 6 framing-bit error count rurrurrurrurrurrurrurrur 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 137 2.3.2.78 pmon ds2 # 7 framing bit error counter this reset-upon read register contains an 8-bit representation of the number of f or m- bit errors that have been detected by receive ds2 framer # 7 (within the chip), since the last read of this register. 2.3.2.79 pmon itu-t g.747 # 1 parity bit error count register this reset-upon-read register contains an 8-bit representation of the number of p bit errors that have been detected by receive g.747 framer # 1 (within the chip) since the last read of this register. n ote : this register is only applicable if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.80 pmon itu-t g.747 # 2 parity bit error count register this reset-upon-read register contains an 8-bit representation of the number of p bit errors that have been detected by receive g.747 framer # 2 (within the chip) since the last read of this register. n ote : this register is only applicable if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.81 pmon itu-t g.747 # 3 parity bit error count register this reset-upon-read register contains an 8-bit representation of the number of p bit errors that have been detected by receive g.747 framer # 3 (within the chip) since the last read of this register. n ote : this register is only applicable if the XRT72L13 has been configured to operate in the itu-t g.747 mode. pmon ds2 # 7 framing bit error count register (address = 0x60) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds2 # 7 framing-bit error count rur rur rur rur rur rur rur rur 00000000 pmon itu-t g.747 # 1 p- bit error count register (address = 0x61) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 itu-t g.747 # 1 p-bit error count rur rur rur rur rur rur rur rur 00000000 pmon itu-t g.747 # 2 p- bit error count register (address = 0x62) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 itu-t g.747 # 2 p-bit error count rur rur rur rur rur rur rur rur 00000000 pmon itu-t g.747 # 3 p- bit error count register (address = 0x63) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 itu-t g.747 # 3 p-bit error count rur rur rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 138 2.3.2.82 pmon itu-t g.747 # 4 parity bit error count register this reset-upon-read register contains an 8-bit representation of the number of p bit errors that have been detected by receive g.747 framer # 4 (within the chip) since the last read of this register. n ote : this register is only applicable if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.83 pmon itu-t g.747 # 5 parity bit error count register this reset-upon-read register contains an 8-bit representation of the number of p bit errors that have been detected by receive g.747 framer # 5 (within the chip) since the last read of this register. n ote : this register is only applicable if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.84 pmon itu-t g.747 # 6 parity bit error count register this reset-upon-read register contains an 8-bit representation of the number of p bit errors that have been detected by receive g.747 framer # 6 (within the chip) since the last read of this register. n ote : this register is only applicable if the XRT72L13 has been configured to operate in the itu-t g.747 mode. 2.3.2.85 pmon itu-t g.747 # 7 parity bit error count register this reset-upon-read register contains an 8-bit representation of the number of p bit errors that have been detected by receive g.747 framer # 7 (within the chip) since the last read of this register. n ote : this register is only applicable if the XRT72L13 has been configured to operate in the itu-t g.747 mode. pmon itu-t g.747 # 4 p- bit error count register (address = 0x64) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 itu-t g.747 # 4 p-bit error count rurrurrurrurrurrurrurrur 00000000 pmon itu-t g.747 # 5 p- bit error count register (address = 0x65) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 itu-t g.747 # 5 p-bit error count rurrurrurrurrurrurrurrur 00000000 pmon itu-t g.747 # 6 p- bit error count register (address = 0x66) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 itu-t g.747 # 6 p-bit error count rurrurrurrurrurrurrurrur 00000000 pmon itu-t g.747 # 7 p- bit error count register (address = 0x67) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 itu-t g.747 # 7 p-bit error count rurrurrurrurrurrurrurrur 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 139 2.3.2.86 pmon holding register each of the pmon registers are 16 bit "reset-upon- read" registers. more specifically, whenever the mi- croprocessor intends to read a pmon register, there are two things to bear in mind. 1. this microprocessor is going to require two read accesses in order read out the full 16-bit expres- sion of these pmon registers. 2. the entire 16-bit expression (of a given pmon register) is going to be reset, immediately after the microprocessor has completed its first read access to the pmon register. hence, the contents of the other byte (of the partially read pmon register) will reside within the pmon holding register. 2.3.2.87 one second error status register bit 1 - errored second this read-only bit-field indicates whether or not there was at least one error within the last one sec- ond accumulation period. if no error has occurred (within the last one second accumulation period) then this bit-field will be set to 0. conversely, if at least one error has occurred (within the last one second accumulation period) then this bit-field will be set to 1. bit 0 - severely errored second this read-only bit-field indicates whether or not the error-rate, in the last one second interval was greater than 1e-3. if the bit error rate (within the last one second accu- mulation period) is less than 1e-3, then this bit-field will be set to 0. conversely, if the bit-error rate (within the last one second accumulation period) is greater than 1e-3, then this bit-field will be set to 1. 2.3.2.88 lcv one second accumulator regis- ter - msb this "read-only" register, along with the "lcv - one second accumulator register - lsb" (address = 0x6f) contains a 16-bit representation of the number of "lcv (line code violation) events that have been detected by the receive ds3 framer block, within the last one-second sampling period. this register con- tains the msb (or upper-byte) value of this 16 bit ex- pression. pmon holding register (address = 0x6c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 pmon holding value rur rur rur rur rur rur rur rur 00000000 one second error status register (address = 0x6d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 errored second severely errored second ro ro ro ro ro ro ro ro 00000000 lcv - one second accumulator register - msb (address = 0x6e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv - one second count - high byte ro ro ro ro ro ro ro ro 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 140 2.3.2.89 lcv one second accumulator regis- ter - lsb this "read-only" register, along with the "lcv - one second accumulator register - msb" (address = 0x6e) contains a 16-bit representation of the number of "lcv (line code violation) events that have been detected by the receive ds3 framer block, within the last one second sampling period. this register con- tains the lsb (or lower-byte) value of this 16 bit ex- pression. 2.3.2.90 p-bit error one second accumulator register - msb this "read-only" register, along with the "frame par- ity errors - one second accumulator register - lsb" (address = 0x71) contains a 16-bit representation of the number of "p-bit errors that have been detected by the receive ds3 framer block, within the last one second sampling period. this register contains the msb (or upper-byte) value of this 16 bit expression. 2.3.2.91 p-bit error one second accumulator register - lsb this "read-only" register, along with the "frame par- ity errors - one second accumulator register - msb" (address = 0x70) contains a 16-bit representation of the number of "p-bit errors that have been detected by the receive ds3 framer block, within the last one- second sampling period. this register contains the lsb (or lower-byte) value of this 16 bit expression. 2.3.2.92 cp-bit error one second accumulator register - msb this read-only register, along with the frame cp- bit error - one second accumulator register - lsb (address = 0x73) contains a 16-bit representation of the number of cp bit errors tjhat have been detect- ed by the receive ds3 framer block, within the last one-second sampling period. this register contains the msb (or upper byte) value of this 16-bit expres- sion. lcv - one second accumulator register - lsb (address = 0x6f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv - one second count - low byte ro ro ro ro ro ro ro ro 00000000 p-bit errors - one second accumulator register - msb (address = 0x70) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 frame parity error count - high byte ro ro ro ro ro ro ro ro 00000000 p-bit errors - one second accumulator register - lsb (address = 0x71) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 frame parity error count - low byte ro ro ro ro ro ro ro ro 00000000 cp-bit errors - one second accumulator register - msb (address = 0x72) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error count - high byte ro ro ro ro ro ro ro ro 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 141 2.3.2.93 cp-bit error one second accumulator register - lsb this read-only register, along with the frame cp- bit error - one second accumulator register - msb (address = 0x72) contains a 16-bit representation of the number of cp bit errors tjhat have been detect- ed by the receive ds3 framer block, within the last one-second sampling period. this register contains the lsb (or lower byte) value of this 16-bit expres- sion. 2.3.2.94 line interface drive register bit 5 - reqb - (receive equalization bypass con- trol) this "read/write" bit-field allows the user to control the state of the reqb output pin of the XRT72L13. this output pin is intended to be connected to the reqb input pins of the xrt7300 ds3/e3 liu ic. if the user forces this signal to toggle "high", then the receive equalizer (within the xrt7300) will be dis- abled. conversely, if the user forces this signal to toggle "low", then the receive equalizer (within the xrt7300) will be enabled. writing a "1" to this bit-field causes the framer device to toggle the reqb output pin "high". writing a "0" to this bit-field causes the framer device to toggle the reqb output pin "low". for information on the criteria that should be used when deciding whether to bypass the equalization cir- cuitry or not, please consult the "xrt7300 ds3/e3/ sts-1 liu ic" data sheet. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then he/she can use this bit-field and the reqb output pin for other purposes. bit 4 - taos - (transmit all ones signal) this "read/write" bit-field allows the user to control the state of the taos output pin of the XRT72L13. this output pin is intended to be connected to the taos input pin of the xrt7300 ds3/e3/sts-1 liu ic. if the user forces this signal to toggle "high", then the xrt7300 liu device will transmit an "all ones" pattern onto the line. conversely, if the user com- mands this output signal to toggle "low" then the xrt7300 liu ic will proceed to transmit data based upon the pattern that it receives via the txpos and txneg output pins (of the framer ic). writing a "1" to this bit-field will cause the taos out- put pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then he/she can use this bit-field, and the taos output pin for other purposes. bit 3 - encodis - (b3zs encoder disable) this "read/write" bit-field allows the user to control the state of the encodis output pin of the XRT72L13 m13 device. this output pin is intended to be con- nected to the encodis input pin of the xrt7300 ds3/ e3/sts-1 liu ic. if the user forces this signal to tog- gle "high", then the "internal b3zs/hdb3 encoder" (within the xrt7300) will be disabled. conversely, if the user command this output signal to toggle "low", then the "internal b3zs/hdb3 encoder" (within the xrt7300) will be enabled. writing a "1" to this bit-field causes the framer ic to toggle the "encodis" output pin "high". writing a "0" to this bit-field will cause the framer ic to toggle this output pin "low". n otes : 1. the b3zs/hdb3 encoder, within the xrt7300, is not to be confused with the b3zs/hdb3 encoding capable that exists within the transmit section of the framer ic. cp-bit errors - one second accumulator register - lsb (address = 0x73) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error count - low byte ro ro ro ro ro ro ro ro 00000000 line interface drive register (address = 0x80) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reqb taos encodis txlev rloop lloop r/w r/w r/w r/w r/w r/w r/w r/w 00001000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 142 2. the user is advised to disabled the b3zs/hdb3 encoder (within the xrt7300 ic) if the XRT72L13 is configured to operate in the b3zs/hdb3 line code. 3. if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then he/she can use this bit-field and the "encodis" output pin for other purposes. 4. it is permissible to tie the "encodis" output pin of the xrt 72l13 ds3 framer ic to both the "enco- dis" and "decodis" input pins of the xrt7300. bit 2 - txlev - (transmit output line build-out select output) this "read/write" bit-field allows the user to control the state of the "txlev" output pin of the XRT72L13. this output pin is intended to be connected to the tx- lev input pin of the xrt7300 ds3/e3/sts-1 liu ic. if the user commands this signal to toggle "high", then the xrt7300 ds3/e3/sts-1 liu ic will disable the "transmit line build-out" circuitry, and will transmit unshaped (square-wave) pulses onto the line. if the user commands this signal to toggle "low", then the xrt7300 ds3/e3 liu ic will enable the "transmit line build-out" circuitry, and will transmit shaped pulses onto the line. in order to insure that the transmit output pulses of the xrt7300 meet the "dsx-3 isolated pulse tem- plate requirements (per bellcore gr-499-core), the user is advised to set this bit-field to "0", if the length of cable (between the xrt7300 transmit out- put and the dsx-3 cross connect system) is greater than 225 feet. conversely, the user is advised to set this bit-field to "1", if the length of cable (between the xrt7300 transmit output and the dsx-3 cross connect sys- tem) is less than 225 feet. writing a "1" to this bit-field commands the framer to toggle the txlev output "high". writing a "0" to this bit-field commands the framer to toggle this output signal "low". bit 1 - rloop - (remote loopback) this "read/write" bit-field allows the user to control the state of the rloop output pin of the XRT72L13 m13 device. this output pin is intended to be con- nected to the "rloop" input pin of the xrt7300 ds3/e3 liu ic. in the xrt7300 ds3/e3 liu ic, the state of the "rloop" and the "lloop" pins are used to dictate which loop-back mode the xrt7300 will operate in. the following table presents the relationship between the state of these two input pins (or bit-fields) and the resulting loop-back modes. writing a "1" into this bit-field commands the framer ic to toggle the "rloop" output signal "high". writ- ing a "0" into this bit-field commands the framer ic to toggle this output signal "low". for a detailed description of the xrt7300 ds3/e3 liu's operation, during each of these above-men- tioned loop-back modes, please consult the "xrt7300 ds3/e3/sts-1 liu ic" data sheet. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then he/she can use this bit-field and the "rloop" output pin for other purposes. bit 0 - lloop - (local loop-back) this "read/write" bit-field allows the user to control the state of the lloop output pin of the XRT72L13 m13 device. this output pin is intended to be con- nected to the lloop input pin of the xrt7300 ds3/ e3 liu ic. in the xrt7300 ds3/e3 liu ic, the state of the "rloop" and the "lloop" pins are used to dictate which loop-back mode the xrt7300 will operate in. the following table presents the relationship between the state of these two input pins (or bit-fields) and the resulting loop-back modes. rloop lloop r esulting l oop - back m ode of the xrt7300 00 normal operation (no loop-back mode) 01 analog local loop-back mode 10 remote loop-back mode 11 digital local loop-back mode rloop lloop r esulting l oop - back m ode of the xrt7300 00 normal operation (no loop-back mode) 01 analog local loop-back mode 10 remote loop-back mode ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 143 writing a "1" into this bit-field commands the XRT72L13 m13 device to toggle the "lloop" output signal "high". writing a "0" into this bit-field com- mands the XRT72L13 m13 device to toggle this out- put signal "low". for a detailed description of the xrt7300 ds3/e3 liu's operation, during each of these above-men- tioned loop-back modes, please consult the "xrt7300 ds3/e3/sts-1 liu ic" data sheet. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 liu ic, then he/she can use this bit-field and the "lloop" output pin for other purposes. 2.3.2.95 line interface scan register bit 2 - dmo - (drive monitor output) this "read-only" bit-field indicates the logic state of the dmo input pin of the XRT72L13 m13 device. this input pin is intended to be connected to the dmo output pin of the xrt7300 ds3/e3 liu ic. if this bit- field contains a logic "1", then the dmo input pin is "high". the xrt7300 ds3/e3 liu ic will set this pin "high" if the drive monitor circuitry (within the xrt7300) has not detected any bipolar signals at the mtip and mring inputs (of the xrt7300) within the last 128 + 32 bit periods. conversely, if this bit-field contains a logic "0", then the dmo input pin is "high". the xrt7300 ds3/e3 liu ic will set this pin "low" if bipolar signals are be- ing detected at the mtip and mring input pins. n ote : if this customer is not using the xrt7300 ds3/e3 liu ic, then he/she can use this input pin for a variety of other purposes. bit 1 - rlol - (receive loss of lock) this "read-only" bit-field indicates the logic state of the rlol input pin of the XRT72L13 m13 device. this input pin is intended to be connected to the rlol output pin of the xrt7300 ds3/e3 liu ic. if this bit-field contains a logic "1", then the rlol input pin is "high". the xrt7300 ds3/e3 liu ic will set this pin "high" if the clock recovery phase-locked-loop circuitry (within the xrt7300) has lost "lock" with the incoming ds3/e3 data-stream and is not properly re- covering clock and data. conversely, if this bit-field contains a logic "0", then the rlol input pin is "low". the xrt7300 ds3/e3 liu ic will hold this pin "low" as long as this "clock re- covery phase-locked-loop" circuitry (within the xrt7300) is properly "locked" onto the incoming ds3 data-stream, and is properly recovering clock and da- ta from this data-stream. for more information on the operation of the xrt7300 ds3/e3/sts-1 liu ic, please consult the "xrt7300 ds3/e3/sts-1 liu ic" data sheet. n ote : if the customer is not using the xrt7300 ds3/e3/ sts-1 ic, then he/she can use this bit-field, and the rlol input pin for other purposes. bit 0 - rlos - (receive loss of signal) this "read-only" bit-field indicates the logic state of the rlos input pin of the XRT72L13 m13 device. this input pin is intended to be connected to the rlos output pin of the xrt7300 ds3/e3 liu ic. if this bit-field contains a logic "1", then the rlos input pin is "high". the xrt7300 will toggle this signal "high" if it (the xrt7300 liu ic) is currently declaring an los (loss of signal) condition. conversely, if this bit-field contains a logic "0", then the rlos input pin is "low". the xrt7300 will hold this signal "low" if it is not currently declaring an los (loss of signal) condition. for more information on the los declaration and clearance criteria of the xrt7300, please consult the "xrt7300 ds3/e3/sts-1 liu ic" data sheet. n ote : asserting the rlos input pin will cause the xrt 72l13 ds3 framer ic to generate the "change in los condition" interrupt and declare an "los" (loss of signal) condition. therefore, this input pin should not be used as a general purpose input. 11 digital local loop-back mode rloop lloop r esulting l oop - back m ode of the xrt7300 line interface scan register (address = 0x81) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 dmo rlol rlos ro ro ro ro ro ro ro ro 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 144 2.3.2.96 m23 rxds2 loopback request inter- rupt enable register bit 6 - m23 # 7 loopback request interrupt enable this read/write bit-field permits the user to enable or disable the receive ds2 channel # 7 loop-back request interrupt. setting this bit-field to 1 enables this interrupt. set- ting this bit-field to 0 disables this interrupt. bit 5 - m23 # 6 loopback request interrupt enable this read/write bit-field permits the user to enable or disable the receive ds2 channel # 6 loop-back request interrupt. setting this bit-field to 1 enables this interrupt. set- ting this bit-field to 0 disables this interrupt. bit 4 - m23 # 5 loopback request interrupt enable this read/write bit-field permits the user to enable or disable the receive ds2 channel # 5 loop-back request interrupt. setting this bit-field to 1 enables this interrupt. set- ting this bit-field to 0 disables this interrupt. bit 3 - m23 # 4 loopback request interrupt enable this read/write bit-field permits the user to enable or disable the receive ds2 channel # 4 loop-back request interrupt. setting this bit-field to 1 enables this interrupt. set- ting this bit-field to 0 disables this interrupt. bit 2 - m23 # 3 loopback request interrupt enable this read/write bit-field permits the user to enable or disable the receive ds2 channel # 3 loop-back request interrupt. setting this bit-field to 1 enables this interrupt. set- ting this bit-field to 0 disables this interrupt. bit 1 - m23 # 2 loopback request interrupt enable this read/write bit-field permits the user to enable or disable the receive ds2 channel # 2 loop-back request interrupt. setting this bit-field to 1 enables this interrupt. set- ting this bit-field to 0 disables this interrupt. bit 0 - m23 # 1 loopback request interrupt enable this read/write bit-field permits the user to enable or disable the receive ds2 channel # 1 loop-back request interrupt. setting this bit-field to 1 enables this interrupt. set- ting this bit-field to 0 disables this interrupt. 2.3.2.97 m23 rxds2 loopback request inter- rupt register bit 6 - change in loop-back request interrupt status, m23 # 7. this reset-upon-read bit-field indicates whether or not there has been a change in the loop-back re- quest status for ds2 channel # 7. m23 rxds2 loop-back request interrupt enable register (address = 0x90) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused m23 # 7 loopback request interrupt enable m23 # 6 loopback request interrupt enable m23 # 5 loopback request interrupt enable m23 # 4 loopback request interrupt enable m23 # 3 loopback request interrupt enable m23 # 2 loopback request interrupt enable m23 # 1 loopback request interrupt enable ro r/wr/wr/wr/wr/wr/wr/w 00000000 m23 rxds2 change in loop-back request state - interrupt register (address = 0x91) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change in loop-back request inter- rupt status m23 # 7 change in loop-back request inter- rupt status m23 # 6 change in loop-back request inter- rupt status m23 # 5 change in loop-back request inter- rupt status m23 # 4 change in loop-back request inter- rupt status m23 # 3 change in loop-back request inter- rupt status m23 # 2 change in loop-back request inter- rupt status m23 # 1 ro rur rur rur rur rur rur rur 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 145 this bit-field will be set to 0 if there has been no change in the loop-back request status for ds2 channel # 7. conversely, this bit-field will set to 1 anytime there has been a change in the loop-back request status for ds2 channel # 7. n ote : this bit-field will be asserted in response to either of the following conditions. 1. the loop-back request status for ds2 chan- nel 7 has transitioned from the active to the inac- tive state. 2. the loop-back request status for ds2 channel 7 has transition from the inactive to the active state. bit 5 - change in loop-back request interrupt status, m23 # 6. this reset-upon-read bit-field indicates whether or not there has been a change in the loop-back re- quest status for ds2 channel # 6. this bit-field will be set to 0 if there has been no change in the loop-back request status for ds2 channel # 6. conversely, this bit-field will set to 1 anytime there has been a change in the loop-back request status for ds2 channel # 6. n ote : this bit-field will be asserted in response to either of the following conditions. 1. the loop-back request status for ds2 chan- nel 6 has transitioned from the active to the inac- tive state. 2. the loop-back request status for ds2 channel 6 has transition from the inactive to the active state. bit 4 - change in loop-back request interrupt status, m23 # 5. this reset-upon-read bit-field indicates whether or not there has been a change in the loop-back re- quest status for ds2 channel # 5. this bit-field will be set to 0 if there has been no change in the loop-back request status for ds2 channel # 5. conversely, this bit-field will set to 1 anytime there has been a change in the loop-back request status for ds2 channel # 5. n ote : this bit-field will be asserted in response to either of the following conditions. 1. the loop-back request status for ds2 chan- nel 5 has transitioned from the active to the inac- tive state. 2. the loop-back request status for ds2 channel 5 has transition from the inactive to the active state. bit 3 - change in loop-back request interrupt status, m23 # 4. this reset-upon-read bit-field indicates whether or not there has been a change in the loop-back re- quest status for ds2 channel # 4. this bit-field will be set to 0 if there has been no change in the loop-back request status for ds2 channel # 4. conversely, this bit-field will set to 1 anytime there has been a change in the loop-back request status for ds2 channel # 4. n ote : this bit-field will be asserted in response to either of the following conditions. 1. the loop-back request status for ds2 chan- nel 4 has transitioned from the active to the inac- tive state. 2. the loop-back request status for ds2 channel 4 has transition from the inactive to the active state. bit 2- change in loop-back request interrupt sta- tus, m23 # 3 this reset-upon-read bit-field indicates whether or not there has been a change in the loop-back re- quest status for ds2 channel # 3. this bit-field will be set to 0 if there has been no change in the loop-back request status for ds2 channel # 3. conversely, this bit-field will set to 1 anytime there has been a change in the loop-back request status for ds2 channel # 3. n ote : this bit-field will be asserted in response to either of the following conditions. 1. the loop-back request status for ds2 chan- nel 3 has transitioned from the active to the inac- tive state. 2. the loop-back request status for ds2 channel 3 has transition from the inactive to the active state. bit 1 - change in loop-back request interrupt status, m23 # 2 this reset-upon-read bit-field indicates whether or not there has been a change in the loop-back re- quest status for ds2 channel # 2. this bit-field will be set to 0 if there has been no change in the loop-back request status for ds2 channel # 2. conversely, this bit-field will set to 1 anytime there has been a change in the loop-back request status for ds2 channel # 2. n ote : this bit-field will be asserted in response to either of the following conditions. XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 146 1. the loop-back request status for ds2 chan- nel 2 has transitioned from the active to the inac- tive state. 2. the loop-back request status for ds2 channel 2 has transition from the inactive to the active state. bit 0 - change in loop-back request interrupt status, m23 # 1. this reset-upon-read bit-field indicates whether or not there has been a change in the loop-back re- quest status for ds2 channel # 1. this bit-field will be set to 0 if there has been no change in the loop-back request status for ds2 channel # 1. conversely, this bit-field will set to 1 anytime there has been a change in the loop-back request status for ds2 channel # 1. n ote : this bit-field will be asserted in response to either of the following conditions. 1. the loop-back request status for ds2 chan- nel 1 has transitioned from the active to the inac- tive state. 2. the loop-back request status for ds2 channel 1 has transition from the inactive to the active state. 2.3.2.98 m23 rxds2 loopback request status register. bit 6 - loop-back request status - m23 # 7 this read-only bit-field reflect the current loop- back request state of m23 # 7. this bit-field will be set to 1 if the loop-back re- quest for m23 # 7 is currently active. conversely, this bit-field will be set to 0 if the loop- back request for m23 # 7 is currently inactive. bit 5 - loop-back request status - m23 # 6 this read-only bit-field reflect the current loop- back request state of m23 # 6. this bit-field will be set to 1 if the loop-back re- quest for m23 # 6 is currently active. conversely, this bit-field will be set to 0 if the loop- back request for m23 # 6 is currently inactive. bit 4 - loop-back request status - m23 # 5 this read-only bit-field reflect the current loop- back request state of m23 # 5. this bit-field will be set to 1 if the loop-back re- quest for m23 # 5 is currently active. conversely, this bit-field will be set to 0 if the loop- back request for m23 # 5 is currently inactive. bit 3 - loop-back request status - m23 # 4 this read-only bit-field reflect the current loop- back request state of m23 # 4. this bit-field will be set to 1 if the loop-back re- quest for m23 # 4 is currently active. conversely, this bit-field will be set to 0 if the loop- back request for m23 # 4 is currently inactive. bit 2 - loop-back request status - m23 # 3 this read-only bit-field reflect the current loop- back request state of m23 # 3. this bit-field will be set to 1 if the loop-back re- quest for m23 # 3 is currently active. conversely, this bit-field will be set to 0 if the loop- back request for m23 # 3 is currently inactive. bit 1 - loop-back request status - m23 # 2 this read-only bit-field reflect the current loop- back request state of m23 # 2. this bit-field will be set to 1 if the loop-back re- quest for m23 # 2 is currently active. conversely, this bit-field will be set to 0 if the loop- back request for m23 # 2 is currently inactive. bit 0 - loop-back request status - m23 # 1 this read-only bit-field reflect the current loop- back request state of m23 # 1. this bit-field will be set to 1 if the loop-back re- quest for m23 # 1 is currently active. conversely, this bit-field will be set to 0 if the loop- back request for m23 # 1 is currently inactive. m23 rxds2 loop-back request status - interrupt register (address = 0x92) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused loop-back request status m23 # 7 loop-back request status m23 # 6 loop-back request status m23 # 5 loop-back request status m23 # 4 loop-back request status m23 # 3 loop-back request status m23 # 2 loop-back request status m23 # 1 ro ro ro ro ro ro ro ro 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 147 2.3.2.99 m12 ds2 # 1 loopback interrupt/inter- rupt enable register bit 7 - ds1 channel 3 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 3 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 3 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 3 loop-back request interrupt has not occurred since the last read of this register. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 6 - ds1 channel 2 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 2 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 2 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 2 loop-back request interrupt has not occurred since the last read of this register. bit 5 - ds1 channel 1 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 1 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 1 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 1 loop-back request interrupt has not occurred since the last read of this register. bit 4 - ds1 channel 0 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 0 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 0 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 0 loop-back request interrupt has not occurred since the last read of this register. bit 3 - ds1 channel 3 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 3 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 2 - ds1 channel 2 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 2 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 1 - ds1 channel 1 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 1 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. m12 ds2 # 1 loop-back interrupt/interrupt enable register (address = 0x93) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds1 channel 3 loop-back request interrupt status ds1 channel 2 loop-back request interrupt status ds1 channel 1 loop-back request interrupt status ds1 channel 0 loop-back request interrupt status ds1 channel 3 loop-back request interrupt enable ds1 channel 2 loop-back request interrupt enable ds1 channel 1 loop-back request interrupt enable ds1 channel 0 loop-back request interrupt enable rur rur rur rur r/w r/w r/w/ r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 148 bit 0 - ds1 channel 0 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 0 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. 2.3.2.100 m12 ds2 # 1 loopback status register bit 3 - ds1 channel # 3 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 3. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 3. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 3. n ote : this bit-field is invalid if the XRT72L13 m13 device is operating in the itu-t g.747 mode. bit 2 - ds1 channel # 2 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 2. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 2. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 2. bit 1 - ds1 channel # 1 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 1. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 1. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 1. bit 0 - ds1 channel # 0 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 0. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 0. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 0. 2.3.2.101 m12 ds2 # 2 loopback interrupt/inter- rupt enable register bit 7 - ds1 channel 7 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 7 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 7 loop-back request interrupt has occurred since the last read of this register. m12 ds2 # 1 loop-back status register (address = 0x94) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds1 channel # 3 loopback status ds1 channel # 2 loopback status ds1 channel # 1 loopback status ds1 channel # 0 loopback status r/o r/o r/o /ro r/o r/o r/o r/o 00000000 m12 ds2 # 2 loop-back interrupt/interrupt enable register (address = 0x95) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds1 channel 7 loop-back request interrupt status ds1 channel 6 loop-back request interrupt status ds1 channel 5 loop-back request interrupt status ds1 channel 4 loop-back request interrupt status ds1 channel 7 loop-back request interrupt enable ds1 channel 6 loop-back request interrupt enable ds1 channel 5 loop-back request interrupt enable ds1 channel 4 loop-back request interrupt enable rur rur rur rur r/w r/w r/w/ r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 149 this bit-field will be set to 0 if the ds1 channel 7 loop-back request interrupt has not occurred since the last read of this register. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 6 - ds1 channel 6 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 6 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 6 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 6 loop-back request interrupt has not occurred since the last read of this register. bit 5 - ds1 channel 5 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 5 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 5 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 5 loop-back request interrupt has not occurred since the last read of this register. bit 4 - ds1 channel 4 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 4 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 4 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 4 loop-back request interrupt has not occurred since the last read of this register. bit 3 - ds1 channel 7 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 7 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 2 - ds1 channel 6 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 6 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 1 - ds1 channel 5 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 5 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 0 - ds1 channel 4 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 4 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. 2.3.2.102 m12 ds2 # 2 loopback status register bit 3 - ds1 channel # 7 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 7. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 7. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 7. m12 ds2 # 1 loop-back status register (address = 0x96) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds1 channel # 7 loopback status ds1 channel # 6 loopback status ds1 channel # 5 loopback status ds1 channel # 4 loopback status r/o r/o r/o /ro r/o r/o r/o r/o 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 150 n ote : this bit-field is invalid if the XRT72L13 m13 device is operating in the itu-t g.747 mode. bit 2 - ds1 channel # 6 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 6. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 6. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 6. bit 1 - ds1 channel # 5 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 5. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 5. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 5. bit 0 - ds1 channel # 4 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 4. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 4. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 4. 2.3.2.103 m12 ds2 # 3 loopback interrupt/inter- rupt enable register bit 7 - ds1 channel 11 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 11 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 11 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 11 loop-back request interrupt has not occurred since the last read of this register. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 6 - ds1 channel 10 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 10 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 10 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 10 loop-back request interrupt has not occurred since the last read of this register. bit 5 - ds1 channel 9 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 9 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 9 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 9 loop-back request interrupt has not occurred since the last read of this register. bit 4 - ds1 channel 8 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 8 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 8 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 8 loop-back request interrupt has not occurred since the last read of this register. bit 3 - ds1 channel 11 loop-back request inter- rupt enable m12 ds2 # 3 loop-back interrupt/interrupt enable register (address = 0x97) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds1 channel 11 loop-back request interrupt status ds1 channel 10 loop-back request interrupt status ds1 channel 9 loop-back request interrupt status ds1 channel 8 loop-back request interrupt status ds1 channel 11 loop-backj request interrupt enable ds1 channel 10 loop-backj request interrupt enable ds1 channel 9 loop-backj request interrupt enable ds1 channel 8 loop-backj request interrupt enable rur rur rur rur r/w r/w r/w/ r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 151 this read/write bit-field permits the user to enable or disable the ds1 channel 11 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 2 - ds1 channel 10 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 10 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 1 - ds1 channel 9 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 9 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 0 - ds1 channel 8 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 8 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. 2.3.2.104 m12 ds2 # 3 loopback status register bit 3 - ds1 channel # 11 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 11. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 11. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 11. n ote : this bit-field is invalid if the XRT72L13 m13 device is operating in the itu-t g.747 mode. bit 2 - ds1 channel # 10 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 10. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 10. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 10. bit 1 - ds1 channel # 9 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 9. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 9. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 9. bit 0 - ds1 channel # 8 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 8. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 8. conversely, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 8. m12 ds2 # 1 loop-back status register (address = 0x98) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds1 channel # 11 loopback status ds1 channel # 10 loopback status ds1 channel # 9 loopback status ds1 channel # 8 loopback status r/o r/o r/o /ro r/o r/o r/o r/o 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 152 2.3.2.105 m12 ds2 # 4 loopback interrupt/inter- rupt enable register bit 7 - ds1 channel 15 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 15 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 15 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 15 loop-back request interrupt has not occurred since the last read of this register. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 6 - ds1 channel 14 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 14 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 14 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 14 loop-back request interrupt has not occurred since the last read of this register. bit 5 - ds1 channel 13 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 13 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 13 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 13 loop-back request interrupt has not occurred since the last read of this register. bit 4 - ds1 channel 12 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 12 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 12 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 12 loop-back request interrupt has not occurred since the last read of this register. bit 3 - ds1 channel 15 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 15 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 2 - ds1 channel 14 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 14 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 1 - ds1 channel 13 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 13 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 0 - ds1 channel 12 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 12 loop-back request interrupt. m12 ds2 # 4 loop-back interrupt/interrupt enable register (address = 0x99) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds1 channel 15 loop-back interrupt ds1 channel 14 loop-back interrupt ds1 channel 13 loop-back interrupt ds1 channel 12 loop-back interrupt ds1 channel 15 loop-backj interrupt enable ds1 channel 14 loop-backj interrupt enable ds1 channel 13 loop-backj interrupt enable ds1 channel 12 loop-backj interrupt enable rur rur rur rur r/w r/w r/w/ r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 153 setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. 2.3.2.106 m12 ds2 # 4 loopback status register bit 3 - ds1 channel # 15 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 15. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 15. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 15. n ote : this bit-field is invalid if the XRT72L13 m13 device is operating in the itu-t g.747 mode. bit 2 - ds1 channel # 14 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 14. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 14. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 14. bit 1 - ds1 channel # 13 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 13. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 13. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 13. bit 0 - ds1 channel # 12 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 12. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 12. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 12. 2.3.2.107 m12 ds2 # 5 loopback interrupt/inter- rupt enable register bit 7 - ds1 channel 19 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 19 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 19 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 19 loop-back request interrupt has not occurred since the last read of this register. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 6 - ds1 channel 18 loop-back request inter- rupt status m12 ds2 # 1 loop-back status register (address = 0x9a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds1 channel # 15 loopback status ds1 channel # 14 loopback status ds1 channel # 13 loopback status ds1 channel # 12 loopback status r/o r/o r/o /ro r/o r/o r/o r/o 00000000 m12 ds2 # 5 loop-back interrupt/interrupt enable register (address = 0x9b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds1 channel 19 loop-back request interrupt status ds1 channel 18 loop-back request interrupt status ds1 channel 17 loop-back request interrupt status ds1 channel 16 loop-back request interrupt status ds1 channel 19 loop-backj request interrupt enable ds1 channel 18 loop-backj request interrupt enable ds1 channel 17 loop-backj request interrupt enable ds1 channel 16 loop-backj request interrupt enable rur rur rur rur r/w r/w r/w/ r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 154 this reset-upon-read bit-field indicates whether the ds1 channel 18 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 18 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 18 loop-back request interrupt has not occurred since the last read of this register. bit 5 - ds1 channel 17 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 17 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 17 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 17 loop-back request interrupt has not occurred since the last read of this register. bit 4 - ds1 channel 16 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 16 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 16 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 16 loop-back request interrupt has not occurred since the last read of this register. bit 3 - ds1 channel 19 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 19 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 2 - ds1 channel 18 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 18 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 1 - ds1 channel 17 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 17 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 0 - ds1 channel 16 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 16 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. 2.3.2.108 m12 ds2 # 5 loopbackstatus register bit 3 - ds1 channel # 19 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 19. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 19. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 19. n ote : this bit-field is invalid if the XRT72L13 m13 device is operating in the itu-t g.747 mode. bit 2 - ds1 channel # 18 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 18. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 18. converse- m12 ds2 # 1 loop-back status register (address = 0x9c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds1 channel # 19 loopback status ds1 channel # 18 loopback status ds1 channel # 17 loopback status ds1 channel # 16 loopback status r/o r/o r/o /ro r/o r/o r/o r/o 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 155 ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 18. bit 1 - ds1 channel # 17 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 17. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 17. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 17. bit 0 - ds1 channel # 16 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 16. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 16. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 16. 2.3.2.109 m12 ds2 # 6 loopback interrupt/inter- rupt enable register bit 7 - ds1 channel 23 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 23 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 23 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 23 loop-back request interrupt has not occurred since the last read of this register. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 6 - ds1 channel 22 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 22 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 22 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 22 loop-back request interrupt has not occurred since the last read of this register. bit 5 - ds1 channel 21 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 21 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 21 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 21 loop-back request interrupt has not occurred since the last read of this register. bit 4 - ds1 channel 20 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 20 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 20 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 20 loop-back request interrupt has not occurred since the last read of this register. bit 3 - ds1 channel 23 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 23 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. m12 ds2 # 6 loop-back interrupt/interrupt enable register (address = 0x9d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds1 channel 23 loop-back request interrupt status ds1 channel 22 loop-back request interrupt status ds1 channel 21 loop-back request interrupt status ds1 channel 20 loop-back request interrupt status ds1 channel 23 loop-backj request interrupt enable ds1 channel 22 loop-backj request interrupt enable ds1 channel 21 loop-backj request interrupt enable ds1 channel 20 loop-backj request interrupt enable rur rur rur rur r/w r/w r/w/ r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 156 bit 2 - ds1 channel 22 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 22 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 1 - ds1 channel 21 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 21 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 0 - ds1 channel 20 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 20 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. 2.3.2.110 m12 ds2 # 6 loopback status register bit 3 - ds1 channel # 24 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 24. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 24. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 24. n ote : this bit-field is invalid if the XRT72L13 m13 device is operating in the itu-t g.747 mode. bit 2 - ds1 channel # 23 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 23. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 23. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 23. bit 1 - ds1 channel # 22 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 22. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 22. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 22. bit 0 - ds1 channel # 21 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 21. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 21. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 21. m12 ds2 # 1 loop-back status register (address = 0x9e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds1 channel # 24 loopback status ds1 channel # 23 loopback status ds1 channel # 22 loopback status ds1 channel # 21 loopback status r/o r/o r/o /ro r/o r/o r/o r/o 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 157 2.3.2.111 m12 ds2 # 7 loopback interrupt/inter- rupt enable register bit 7 - ds1 channel 27 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 27 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 27 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 27 loop-back request interrupt has not occurred since the last read of this register. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 6 - ds1 channel 26 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 26 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 26 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 26 loop-back request interrupt has not occurred since the last read of this register. bit 5 - ds1 channel 25 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 25 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 25 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 25 loop-back request interrupt has not occurred since the last read of this register. bit 4 - ds1 channel 24 loop-back request inter- rupt status this reset-upon-read bit-field indicates whether the ds1 channel 24 loop-back request interrupt has occurred or not. this bit-field will be set to 1 if the ds1 channel 24 loop-back request interrupt has occurred since the last read of this register. this bit-field will be set to 0 if the ds1 channel 24 loop-back request interrupt has not occurred since the last read of this register. bit 3 - ds1 channel 27 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 27 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. n ote : this bit-field is ignored if the XRT72L13 is config- ured to operate in the itu-t g.747 mode. bit 2 - ds1 channel 26 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 26 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. bit 1 - ds1 channel 25 loop-back request inter- rupt enable this read/write bit-field permits the user to enable or disable the ds1 channel 25 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. m12 ds2 # 7 loop-back interrupt/interrupt enable register (address = 0x9f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 ds1 channel 27 loop-back request interrupt status ds1 channel 26 loop-back request interrupt status ds1 channel 25 loop-back request interrupt status ds1 channel 24 loop-back request interrupt status ds1 channel 27 loop-backj request interrupt enable ds1 channel 26 loop-backj request interrupt enable ds1 channel 25 loop-backj request interrupt enable ds1 channel 24 loop-backj request interrupt enable rur rur rur rur r/w r/w r/w/ r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 158 bit 0 - ds1 channel 24 loop-back interrupt en- able this read/write bit-field permits the user to enable or disable the ds1 channel 24 loop-back request interrupt. setting this bit to 0 disables this interrupt. con- versely, setting this bit to 1 enables this interrupt. 2.3.2.112 m12 ds2 # 7 loopback status register bit 3 - ds1 channel # 27 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 27. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 27. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 27. n ote : this bit-field is invalid if the XRT72L13 m13 device is operating in the itu-t g.747 mode. bit 2 - ds1 channel # 26 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 26. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 26. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 26. bit 1 - ds1 channel # 25 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 25. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 25. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 25. bit 0 - ds1 channel # 24 loop-back status this read-only bit-field indicates whether or not a loop-back request has been detected for ds1 chan- nel # 24. this bit-field will be set to 1 if a loop-back request has been detected for ds1 channel # 24. converse- ly, this bit-field will be set to 0 if a loop-back request has not been detected for ds1 channel # 24. 2.3.2.113 ds2 # 1 framer interrupt enable regis- ter bit 5 - ds2 cofa (change of framing alignment) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 change of framing alignment interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 4 - ds2 oof (out of frame) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 out of frame interrupt. m12 ds2 # 1 loop-back status register (address = 0xa0) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds1 channel # 27 loopback status ds1 channel # 26 loopback status ds1 channel # 25 loopback status ds1 channel # 24 loopback status r/o r/o r/o /ro r/o r/o r/o r/o 00000000 ds2 # 1 framer interrupt enable register (address = 0xa1) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa interrupt enable ds2 oof interrupt enable ds2 ferf interrupt enable ds2 red alarm interrupt enable ds2 ais interrupt enable ds2 resv interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 159 setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 3 - ds2 ferf (far-end-receive failure) inter- rupt enable. this read/write bit-field permits the user to enable or disable the ds2 far-end receive failure inter- rupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 2 - ds2 red alarm interrupt enable this read/write bit-field permits the user to enable or disable the ds2 red alarm interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 1 - ds2 ais interrupt enable this read/write bit-field permits the user to enable or disable the ds2 ais interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 0 - ds2 resv interrupt enable. to be provided in the next update. 2.3.2.114 ds2 # 1 framer interrupt register bit 5 - change in ds2 cofa (change of framing alignment) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 cofa state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 cofa state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 cofa state has not occurred since the last read of this register. bit 4 - change in ds2 oof (out-of-frame) inter- rupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 out-of-frame state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 oof state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 oof state has not occurred since the last read of this register. bit 3 - change in ds2 ferf (far-end receive fail- ure) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ferf state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ferf state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 ferf state has not occurred since the last read of this register. bit 2 - change in ds2 red alarm interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 red alarm state has oc- curred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 red alarm state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 red alarm state has not oc- curred since the last read of this register. bit 1 - change in ds2 ais interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ais state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ais state has occurred since the last read of this reg- ister. conversely, this bit-field will be set to 0 if a change in the ds2 ais state has not occurred since the last read of this register. bit 0 - change in ds2 resv interrupt status ds2 # 1 framer interrupt register (address = 0xa2) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change in ds2 cofa interrupt status change in ds2 oof interrupt status change in ds2 ferf interrupt status change in ds2 red alarm interrupt status change in ds2 ais interrupt status change in ds2 resv interrupt status r/o r/o rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 160 to be provided in the next update. 2.3.2.115 ds2 # 1 framer status register bit 5 - ds2 cofa (change of framing alignment) status this read-only bit-field reflects the current cofa status of ds2 channel # 1. this bit-field will be set to 0 is there is no change of framing alignment in ds2 channel # 1. converse- ly, this bit-field will be set to 1 is there is a change of framing alignment in ds2 channel # 1. bit 4 - ds2 oof (out-of-frame) status this read-only bit-field reflects the current oof status of ds2 channel # 1. this bit-field will be set to 0 if ds2 channel # 1 is currently in the in-frame condition. conversely, this bit-field will be set to 1 if ds2 channel # 1 is currently declaring an out-of-frame condtion. bit 3 - ds2 ferf (far-end receive failure) status his read-only bit-field reflects the current ferf status of ds2 channel # 1. this bit-field will be set to 0 if ds2 channel # 1 is currently not declaring the ferf condition. con- versely, this bit-field will be set to 1 if ds2 channel # 1 is currently declaring a ferf condtion. bit 2 - ds2 red alarm status this read-only bit-field reflects the current red alarm status of ds2 channel # 1. this bit-field will be set to 0 if ds2 channel # 1 is not currently declaring a red alarm condition. conversely, this bit-field will be set to 1 if ds2 chan- nel # 1 is currently declaring a red alarm condition. bit 1 - ds2 ais (alarm indication signal) status this read-only bit-field reflects the current ais status of ds2 channel # 1. this bit-field will be set to 0 if ds2 channel # 1 is not currently declaring an ais condition. converse- ly, this bit-field will be set to 1 if ds2 channel # 1 is currently declaring an ais condition. bit 0 - ds2 resv status to be provided in the next update. 2.3.2.116 ds2 # 2 framer interrupt enable regis- ter bit 5 - ds2 cofa (change of framing alignment) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 change of framing alignment interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 4 - ds2 oof (out of frame) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 out of frame interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 3 - ds2 ferf (far-end-receive failure) inter- rupt enable. ds2 # 1 framer status register (address = 0xa3) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ds2 # 2 framer interrupt enable register (address = 0xa4) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa interrupt enable ds2 oof interrupt enable ds2 ferf interrupt enable ds2 red alarm interrupt enable ds2 ais interrupt enable ds2 resv interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 161 this read/write bit-field permits the user to enable or disable the ds2 far-end receive failure inter- rupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 2 - ds2 red alarm interrupt enable this read/write bit-field permits the user to enable or disable the ds2 red alarm interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 1 - ds2 ais interrupt enable this read/write bit-field permits the user to enable or disable the ds2 ais interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 0 - ds2 resv interrupt enable. to be provided in the next update. 2.3.2.117 ds2 # 2 framer interrupt register bit 5 - change in ds2 cofa (change of framing alignment) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 cofa state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 cofa state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 cofa state has not occurred since the last read of this register. bit 4 - change in ds2 oof (out-of-frame) inter- rupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 out-of-frame state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 oof state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 oof state has not occurred since the last read of this register. bit 3 - change in ds2 ferf (far-end receive fail- ure) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ferf state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ferf state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 ferf state has not occurred since the last read of this register. bit 2 - change in ds2 red alarm interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 red alarm state has oc- curred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 red alarm state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 red alarm state has not oc- curred since the last read of this register. bit 1 - change in ds2 ais interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ais state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ais state has occurred since the last read of this reg- ister. conversely, this bit-field will be set to 0 if a change in the ds2 ais state has not occurred since the last read of this register. bit 0 - change in ds2 resv interrupt status to be provided in the next update. ds2 # 2 framer interrupt register (address = 0xa5) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change in ds2 cofa interrupt enable change in ds2 oof interrupt enable change in ds2 ferf interrupt enable change in ds2 red alarm interrupt enable change in ds2 ais interrupt enable change in ds2 resv interrupt enable r/o r/o rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 162 2.3.2.118 ds2 # 2 framer status register bit 5 - ds2 cofa (change of framing alignment) status this read-only bit-field reflects the current cofa status of ds2 channel # 2. this bit-field will be set to 0 is there is no change of framing alignment in ds2 channel # 2. converse- ly, this bit-field will be set to 1 is there is a change of framing alignment in ds2 channel # 2. bit 4 - ds2 oof (out-of-frame) status this read-only bit-field reflects the current oof status of ds2 channel # 2. this bit-field will be set to 0 if ds2 channel # 2 is currently in the in-frame condition. conversely, this bit-field will be set to 1 if ds2 channel # 2 is currently declaring an out-of-frame condtion. bit 3 - ds2 ferf (far-end receive failure) status his read-only bit-field reflects the current ferf status of ds2 channel # 2. this bit-field will be set to 0 if ds2 channel # 2 is currently not declaring the ferf condition. con- versely, this bit-field will be set to 1 if ds2 channel # 2 is currently declaring a ferf condtion. bit 2 - ds2 red alarm status this read-only bit-field reflects the current red alarm status of ds2 channel # 2. this bit-field will be set to 0 if ds2 channel # 2 is not currently declaring a red alarm condition. conversely, this bit-field will be set to 1 if ds2 chan- nel # 1 is currently declaring a red alarm condition. bit 1 - ds2 ais (alarm indication signal) status this read-only bit-field reflects the current ais status of ds2 channel # 2. this bit-field will be set to 0 if ds2 channel # 2 is not currently declaring an ais condition. converse- ly, this bit-field will be set to 1 if ds2 channel # 2 is currently declaring an ais condition. bit 0 - ds2 resv status to be provided in the next update. 2.3.2.119 ds2 # 3 framer interrupt enable regis- ter bit 5 - ds2 cofa (change of framing alignment) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 change of framing alignment interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 4 - ds2 oof (out of frame) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 out of frame interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 3 - ds2 ferf (far-end-receive failure) inter- rupt enable. ds2 # 2 framer status register (address = 0xa6) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ds2 # 3 framer interrupt enable register (address = 0xa7) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa interrupt enable ds2 oof interrupt enable ds2 ferf interrupt enable ds2 red alarm interrupt enable ds2 ais interrupt enable ds2 resv interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 163 this read/write bit-field permits the user to enable or disable the ds2 far-end receive failure inter- rupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 2 - ds2 red alarm interrupt enable this read/write bit-field permits the user to enable or disable the ds2 red alarm interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 1 - ds2 ais interrupt enable this read/write bit-field permits the user to enable or disable the ds2 ais interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 0 - ds2 resv interrupt enable. to be provided in the next update. 2.3.2.120 ds2 # 3 framer interrupt register bit 5 - change in ds2 cofa (change of framing alignment) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 cofa state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 cofa state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 cofa state has not occurred since the last read of this register. bit 4 - change in ds2 oof (out-of-frame) inter- rupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 out-of-frame state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 oof state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 oof state has not occurred since the last read of this register. bit 3 - change in ds2 ferf (far-end receive fail- ure) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ferf state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ferf state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 ferf state has not occurred since the last read of this register. bit 2 - change in ds2 red alarm interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 red alarm state has oc- curred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 red alarm state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 red alarm state has not oc- curred since the last read of this register. bit 1 - change in ds2 ais interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ais state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ais state has occurred since the last read of this reg- ister. conversely, this bit-field will be set to 0 if a change in the ds2 ais state has not occurred since the last read of this register. bit 0 - change in ds2 resv interrupt status to be provided in the next update. ds2 # 3 framer interrupt register (address = 0xa8) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change in ds2 cofa interrupt enable change in ds2 oof interrupt enable change in ds2 ferf interrupt enable change in ds2 red alarm interrupt enable change in ds2 ais interrupt enable change in ds2 resv interrupt enable r/o r/o rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 164 2.3.2.121 ds2 # 3 framer status register bit 5 - ds2 cofa (change of framing alignment) status this read-only bit-field reflects the current cofa status of ds2 channel # 3. this bit-field will be set to 0 is there is no change of framing alignment in ds2 channel # 3. converse- ly, this bit-field will be set to 1 is there is a change of framing alignment in ds2 channel # 3. bit 4 - ds2 oof (out-of-frame) status this read-only bit-field reflects the current oof status of ds2 channel # 3. this bit-field will be set to 0 if ds2 channel # 3 is currently in the in-frame condition. conversely, this bit-field will be set to 1 if ds2 channel # 3 is currently declaring an out-of-frame condtion. bit 3 - ds2 ferf (far-end receive failure) status his read-only bit-field reflects the current ferf status of ds2 channel # 3. this bit-field will be set to 0 if ds2 channel # 3 is currently not declaring the ferf condition. con- versely, this bit-field will be set to 1 if ds2 channel # 1 is currently declaring a ferf condtion. bit 2 - ds2 red alarm status this read-only bit-field reflects the current red alarm status of ds2 channel # 3. this bit-field will be set to 0 if ds2 channel # 3 is not currently declaring a red alarm condition. conversely, this bit-field will be set to 1 if ds2 chan- nel # 3 is currently declaring a red alarm condition. bit 1 - ds2 ais (alarm indication signal) status this read-only bit-field reflects the current ais status of ds2 channel # 3. this bit-field will be set to 0 if ds2 channel # 3 is not currently declaring an ais condition. converse- ly, this bit-field will be set to 1 if ds2 channel # 3 is currently declaring an ais condition. bit 0 - ds2 resv status to be provided in the next update. 2.3.2.122 ds2 # 4 framer interrupt enable regis- ter bit 5 - ds2 cofa (change of framing alignment) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 change of framing alignment interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 4 - ds2 oof (out of frame) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 out of frame interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 3 - ds2 ferf (far-end-receive failure) inter- rupt enable. ds2 # 3 framer status register (address = 0xa9) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ds2 # 4 framer interrupt enable register (address = 0xaa) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa interrupt enable ds2 oof interrupt enable ds2 ferf interrupt enable ds2 red alarm interrupt enable ds2 ais interrupt enable ds2 resv interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 165 this read/write bit-field permits the user to enable or disable the ds2 far-end receive failure inter- rupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 2 - ds2 red alarm interrupt enable this read/write bit-field permits the user to enable or disable the ds2 red alarm interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 1 - ds2 ais interrupt enable this read/write bit-field permits the user to enable or disable the ds2 ais interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 0 - ds2 resv interrupt enable. to be provided in the next update. 2.3.2.123 ds2 # 4 framer interrupt register bit 5 - change in ds2 cofa (change of framing alignment) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 cofa state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 cofa state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 cofa state has not occurred since the last read of this register. bit 4 - change in ds2 oof (out-of-frame) inter- rupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 out-of-frame state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 oof state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 oof state has not occurred since the last read of this register. bit 3 - change in ds2 ferf (far-end receive fail- ure) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ferf state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ferf state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 ferf state has not occurred since the last read of this register. bit 2 - change in ds2 red alarm interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 red alarm state has oc- curred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 red alarm state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 red alarm state has not oc- curred since the last read of this register. bit 1 - change in ds2 ais interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ais state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ais state has occurred since the last read of this reg- ister. conversely, this bit-field will be set to 0 if a change in the ds2 ais state has not occurred since the last read of this register. bit 0 - change in ds2 resv interrupt status to be provided in the next update. ds2 # 4 framer interrupt enable register (address = 0xab) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change in ds2 cofa interrupt enable change in ds2 oof interrupt enable change in ds2 ferf interrupt enable change in ds2 red alarm interrupt enable change in ds2 ais interrupt enable change in ds2 resv interrupt enable r/o r/o rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 166 2.3.2.124 ds2 # 4 framer status register bit 5 - ds2 cofa (change of framing alignment) status this read-only bit-field reflects the current cofa status of ds2 channel # 4. this bit-field will be set to 0 is there is no change of framing alignment in ds2 channel # 4. converse- ly, this bit-field will be set to 1 is there is a change of framing alignment in ds2 channel # 4. bit 4 - ds2 oof (out-of-frame) status this read-only bit-field reflects the current oof status of ds2 channel # 4. this bit-field will be set to 0 if ds2 channel # 4 is currently in the in-frame condition. conversely, this bit-field will be set to 1 if ds2 channel # 4 is currently declaring an out-of-frame condtion. bit 3 - ds2 ferf (far-end receive failure) status his read-only bit-field reflects the current ferf status of ds2 channel # 4. this bit-field will be set to 0 if ds2 channel # 4 is currently not declaring the ferf condition. con- versely, this bit-field will be set to 1 if ds2 channel # 4 is currently declaring a ferf condtion. bit 2 - ds2 red alarm status this read-only bit-field reflects the current red alarm status of ds2 channel # 4. this bit-field will be set to 0 if ds2 channel # 4 is not currently declaring a red alarm condition. conversely, this bit-field will be set to 1 if ds2 chan- nel # 4 is currently declaring a red alarm condition. bit 1 - ds2 ais (alarm indication signal) status this read-only bit-field reflects the current ais status of ds2 channel # 4. this bit-field will be set to 0 if ds2 channel # 4 is not currently declaring an ais condition. converse- ly, this bit-field will be set to 1 if ds2 channel # 4 is currently declaring an ais condition. bit 0 - ds2 resv status to be provided in the next update. 2.3.2.125 ds2 # 5 framer interrupt enable regis- ter bit 5 - ds2 cofa (change of framing alignment) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 change of framing alignment interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 4 - ds2 oof (out of frame) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 out of frame interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 3 - ds2 ferf (far-end-receive failure) inter- rupt enable. ds2 # 4 framer status register (address = 0xac) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ds2 # 5 framer interrupt enable register (address = 0xad) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa interrupt enable ds2 oof interrupt enable ds2 ferf interrupt enable ds2 red alarm interrupt enable ds2 ais interrupt enable ds2 resv interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 167 this read/write bit-field permits the user to enable or disable the ds2 far-end receive failure inter- rupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 2 - ds2 red alarm interrupt enable this read/write bit-field permits the user to enable or disable the ds2 red alarm interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 1 - ds2 ais interrupt enable this read/write bit-field permits the user to enable or disable the ds2 ais interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 0 - ds2 resv interrupt enable. to be provided in the next update. 2.3.2.126 ds2 # 5 framer interrupt register bit 5 - change in ds2 cofa (change of framing alignment) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 cofa state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 cofa state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 cofa state has not occurred since the last read of this register. bit 4 - change in ds2 oof (out-of-frame) inter- rupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 out-of-frame state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 oof state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 oof state has not occurred since the last read of this register. bit 3 - change in ds2 ferf (far-end receive fail- ure) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ferf state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ferf state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 ferf state has not occurred since the last read of this register. bit 2 - change in ds2 red alarm interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 red alarm state has oc- curred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 red alarm state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 red alarm state has not oc- curred since the last read of this register. bit 1 - change in ds2 ais interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ais state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ais state has occurred since the last read of this reg- ister. conversely, this bit-field will be set to 0 if a change in the ds2 ais state has not occurred since the last read of this register. bit 0 - change in ds2 resv interrupt status to be provided in the next update. ds2 # 5 framer interrupt enable register (address = 0xaf) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change in ds2 cofa interrupt enable change in ds2 oof interrupt enable change in ds2 ferf interrupt enable change in ds2 red alarm interrupt enable change in ds2 ais interrupt enable change in ds2 resv interrupt enable r/o r/o rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 168 2.3.2.127 ds2 # 5 framer status register bit 5 - ds2 cofa (change of framing alignment) status this read-only bit-field reflects the current cofa status of ds2 channel # 5. this bit-field will be set to 0 is there is no change of framing alignment in ds2 channel # 5. converse- ly, this bit-field will be set to 1 is there is a change of framing alignment in ds2 channel # 5. bit 4 - ds2 oof (out-of-frame) status this read-only bit-field reflects the current oof status of ds2 channel # 5. this bit-field will be set to 0 if ds2 channel # 5 is currently in the in-frame condition. conversely, this bit-field will be set to 1 if ds2 channel # 5 is currently declaring an out-of-frame condtion. bit 3 - ds2 ferf (far-end receive failure) status his read-only bit-field reflects the current ferf status of ds2 channel # 5. this bit-field will be set to 0 if ds2 channel # 5 is currently not declaring the ferf condition. con- versely, this bit-field will be set to 1 if ds2 channel # 5 is currently declaring a ferf condtion. bit 2 - ds2 red alarm status this read-only bit-field reflects the current red alarm status of ds2 channel # 5. this bit-field will be set to 0 if ds2 channel # 5 is not currently declaring a red alarm condition. conversely, this bit-field will be set to 1 if ds2 chan- nel # 5 is currently declaring a red alarm condition. bit 1 - ds2 ais (alarm indication signal) status this read-only bit-field reflects the current ais status of ds2 channel # 5. this bit-field will be set to 0 if ds2 channel # 5 is not currently declaring an ais condition. converse- ly, this bit-field will be set to 1 if ds2 channel # 5 is currently declaring an ais condition. bit 0 - ds2 resv status to be provided in the next update. 2.3.2.128 ds2 # 6 framer interrupt enable regis- ter bit 5 - ds2 cofa (change of framing alignment) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 change of framing alignment interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 4 - ds2 oof (out of frame) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 out of frame interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 3 - ds2 ferf (far-end-receive failure) inter- rupt enable. ds2 # 5 framer status register (address = 0xaf) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ds2 # 6 framer interrupt enable register (address = 0xb0) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa interrupt enable ds2 oof interrupt enable ds2 ferf interrupt enable ds2 red alarm interrupt enable ds2 ais interrupt enable ds2 resv interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 169 this read/write bit-field permits the user to enable or disable the ds2 far-end receive failure inter- rupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 2 - ds2 red alarm interrupt enable this read/write bit-field permits the user to enable or disable the ds2 red alarm interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 1 - ds2 ais interrupt enable this read/write bit-field permits the user to enable or disable the ds2 ais interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 0 - ds2 resv interrupt enable. to be provided in the next update. 2.3.2.129 ds2 # 6 framer interrupt register bit 5 - change in ds2 cofa (change of framing alignment) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 cofa state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 cofa state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 cofa state has not occurred since the last read of this register. bit 4 - change in ds2 oof (out-of-frame) inter- rupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 out-of-frame state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 oof state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 oof state has not occurred since the last read of this register. bit 3 - change in ds2 ferf (far-end receive fail- ure) interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ferf state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ferf state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 ferf state has not occurred since the last read of this register. bit 2 - change in ds2 red alarm interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 red alarm state has oc- curred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 red alarm state has occurred since the last read of this register. conversely, this bit-field will be set to 0 if a change in the ds2 red alarm state has not oc- curred since the last read of this register. bit 1 - change in ds2 ais interrupt status this reset-upon-read bit-field indicates whether or not a change in the ds2 ais state has occurred since the last read of this register. this bit-field will be set to 1 if a change in the ds2 ais state has occurred since the last read of this reg- ister. conversely, this bit-field will be set to 0 if a change in the ds2 ais state has not occurred since the last read of this register. bit 0 - change in ds2 resv interrupt status to be provided in the next update. 2.3.2.130 ds2 # 6 framer status register ds2 # 6 framer interrupt register (address = 0xb2) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change in ds2 cofa interrupt enable change in ds2 oof interrupt enable change in ds2 ferf interrupt enable change in ds2 red alarm interrupt enable change in ds2 ais interrupt enable change in ds2 resv interrupt enable r/o r/o rur rur rur rur rur rur 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 170 bit 5 - ds2 cofa (change of framing alignment) status this read-only bit-field reflects the current cofa status of ds2 channel # 6. this bit-field will be set to 0 is there is no change of framing alignment in ds2 channel # 6. converse- ly, this bit-field will be set to 1 is there is a change of framing alignment in ds2 channel # 6. bit 4 - ds2 oof (out-of-frame) status this read-only bit-field reflects the current oof status of ds2 channel # 6. this bit-field will be set to 0 if ds2 channel # 6 is currently in the in-frame condition. conversely, this bit-field will be set to 1 if ds2 channel # 6 is currently declaring an out-of-frame condtion. bit 3 - ds2 ferf (far-end receive failure) status his read-only bit-field reflects the current ferf status of ds2 channel # 6. this bit-field will be set to 0 if ds2 channel # 6 is currently not declaring the ferf condition. con- versely, this bit-field will be set to 1 if ds2 channel # 1 is currently declaring a ferf condtion. bit 2 - ds2 red alarm status this read-only bit-field reflects the current red alarm status of ds2 channel # 6. this bit-field will be set to 0 if ds2 channel # 6 is not currently declaring a red alarm condition. conversely, this bit-field will be set to 1 if ds2 chan- nel # 6 is currently declaring a red alarm condition. bit 1 - ds2 ais (alarm indication signal) status this read-only bit-field reflects the current ais status of ds2 channel # 6. this bit-field will be set to 0 if ds2 channel # 6 is not currently declaring an ais condition. converse- ly, this bit-field will be set to 1 if ds2 channel # 6 is currently declaring an ais condition. bit 0 - ds2 resv status to be provided in the next update. 2.3.2.131 ds2 # 7 framer interrupt enable regis- ter bit 5 - ds2 cofa (change of framing alignment) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 change of framing alignment interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 4 - ds2 oof (out of frame) interrupt enable this read/write bit-field permits the user to enable or disable the ds2 out of frame interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 3 - ds2 ferf (far-end-receive failure) inter- rupt enable. ds2 # 6 framer status register (address = 0xb2) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ds2 # 7 framer interrupt enable register (address = 0xb3) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa interrupt enable ds2 oof interrupt enable ds2 ferf interrupt enable ds2 red alarm interrupt enable ds2 ais interrupt enable ds2 resv interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic XRT72L13 preliminary rev. 1.0.6 171 this read/write bit-field permits the user to enable or disable the ds2 far-end receive failure inter- rupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 2 - ds2 red alarm interrupt enable this read/write bit-field permits the user to enable or disable the ds2 red alarm interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 1 - ds2 ais interrupt enable this read/write bit-field permits the user to enable or disable the ds2 ais interrupt. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. bit 0 - ds2 resv interrupt enable. to be provided in the next update. 2.3.2.132 ds2 # 7 framer interrupt register 2.3.2.133 ds2 # 7 framer status register bit 5 - ds2 cofa (change of framing alignment) status this read-only bit-field reflects the current cofa status of ds2 channel # 7. this bit-field will be set to 0 is there is no change of framing alignment in ds2 channel # 7. converse- ly, this bit-field will be set to 1 is there is a change of framing alignment in ds2 channel # 7. bit 4 - ds2 oof (out-of-frame) status this read-only bit-field reflects the current oof status of ds2 channel # 7. this bit-field will be set to 0 if ds2 channel # 7 is currently in the in-frame condition. conversely, this bit-field will be set to 1 if ds2 channel # 7 is currently declaring an out-of-frame condtion. bit 3 - ds2 ferf (far-end receive failure) status his read-only bit-field reflects the current ferf status of ds2 channel # 7. this bit-field will be set to 0 if ds2 channel # 7 is currently not declaring the ferf condition. con- versely, this bit-field will be set to 1 if ds2 channel # 1 is currently declaring a ferf condtion. bit 2 - ds2 red alarm status this read-only bit-field reflects the current red alarm status of ds2 channel # 7. this bit-field will be set to 0 if ds2 channel # 7 is not currently declaring a red alarm condition. conversely, this bit-field will be set to 1 if ds2 chan- nel # 7 is currently declaring a red alarm condition. bit 1 - ds2 ais (alarm indication signal) status this read-only bit-field reflects the current ais status of ds2 channel # 1. ds2 # 7 framer interrupt register (address = 0xb5) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change in ds2 cofa interrupt enable change in ds2 oof interrupt enable change in ds2 ferf interrupt enable change in ds2 red alarm interrupt enable change in ds2 ais interrupt enable change in ds2 resv interrupt enable r/o r/o rur rur rur rur rur rur 00000000 ds2 # 7 framer status register (address = 0xb5) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 multiplexer/framer ic ? ? ? ? preliminary rev. 1.0.6 172 this bit-field will be set to 0 if ds2 channel # 7 is not currently declaring an ais condition. converse- ly, this bit-field will be set to 1 if ds2 channel # 7 is currently declaring an ais condition. bit 0 - ds2 resv status to be provided in the next update. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 173 3.0 the microprocessor interface block the microprocessor interface section supports com- munication between the "local" microprocessor (p) and the framer ic. in particular, the microprocessor interface section supports the following operations between the local microprocessor and the framer. ? the writing of configuration data into the framer on-chip (addressable) registers. ? the writing of an "outbound" pmdl path mainte- nance data link) message into the "transmit lapd message" buffer (within the framer ic). ? the framer ic's generation of an interrupt request to the p. ? the p's servicing of the interrupt request from the framer ic. ? the monitoring of the system's "health" by periodi- cally reading the on-chip performance monitor reg- isters. ? the reading of an "inbound" pmdl message from the "receive lapd" message buffer (within the framer ic). each of these operations (between the local micro- processor and the framer ic) will be discussed in some detail, throughout this data sheet. figure 46 presents a simple block diagram of the mi- croprosser interface block. 3.1 t he m icroprocessor i nterface b lock s ig - nal the framer ic may be configured into a wide variety of different operating modes and have its perfor- mance monitored by software through a standard (lo- cal "housekeeping") microprocessor, using data, ad- dress and control signals. the local p configures the framer ic (into a desired operating mode) by writing data into specific address- able, on-chip "read/write" registers; or on-chip ram. the microprocessor interface provides the signals which are required for a general purpose micropro- cessor to read or write data into these registers. the microprocessor interface also supports "polled" and interrupt driven environments. these interface sig- nals are described below in tables 1, 2, and 3. the microprocessor interface can be configured to oper- ate in the "motorola" mode or in the "intel" mode. when the microprocessor interface is operating in the "motorola" mode, then some of the control signals function in a manner as required by the motorola 68000 family of microprocessors. likewise, when the microprocessor interface is operating in the "intel" mode, then some of these control signals function in a manner as required by the intel 80xx family of mi- croprocessors. table 6 lists and describes those microprocessor in- terface signals whose role is constant across the two modes. table 7 describes the role of some of these signals when the microprocessor interface is operat- ing in the intel mode. likewise, table 8 describes the role of these signals when the microprocessor inter- face is operating in the motorola mode. f igure 46. s imple b lock d iagram of the m icroprocessor i nterface b lock , within the f ramer ic a[8:0] wrb_rw rdb_ds csb* ale_as reset intb* d[7:0] moto rdy_dtck microprocessor interface and programmable registers XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 174 t able 6: d escription of the m icroprocessor i nterface s ignals that exhibit constant roles in both the "i ntel " and "m otorola " m odes p in n ame t ype d escription moto i selection input for intel/motorola p interface. setting this pin to a logic "high" configures the microprocessor interface to operate in the "motor- ola" mode. likewise, setting this pin to a logic "low" configures the microprocessor interface to operate in the "intel" mode. d[7:0] i/o bi-directional data bus for register read or write operations a[8:0] i nine bit address bus input: this nine bit address bus is provided to allow the user to select an on-chip register or on-chip ram location. cs i chip select input. this "active low" signal selects the microprocessor interface of the uni device and enables read/write operations with the on-chip registers/on-chip ram. int o interrupt request output: this "open-drain/active-low" output signal will inform the local p that the uni has an interrupt condition that needs servicing. t able 7: p in d escription of m icroprocessor i nterface s ignals - w hile the m icroprocessor i nterface is o perating in the i ntel m ode p in n ame e quivalent p in in i ntel environment t ype d escription ale_as ale i address-latch enable: this "active-high" signal is used to latch the contents on the address bus, a[8:0]. the contents of the address bus are latched into the a[8:0] inputs on the falling edge of ale_as. additionally, this signal can be used to indicate the start of a burst cycle. rd _ds rd i read signal: this "active-low" input functions as the read signal from the local p . when this signal goes "low", the uni microprocessor interface will place the contents of the addressed register on the data bus pins (d[15:0]). the data bus will be "tri-stated" once this input signal returns "high". wr _rw wr i write signal: this "active-low" input functions as the write signal from the local p . the contents of the data bus (d[15:0]) will be written into the addressed reg- ister (via a[8:0]), on the rising edge of this signal. rdy_dtck ready o ready output: this "active-low" signal is provided by the uni device, and indi- cates that the current read or write cycle is to be extended until this signal is asserted. the local p will typically insert "wait" states until this signal is asserted. this output will toggle "low" when the device is ready for the next read or write cycle. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 175 3.2 i nterfacing the XRT72L13 ds3 f ramer to the l ocal c/p over via the m icroproces - sor i nterface b lock the microprocessor interface block, within the fram- er is very flexible and provides the following options to the user. ? to interface the framer to a c/p over an 8-bit wide bi-directional data bus. ? to interface the framer to an intel-type or motorola- type c/p. ? to transfer data (between the framer ic and the c/p) via the programmed i/o or burst mode each of the options are discussed in detail below. section 3.2.1 will discussed the issues associated with interfacing the framer to a c/p over an 8-bit bi-directional data bus. afterwards, section 3.2.2 will discuss data access (e.g., programmed i/o and burst) mode when interfaced to both motorola-type and intel-type c/p. 3.2.1 interfacing the XRT72L13 ds3 framer to the microprocessor over an 8 bit wide bi-direc- tional data bus the XRT72L13 ds3 framer microprocessor interface permits the user to interface it to a c/p over an 8 wide bi-directional data bus. 3.2.1.1 interfacing the framer to the c/p over an 8-bit wide bi-directional data bus. in general, interfacing the framer to an "8-bit" c/p is quite straight-forward. this is because most of the registers, within the framer, are 8-bits wide. further, in this mode, the c/p can read or write data into both even and odd numbered addresses within the framer address space. reading performance monitor (pmon) registers the only awkward issue that the user should be wary of (while operating in the "8-bit" mode) occurs when- ever the c/p needs to read the contents of one of the pmon (performance monitor) registers. the XRT72L13 ds3 framer consists of the following pmon registers. ? pmon lcv event count register ? pmon framing error event count register ? pmon received febe event count register ? pmon parity error event count register ? pmon received single-bit hec error count reg- ister ? pmon received multiple-bit hec error count register ? pmon received idle cell count register ? pmon received valid cell count register ? pmon discarded cell count register ? pmon transmitted idle cell count register ? pmon transmitted valid cell count register. unlike most of the registers within the framer, the pmon registers are "16-bit" registers (or 16-bits wide). table 4 lists each of these pmon registers as consisting of two 8-bit registers. one of these "8-bit" register is labeled "msb" (or most significant byte") t able 8: p in d escription of the m icroprocessor i nterface s ignals while the m icroprocessor i nterface is operating in the m otorola m ode p in n ame e quivalent p in in m otorola environment t ype d escription ale_as as* i address strobe: this "active-low" signal is used to latch the contents on the address bus input pins: a[8:0] into the microprocessor interface circuitry. the contents of the address bus are latched into the uni device on the rising edge of the ale_as signal. this signal can also be used to indicate the start of a burst cycle. rd _ds ds* i data strobe: this signal latches the contents of the bi-directional data bus pins into the addressed register (within the uni) during a write cycle. wr _rw r/w* i read/write* input: when this pin is "high", it indicates a read cycle. when this pin is "low", it indicates a write cycle. rdy_dtck dtack* o data transfer acknowledge: the uni device asserts dtack* in order to inform the cpu that the present read or write cycle is nearly complete. the 68000 family of cpus requires this signal from its peripheral devices, in order to quickly and properly complete a read or write cycle. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 176 and the other register is labeled "lsb" (or least sig- nificant byte). when an "8-bit" pmon register is concatenated with its "companion 8-bit" pmon reg- ister, one obtains the "full 16-bit expression" within that pmon register. the consequence of having these 16-bit registers is that an "8-bit" c/p will have to perform two consec- utive read operations in order to read in the full 16-bit expression contained within a given pmon register. to complicate matters, these pmon registers are "reset-upon-read" registers. more specifically, these pmon register are "reset-upon-read" in the sense that, the entire "16-bit" contents, within a given pmon register is reset, as soon as an "8-bit" c/p reads in either "byte" of this "two-byte" (e.g., 16 bit) expression. for example; consider that an "8-bit" c/p needs to read in the "pmon lcv event count" register. in order to ac- complish this task, the 8-bit c/p is going to have to read in the contents of "pmon lcv event count register - msb" (located at address = 0x40) and the contents of the "pmon lcv event count register - lsb (located at address = 0x41). these two "eight- bit" registers, when concatenated together, make up the "pmon lcv event count" register. if the 8-bit c/p reads in the "pmon lcv event count-lsb" register first; then the entire "pmon lcv event count" register will be reset to 0x0000. as a consequence, if the 8-bit c/p attempts to read in the "pmon lcv event count-msb" register in the very next read cycle, it will read in the value 0x00. the pmon holding register in order to "get-around" this "reset-upon-read" problem, the XRT72L13 ds3 framer includes a spe- cial register, which permits "8-bit" c/p to read in the full 16-bit contents of these pmon registers. this special register is called the "pmon holding" regis- ter; and is located at 0x56 within the framer address space. the way the pmon holding register works is as fol- lows. whenever an "8-bit" c/p reads in one of the bytes (of the "2-byte" pmon register); the contents of the "unread" (e.g., other) byte will be stored in the pmon holding register. therefore, the "8-bit" c/p must then read in the contents of the pmon holding register in the very next read operation. in summary: whenever an "8-bit" c/p needs to read a pmon register, it must execute the follow- ing steps. step 1: read in the contents of a given "8-bit" pmon register (it does not matter whether the c/p reads in the "-msb" or the "-lsb" register). step 2: read in the contents of the "pmon holding" register (located at address = 0x56). this register will contain the contents of the "other" byte. 3.2.2 data access modes as mentioned earlier, the microprocessor interface block supports data transfer between the framer and the c/p (e.g., "read" and "write" operations) via two modes: the "programmed i/o" and the "burst" modes. each of these "data access" modes are dis- cussed in detail below. 3.2.2.1 data access using programmed i/o "programmed i/o" is the conventional manner in which a microprocessor exchanges data with a pe- ripheral device. however, it is also the slowest meth- od of data exchange between the framer and the c/ p; as will be described in this text. the next two sections present detailed information on programmed i/o access, when the XRT72L13 ds3 framer is operating in the "intel mode" and in the "motorola mode". 3.2.2.1.1 programmed i/o access in the "intel" mode if the XRT72L13 ds3 framer is interfaced to an "in- tel-type" c/p (e.g., the 80x86 family, etc.), then it should be configured to operate in the "intel" mode (by tying the "moto" pin to ground). intel-type "read" and "write" operations are described below. 3.2.2.1.1.1 the intel mode read cycle whenever an intel-type c/p wishes to read the contents of a register or some location within the re- ceive lapd message buffer or the receive oam cell buffer, (within the framer device), it should do the fol- lowing. 1. place the address of the "target" register or buffer location (within the framer) on the address bus input pins a[8:0]. 2. while the c/p is placing this address value on the address bus, the address decoding circuitry (within the user's system) should assert the cs* (chip select) pin of the framer, by toggling it "low". this action enables further communication between the c/p and the framer microproces- sor interface block. 3. toggle the ale_as (address latch enable) input pin "high". this step enables the "address bus" input drivers, within the microprocessor interface block of the framer. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address" ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 177 data setup time"), the c/p should toggle the ale_as pin "low". this step causes the framer device to "latch" the contents of the "address bus" into its internal circuitry. at this point, the address of the register or buffer locations (within the framer), has now been selected. 5. next, the c/p should indicates that this current bus cycle is a "read" operation by toggling the rd _ds (read strobe) input pin "low". this action also enables the bi-directional data bus output drivers of the framer device. at this point, the "bi-directional" data bus output drivers will pro- ceed to drive the contents of the "latched addressed" register (or buffer location) onto the bi-directional data bus, d[7:0]. 6. immediately after the c/p toggles the "read strobe" signal "low", the framer device will toggle the rdy_dtck output pin "low". the framer device does this in order to inform the c/p that the data (to be read from the data bus) is "not ready" to be "latched" into the c/p. 7. after some settling time, the data on the "bi-direc- tional" data bus will stabilize and can be read by the c/p. the XRT72L13 ds3 framer will indi- cate that this data can be read by toggling the rdy_dtck (ready) signal "high". 8. after the c/p detects the rdy_dtck signal (from the XRT72L13 ds3 framer), it can then ter- minate the read cycle by toggling the rd _ds (read strobe) input pin "high". figure 47 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during an "intel-type" programmed i/o read opera- tion. 3.2.2.1.1.2 the intel mode write cycle whenever an intel-type c/p wishes to write a byte or word of data into a register or buffer location, within the framer, it should do the following. 1. assert the ale_as (address latch enable) input pin by toggling it "high". when the c/p asserts the ale_as input pin, it enables the "address bus input drivers" within the framer chip. 2. place the address of the "target" register or buffer location (within the framer), on the address bus input pins, a[8:0]. 3. while the c/p is placing this address value onto the address bus, the address decoding cir- cuitry (within the user's system) should assert the cs* input pin of the framer device by toggling it "low". this step enables further communication between the c/p and the framer microproces- sor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time); the c/p should toggle the ale_as input pin "low". this step causes the framer device to "latch" the contents of the "address bus" into its internal circuitry. at this point, the address of the register or buffer loca- tion (within the framer), has now been selected. 5. next, the c/p should indicate that this current bus cycle is a "write" operation; by toggling the wr _rw (write strobe) input pin "low". this action also enables the "bi-directional" data bus input drivers of the framer device. 6. the c/p should then place the byte or word that it intends to write into the "target" register, on the bi-directional data bus, d[7:0]. 7. after waiting the appropriate amount of time, for the data (on the bi-directional data bus) to settle; f igure 47. b ehavior of m icroprocessor i nterface signals during an "i ntel - type " p rogrammed i/o r ead o peration ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid address of target register wrb_rw XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 178 the c/p should toggle the wr _rw (write strobe) input pin "high". this action accom- plishes two things: a. it latches the contents of the bi-directional data bus into the XRT72L13 ds3 framer microproces- sor interface block. b. it terminates the write cycle. figure 48 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during an "intel-type" programmed i/o write opera- tion. 3.2.2.1.2 programmed i/o access in the motor- ola mode if the XRT72L13 ds3 framer is interfaced to a "mo- torola-type" c/p (e.g., the mc680x0 family, etc.); it should be configured to operate in the "motorola" mode (by tying the "moto" pin to vcc). motorola- type programmed i/o "read" and "write" operations are described below. 3.2.2.1.2.1 the motorola mode read cycle whenever a "motorola-type" c/p wishes to read the contents of a register or some location within the receive lapd message or receive oam cell buffer, (within the framer device) it should do the following. 1. assert the ale_as (address-strobe) input pin by toggling it low. this step enables the address bus input drivers, within the microprocessor inter- face block of the framer ic. 2. place the address of the "target" register (or buffer location) within the framer, on the address bus input pins, a[8:0]. 3. at the same time, the address decoding circuitry (within the user's system) should assert the cs* (chip select) input pin of the framer device, by toggling it "low". this action enables further com- munication between the c/p and the framer microprocessor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to latch the contents of the "address bus" into its internal circuitry. at this point, the address of the register or buffer loca- tion (within the framer) has now been selected. 5. further, the c/p should indicate that this cycle is a "read" cycle by setting the wr _rw (r/w*) input pin "high". 6. next the c/p should initiate the current bus cycle by toggling the rd _ds (data strobe) input pin "low". this step enables the bi-directional data bus output drivers, within the XRT72L13 ds3 framer device. at this point, the bi-direc- tional data bus output drivers will proceed to driver the contents of the "address" register onto the bi-directional data bus, d[7:0]. 7. after some settling time, the data on the "bi-direc- tional" data bus will stabilize and can be read by the c/p. the XRT72L13 ds3 framer will indi- cate that this data can be read by asserting the rdy_dtck (dtack) signal. 8. after the c/p detects the rdy_dtck signal (from the XRT72L13 ds3 framer) it will terminate the read cycle by toggling the "rd _ds" (data strobe) input pin "high". figure 49 presents a timing diagram which illustrates the behavior of the microprocessor interface signals during a "motorola-type" programmed i/o read op- eration. f igure 48. b ehavior of the m icroprocessor i nterface s ignals , during an "i ntel - type " p rogrammed i/ o w rite o peration ale_as a[8:0] cs* d[15:0] wrb_rw data to be written address of target register rdb_ds ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 179 3.2.2.1.2.2 the motorola mode write cycle whenever a motorola-type c/p wishes to write a byte or word of data into a register or buffer location, within the framer, it should do the following. 1. assert the ale_as (address select) input pin by toggling it "low". this step enables the "address bus" input drivers (within the framer chip). 2. place the address of the "target" register or buffer location (within the framer), on the address bus input pins, a[8:0]. 3. while the c/p is placing this address value onto the address bus, the address-decoding cir- cuitry (within the user's system) should assert the cs* (chip select) input pins of the framer by tog- gling it "low". this step enables further communi- cation between the c/p and the framer micro- processor interface block. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to "latch" the contents of the "address bus" into its own circuitry. at this point, the address of the register or buffer location (within the framer), has now been selected. 5. further, the c/p should indicate that this cur- rent bus cycle is a "write" operation by toggling the wr _rw (r/w*) input pin "low". 6. the c/p should then place the byte or word that it intends to write into the "target" register, on the bi-directional data bus, d[7:0]. 7. next, the c/p should initiate the bus cycle by toggling the rd _ds (data strobe) input pin "low". when the XRT72L13 ds3 framer senses that the wr _rw (r/w*) input pin is "high" and that the rd _ds (data strobe) input pin has toggled "low", it will enable the "input drivers" of the bi- directional data bus, d[7:0]. 8. after waiting the appropriate time, for this newly placed data to settle on the bi-directional data bus (e.g., the "data setup" time) the framer will assert the rdy_dtck output signal. 9. after the c/p detects the rdy_dtck signal (from the framer), the c/p should toggle the rd _ds input pin "high". this action accom- plishes two things. a. it latches the contents of the bi-directional data bus into the XRT72L13 ds3 microprocessor interface block. b. it terminates the "write" cycle. figure 50 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during a "motorola-type" programmed i/o write op- eration. f igure 49. i llustration of the b ehavior of m icroprocessor i nterface signals , during a "m otorola - type " p rogrammed i/o r ead o peration ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data address of target register wrb_rw XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 180 3.2.2.2 data access using burst mode i/o burst mode i/o access is a much faster way to trans- fer data between the c/p and the microprocessor interface (of the XRT72L13 ds3 framer), than pro- grammed i/o. the reason why burst mode i/o is so much faster follows. data is placed upon the address bus input pins a[8:0]; only for the very first access, within a given burst access. the remaining read or write operations (within this burst access) do not require the place- ment of the address data on the address data bus. as a consequence, the user does not have to wait through the "address setup" and "hold" times; for each of these read/write operation, within the "burst" access. it is important to note that there are some limitations associated with burst mode i/o operations. 1. all cycles within the burst access, must be either "all read" or "all write" cycles. no "mixing of "read" and "write" cycles is permitted. 2. a burst access can only be used when "read" or "write" operations are to be employed over a contiguous range of address locations, within the framer device. 3. the very first "read" or "write" cycle, within a burst access, must start at the "lowest" address value, of the range of addresses to be accessed. subsequent operations will automatically be incremented to the very next higher address value. examples of burst mode i/o operations are present- ed below for read and write operations, with both "in- tel-type" and "motorola-type" c/p. 3.2.2.2.1 burst i/o access in the intel mode if the XRT72L13 ds3 framer is interfaced to an "in- tel-type" c/p (e.g., the 80x86 family, etc.), then it should be configured to operate in the "intel" mode (by tying the "moto" pin to ground). intel-type "read" and "write" burst i/o access operations are described below. 3.2.2.2.1.1 the "intel-mode" read burst access whenever an "intel-type" c/p wishes to read the contents of numerous registers or buffer locations over a "contiguous" range of addresses; then it should do the following. a. perform the initial "read" operation of the burst access. b. perform the remaining "read" operations of the burst access. c. terminate the "burst access" operation. each of these "operations" within the burst access are described below. 3.2.2.2.1.1.1 the initial read operation the initial read operation of an "intel-type" read burst access is accomplished by executing a "programmed i/o" read cycle as summarized below. a.0 execute a single ordinary (programmed i/ o) read cycle, as described in steps a.1 through a.7 below. a.1 place the address of the "initial-target" register or buffer location (within the framer) on the address bus input pins a[8:0]. f igure 50. i llustration of the b ehavior of the m icroprocessor i nterface signal , during a "m otor - ola - type " p rogrammed i/o w rite o peration ale_as a[8:0] cs* d[15:0] rdb_ds rdy_dtck data to be written address of target register wrb_rw ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 181 a.2 while the c/p is placing this address value onto the address bus, the address decoding circuitry (within the user's system) should assert the cs* input pin of the framer, by tog- gling it "low". this step enables further commu- nication between the c/p and the framer microprocessor interface block. a.3 assert the ale_as (address latch enable) pin by toggling it "high". this step enables the "address bus" input drivers, within the micro- processor interface block of the framer. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate "address" data setup time"), the c/p should then tog- gle the ale_as pin "low". this step latches the contents, on the address bus pins, a[8:0], into the XRT72L13 ds3 framer microproces- sor interface block. at this point, the "initial" address of the burst access has now been selected. n ote : the ale_as input pin should remain "low" for the remainder of this "burst access" operation. a.5 next, the c/p should indicate that this cur- rent bus cycle is a "read" operation by tog- gling the rd _ds (read strobe) input pin "low". this action also enables the "bi-directional" data bus output drivers of the framer device. at this point, the bi-directional data bus output drivers will proceed to drive the contents of the "addressed" register onto the "bi-directional" data bus, d[7:0]. a.6 immediately after the c/p toggles the "read strobe" signal "low", the framer device will tog- gle the rdy_dtck (ready) output pin "low". the framer device does this in order to inform the c/p that the data (to be read from the data bus) is "not ready" to be latched into the c/p. a.7 after some settling time, the data on the "bi- directional" data bus will stabilize and can be read by the c/p. the XRT72L13 ds3 framer will indicate that this data is ready to be read, by toggling the rdy_dtck (ready) signal "high". a.8 after the c/p detects the rdy_dtck signal (from the XRT72L13 ds3 framer ic), it can then will terminate the "read" cycle by toggling the rd _ds (read strobe) input pin "high". figure 51 presents an illustration of the behavior of the microprocessor interface signals, during the "ini- tial" read operation, within a burst i/o cycle; for an intel-type c/p. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 182 at the completion of this initial read cycle, the c/p has read in the contents of the first register or buffer location (within the XRT72L13 ds3 framer) for this particular burst i/o access operation. in order to illus- trate how this "burst access operation" works, the byte (or word) of data, that is being read in figure 51 , has been labeled "valid data at offset = 0x00". this label indicates that the c/p is reading the very first register (or buffer location) in this burst access opera- tion. 3.2.2.2.1.1.2 the subsequent read operations the procedure that the c/p must use to perform the remaining read cycles, within this burst access operation, is presented below. b.0 execute each subsequent read cycles, as described in steps 1 through 3 below. b.1 without toggling the ale_as input pin (e.g., keeping it "low"); toggle the rd _ds input pin "low". this step accomplishes the following. a. the framer will internally increments the "latched address" value (within the microprocessor inter- face circuitry). b. the output drivers of the "bi-directional" data bus, d[7:0] are enabled. at some time later, the regis- ter or buffer location corresponding to the "incre- mented" latched address value will be driven onto the bi-directional data bus. b.2 immediately after the "read strobe" pin toggles "low" the framer ic will toggle the rdy_dtck (ready) output pin "low" to indicate its "not ready" status. b.3 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the XRT72L13 ds3 framer will indicate that this data is ready to be read by toggling the rdy_dtck (ready) signal "high". b.4 after the c/p detects the rdy_dtck signal (from the XRT72L13 ds3 framer), it can then terminates the "read" cycle by toggling the rd _ds (read strobe) input pin "high". f igure 51. b ehavior of the m icroprocessor i nterface s ignals , during the "i nitial " r ead o peration of a b urst c ycle (i ntel t ype p rocessor ) ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data of offset = 0x00 address of initial target register (offset = 0x00) wrb_rw ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 183 for subsequent read operations, within this burst cy- cle, the c/p simply repeats steps 1 through 3, as il- lustrated in figure 52 . in addition to the behavior of the microprocessor in- terface signals, figure 52 also illustrates other points regarding the "burst access operation". a. the framer internally increments the address value, from the original "latched" value shown in figure 51 . this is illustrated by the data, appear- ing on the data bus, (for the first read access) being labeled "valid data at offset = 0x01"; and that for the second read access being labeled "valid data at offset = 0x02.". b. the framer performs this "address incrementing" process even though there are no changes in the address bus data, a[8:0]. 3.2.2.2.1.1.3 terminating the burst access operation the burst access operation will be terminated upon the rising edge of the ale_as input signal. at this point the framer will cease to internally increment the "latched" address value. further, the c/p is now free to execute either a "programmed i/o" access or to start another "burst access" operation with the XRT72L13 ds3 framer. 3.2.2.2.1.2 the "intel-mode" write burst access whenever an "intel-type" c/p wishes to write data into a "contiguous" range of addresses, then it should do the following. a. perform the initial "write" operation; of the burst access. b. perform the remaining "write" operations, of the burst access. c. terminate the burst access operation. each of these "operations" within the burst access are described below. 3.2.2.2.1.2.1 the initial write operation the initial write operation of an "intel-type" write burst access is accomplished by executing a "pro- grammed i/o" write cycle as summarized below. a.0 execute a single ordinary (programmed i/ o) write cycle, as described in steps a.1 through a.7 below. a.1 place the address of the "initial" target register (or buffer location) within the framer, on the address bus pins, a[8:0]. a.2 a.2 at the same time, the "address-decoding" circuitry (within the user's system) should assert the cs* (chip select) input pin of the framer, by toggling it "low". this step enables further communication between the c/p and the framer microprocessor interface block. a.3 assert the ale_as (address latch enable) input pin "high". this step enables the address bus input drivers, within the microprocessor interface block of the framer. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time); the c/p should then toggle the ale_as input pin "low". this step latches the contents, on the address bus pins, a[8:0], into the XRT72L13 ds3 framer microprocessor interface block. at this point, the "initial" f igure 52. b ehavior of the m icroprocessor i nterface s ignals , during subsequent "r ead " o pera - tions within the b urst i/o c ycle ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data at offset =0x01 wrb_rw not valid valid data at offset =0x02 address of initial target register (offset = 0x00) XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 184 address of the "burst access" has now been selected. n ote : the ale_as input pin should remain "low" for the remainder of this "burst i/o access" operation. a.5 next, the c/p should indicate that this cur- rent bus cycle is a "write" operation by keeping the rd _ds pin "high" and toggling the wr _rw (write strobe) pin "low". this action also enables the "bi-directional" data bus input driv- ers of the framer device. a.6 the c/p places the byte (or word) that it intends to write into the "target" register on the "bi-directional data" bus, d[7:0]. a.7 after waiting the appropriate amount of time, for the data (on the bi-directional data bus) to set- tle, the c/p should toggle the wr _rw (write strobe) input pin "high". this action accom- plishes two things. a. it latches the contents of the bi-directional data bus into the XRT72L13 ds3 framer microproces- sor interface block. b. it terminates the write cycle. figure 53 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during the "initial" write operation within a burst ac- cess, for an "intel-type" c/p. at the completion of this initial write cycle, the c/p has written a byte or word into the first register or buffer location (within the XRT72L13 ds3 framer) for this particular burst access operation. in order to il- lustrate this point, the byte (or word) of data, that is being written in figure 53 has been labeled "data to be written (offset = 0x00)". 3.2.2.2.1.2.2 the subsequent write operations the procedure that the c/p must use to perform the remaining write cycles, within this burst access operation, is presented below. b.0 execute each subsequent write cycle, as described in steps b.1 through b.3. b.1 without toggling the ale_as input pin (e.g., keeping it "low"); apply the value of the next byte or word (to be written into the framer) to the bi-directional data bus pins, d[7:0]. f igure 53. b ehavior of the m icroprocessor i nterface signals , during the "i nitial " w rite o peration of a b urst c ycle (i ntel - type p rocessor ) ale_as a[8:0] cs* d[7:0] wrb_rw data to be written (offset = 0x00) address of initial target register (offset = 0x00) rdb_ds ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 185 b.2 toggle the wr _rw (write strobe) input pin "low". this step accomplishes two things. a. it enables the input drivers of the bi-directional data bus. b. it causes the framer to internally increment the value of the "latched" address. b.3 after waiting the appropriate amount of settling time the data, in the internal data bus, will stabi- lize and is ready to be latched into the framer microprocessor interface block. at this point, the c/p should latch the data into the framer by toggling the wr _rw input pin "high". for subsequent write operations, within this burst i/o access, the c/p simply repeats steps b.1 through b.3, as illustrated in figure 54 . 3.2.2.2.1.2.3 terminating the burst i/o access burst access operation will be terminated upon the rising edge of the ale_as input signal. at this point the framer will cease to internally increment the "latched" address value. further, the c/p is now free to execute either a "programmed i/o" access or to start another "burst access operation" with the XRT72L13 ds3 framer. 3.2.2.2.2 burst i/o access in the motorola mode if the XRT72L13 ds3 framer is interfaced to a "mo- torola-type" c/p (e.g., the mc680x0 family, etc.), then it should be configured to operate in the "motor- ola" mode (by tying the "moto" pin to vcc). motoro- la-type "read" and "write" burst i/o access opera- tions are described below. 3.2.2.2.2.1 the "motorola-mode" read burst i/ o access operation whenever a "motorola-type" c/p wishes to read the contents of numerous registers or buffer locations over a "contiguous" range of addresses, then it should do the following. a. perform the initial "read" operation of the burst access. b. perform the remaining "read" operations; in the burst access. c. terminate the "burst access" operation. each of these operations, within the burst access are discussed below. 3.2.2.2.2.1.1 the initial read operation the initial read operation of a "motorola-type" read burst access is accomplished by executing a "pro- grammed i/o read" cycle, as summarized below. a.0 execute a single ordinary (programmed i/ o) read cycle, as described in steps a.1 through a.8 below. a.1 assert the ale_as (as*) input pin by toggling it "low". this step enables the "address bus" input drivers (within the XRT72L13 ds3 framer) within the framer microprocessor interface block. a.2 place the address of the "initial" target register or buffer location (within the framer), on the address bus input pins, a[8:0]. a.3 at the same time, the address-decoding cir- cuitry (within the user's system) should assert the cs* (chip select) input pins of the framer by toggling it "low". this action enables further f igure 54. b ehavior of the m icroprocessor i nterface s ignals , during subsequent "w rite " o pera - tions within the b urst i/o c ycle ale_as wrb_rw a[8:0] cs* d[15:0] rdy_dtck data written at offset =0x01 rdb_ds data written at offset =0x02 address of initial target register (offset = 0x00) XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 186 communication between the c/p and the framer microprocessor interface block. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to latch the contents of the address bus into its internal circuitry. at this point, the "initial" address of the burst access has now been selected. a.5 further, the c/p should indicate that this cycle is a "read" cycle by setting the wr _rw (r/w*) input pin "high". a.6 next the c/p should initiate the current bus cycle by toggling the rd _ds (data strobe) input pin "low". this step will enable the bi- directional data bus output drivers, within the XRT72L13 ds3 framer. at this point, the bi- directional data bus output drivers will proceed to driver the contents of the "address" register onto the bi-directional data bus. a.7 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the XRT72L13 ds3 framer will indicate that this data can be read by asserting the rdy_dtck (dtack) signal. a.8 after the c/p detects the rdy_dtck signal (from the XRT72L13 ds3 framer) it will termi- nate the read cycle by toggling the "rd _ds" (data strobe) input pin "high". figure 55 presents an illustration of the behavior of the microprocessor interface signals during the "ini- tial" read operation, within a burst i/o cycle; for a motorola-type c/p. at the completion of this initial read cycle, the c/p has read in the contents of the first register or buffer location (within the XRT72L13 ds3 framer) for this particular burst access operation. in order to illus- trate how this "burst i/o cycle" works, the byte (or word) of data, that is being read in figure 55 has been labeled "valid data at offset = 0x00". this indi- cates that the c/p is reading the very first register (or buffer location) in this burst access. 3.2.2.2.2.1.2 the subsequent read operations the procedure that the c/p must use to perform the remaining read cycles, within this burst access operation, is presented below. b.0 execute each subsequent read cycle, as described in steps b.1 through b.3, below. b.1 without toggling the ale_as input pin (e.g., keeping it "high"); toggle the rd _ds (data strobe) input pin "low". this step accomplishes the following. a. the framer internally increments the "latched address" value (within the microprocessor inter- face circuitry). b. the output drivers of the "bi-directional" data bus (d[7:0]) are enabled. at some time later, the reg- ister or buffer location corresponding to the "incremented" latched address value will be driven onto the bi-directional data bus. n ote : in order to insure that the XRT72L13 ds3 framer will interpret this signal as being a "read" signal, the c/ p should keep the wr _rw input pin "high". f igure 55. b ehavior of the m icroprocessor i nterface s ignals , during the "i nitial " r ead o peration of a b urst c ycle (m otorola t ype p rocessor ) ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data at offset = 0x00 address of initial target register (offset = 0x00) wrb_rw ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 187 b.2 after some settling time, the data on the bi- directional data bus will stabilize and can be read by the c/p. the XRT72L13 ds3 framer will indicate that this data is ready to be read by asserting the rdy_dtck (dtack*) signal. b.3 after the c/p detects the rdy_dtck signal (from the XRT72L13 ds3 framer), it terminates the "read" cycle by toggling the rd _ds (data strobe) input pin "high". for subsequent read operations, within this burst cy- cle, the c/p simply repeats steps b.1 through b.3, as illustrated in figure 56 . 3.2.2.2.2.1.3 terminating the burst access operation the burst i/o access will be terminated upon the fall- ing edge of the ale_as input signal. at this point the framer will cease to internally increment the "latched" address value. further, the c/p is now free to exe- cute either a "programmed i/o" access or to start an- other "burst access" operation with the XRT72L13 ds3 framer. 3.2.2.2.2.2 the "motorola-mode" write burst access whenever a "motorola-type" c/p wishes to write the contents of numerous registers or buffer locations over a "contiguous" range of addresses, then it should do the following. a. perform the initial "write" operation; of the burst access. b. perform the remaining "write" operations, of the burst access. c. terminate the burst access operation. each of these "operations" within the burst access are described below. 3.2.2.2.2.2.1 the initial write operation the initial write operation of a "motorola-type" write burst access is accomplished by executing a "pro- grammed i/o write cycle" as summarized below. a.0 execute a single ordinary (programmed i/ o) write cycle, as described in steps a.1 through a.7 below. a.1 assert the ale_as (address strobe) input pin by toggling it "low". this step enables the address bus input drivers (within the XRT72L13 ds3 framer). a.2 place the address of the "initial" target register or buffer location (within the framer), on the address bus input pins, a[8:0]. a.3 at the same time, the address-decoding cir- cuitry (within the user's system) should assert the cs* input pin of the framer by toggling it "low". this step enables further communication between the c/p and the framer micropro- cessor interface block. a.4 after allowing the data on the address bus pins to settle (by waiting the appropriate "address setup" time), the c/p should toggle the ale_as input pin "high". this step causes the framer device to "latch" the contents of the "address bus" into its own circuitry. at this f igure 56. b ehavior the m icroprocessor i nterface s ignals , during subsequent "r ead " o perations within the b urst i/o c ycle (m otorola - type c/p) ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck not valid valid data at offset =0x01 wrb_rw not valid valid data at offset =0x02 address of initial target register (offset = 0x00) XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 188 point, the "initial" address of the burst access has now been selected. a.5 further, the c/p should indicate that this cur- rent bus cycle is a "write" operation by toggling the wr _rw (r/w*) input pin "low". a.6 the c/p should then place the byte or word that it intends to write into the "target" register, on the bi-directional data bus, d[7:0]. a.7 next, the c/p should initiate the bus cycle by toggling the rd _ds (data strobe) input pin "low". when the XRT72L13 ds3 framer senses that the wr _rw input pin is "low", and that the rd _ds input pin has toggled "low" it will enable the "input drivers" of the bi-direc- tional data bus, d[7:0]. a.8 after waiting the appropriate amount of time, for this newly placed data to settle on the bi-direc- tional data bus( e.g., the "data setup" time) the framer will assert the rdy_dtck (dtack) out- put signal. a.9 after the p/c detects the rdy_dtck signal (from the framer) it should toggle the rd _ds input pin "high". this action accomplishes two things: a. it latches the contents of the bi-directional data bus into the XRT72L13 ds3 framer microproces- sor interface block. b. it terminates the "write" cycle. figure 57 presents a timing diagram which illustrates the behavior of the microprocessor interface signals, during the "initial" write operation within a burst ac- cess, for a "motorola-type" c/p. at the completion of this initial write cycle, the c/p has written a byte or word into the first register or buffer location (within the XRT72L13 ds3 framer) for this particular burst i/o access. in order to illustrate how this "burst i/o cycle" works, the byte (or word) of data, that is being written in figure 57 has been la- beled "data to be written (offset = 0x00)." 3.2.2.2.2.2.2 the subsequent write operations the procedure that the c/p must use to perform the remaining write cycles, within this burst access operation, is presented below. b.0 execute each subsequent write cycle, as described in steps b.1 through b.3 b.1 without toggling the ale_as (address strobe) input pin (e.g., keeping it "high"); apply the value of the next byte or word (to be written into the framer) to the bi-directional data bus pins, d[7:0]. b.2 toggle the rd _ds (data strobe) input pin "low". this step accomplishes the following. a. the framer internally increments the "latched address" value (within the microprocessor inter- face). b. the input drivers of the bi-directional data bus are enabled. n ote : in order to insure that the XRT72L13 ds3 framer will interpret this signal as being a "write" signal, the c/ p should keep the wr _rw input pin "low". b.3 after some settling time, the data, in the inter- nal data bus, will stabilize and is ready to be latched into the framer microprocessor inter- face block. the microprocessor interface block f igure 57. b ehavior of the m icroprocessor i nterface signals , during the "i nitial " w rite o peration of a b urst c ycle (m otorola - type p rocessor ) ale_as a[8:0] cs* d[15:0] rdb_ds rdy_dtck data to be written (offset = 0x00) address of initial target register (offset = 0x00) ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 189 will indicate that this data is ready to be latched by asserting the rdy_dtck (dtack) output sig- nal. at this point, the c/p should latch the data into the framer by toggling the rd _ds input pin "high". for subsequent write operations, within this burst i/o access, the c/p simply repeats steps b.1 through b.3 as illustrated in figure 58 . 3.2.2.2.2.2.3 terminating the burst i/o access the burst i/o access will be terminated upon the fall- ing edge of the ale_as input signal. at this point the framer will cease to internally increment the "latched" address value. further, the c/p is now free to exe- cute either a "programmed i/o" access or to start an- other "burst i/o access" with the XRT72L13 ds3 framer. 3.3 o n -c hip r egister o rganization the microprocessor interface section, within the framer allows the user to do the following. ? configure the framer into a wide variety of operat- ing modes. ? employ various features of the framer. ? perform status monitoring ? enable/disable and service interrupt conditions all of these things are accomplished by reading from and writing to the many on-chip registers within the framer. table 4 lists each of these registers and their corresponding address locations within the framer address space. 3.3.1 framer register addressing the array of on-chip registers consists of a variety of register types. these registers are denoted in table 4, as follows. r/o - read only registers. r/w - read/write registers rur - reset-upon-read registers additionally, some of these registers consists of both "r/o" and "r/w" bit-fields. these registers are de- noted in table 4 as "combination of r/w and r/o". the bit-format and definitions for each of these regis- ters are presented in section 3.3.2 3.3.2 m13 mux/framer register description this section provides a function description of each bit-field within each of the on-chip framer register. n ote : for all on-chip registers, a table containing the bit- format of the register is presented. additionally, these tables also contain the default values for each of these reg- ister bits. finally, the function description, associated with each register bit-field is presented, along with a reference to a section number, within this data sheet, that provides a more in-depth discussion of the functions associated with this register bit-field. 3.3.2.1 operating mode register f igure 58. b ehavior of the m icroprocessor i nterface s ignals , during subsequent "w rite " o pera - tions with the b urst i/o c ycle (m otorola - type c/p) ale_as rdb_ds a[8:0] cs* d[15:0] rdy_dtck data written at offset =0x01 wrb_rw data written at offset =0x02 address of initial target register (offset = 0x00) XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 190 bit 7 - local loop-back mode this bit-field permits the user to configure the XRT72L13 m13 device to operate in the local loop- back mode. setting this bit-field to 1 configures the XRT72L13 m13 chip to operate in the local loopback mode. setting this bit-field to 0 configures the XRT72L13 m13 chip to not operate in the local loopback mode. bit 6 - line loopback mode this bit-field permits the user to configure the XRT72L13 m13 device to operate in the line loop- back mode. setting this bit-field to 1 configures the XRT72L13 m13 chip to operate in the line loopback mode. setting this bit-field to 0 configures the XRT72L13 m13 chip to not operate in the line loopback mode. bit 5 - internal los enable this read/write bit-field permits the user to config- ure the XRT72L13 m13 chip to either declare an los (loss of signal) condition, based upon the internal circuits criteria or not. setting this bit-field to 0 configures the XRT72L13 m13 chip to not declare an los condition, based upon its own internal criteria. setting this bit-field to 1 configures the XRT72L13 los condition, based upon its own internal criteria. n otes : 1. the XRT72L13 m13 chip will declare an los condition anytime the rlos input pin is set high independent of the setting of this bit-field. 2. for more information on the XRT72L13 m13 chips internal criteria for loss of signal please see section _. bit 4 - reset this read/write bit-field permits the user to com- mand the XRT72L13 m13 chip into a software reset state. if the XRT72L13 m13 chip is commanded into the reset state, all of its internal register bits will automatically be set to their default condition. the user can configure the XRT72L13 to operate in the reset state by inducing a 0 to 1 transition in this bit-field. bit 3 - interrupt enable reset this read/write bit-field permits the user to config- ure the XRT72L13 m13 chip to automatically disable all interrupts that are activated. setting this bit-field to 0 configures the XRT72L13 m13 chip to not disable the interrupt enable status of any interrupt following their activation. setting this bit-field to 1 configures the XRT72L13 m13 to disable the interrupt enable status of any in- terrupt following their activation. for more information on this feature, please see sec- tion _. bit 2 - frame format select this read/write bit-field permits the user to select the framing format that the XRT72L13 m13 device will be operating in. setting this bit-field to 0 configures the XRT72L13 m13 device to operate in the c-bit parity framing format. setting this bit-field to 1 configures the XRT72L13 m13 device to operate in the m13 framing format. bits 1 and 0 - timrefsel[1:0] - timing reference select operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1] timrefsel[0] r/w r/w r/w r/w r/w r/w r/w r/w 00101011 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 191 these two read/write bit-fields permits the user to select both a framing reference and a timing ref- erence for the transmit section of the XRT72L1372l13. the following table relates the states of the two-fields to the selected framing and timing references. n ote : for more information on framing and timing refer- ences, please see section _. 3.3.2.2 i/o control register bit 7 - disable txloc bit 6 - loc (loss of clock) indicator bit 5 - disable rxloc bit 4 - ami/b3zs* line code select this read/write bit-field pemits the user to config- ure the XRT72L13 m13 device to transmit and re- ceive data via the ami (alternate mark inversion) line code or via the b3zs (bipolar 3 zero substitution) line code. setting this bit-field to 0 configures the XRT72L13 m13 device to transmit and receive data (via the ds3 framer block) via the b3zs format. setting this bit- field to 1 configures the XRT72L13 m13 device to transmit and receive data via the ami line code. bit 3 - single-rail/dual-rail select this read/write bit-field permits the user to config- ure the XRT72L13 m13 device to operate in the sin- gle-rail or dual-rail format. setting this bit-field to 0 configures the XRT72L13 to operate in the dual-rail mode. in this mode, the transmit section of the XRT72L13 m13 device will output data to the liu via the txpos and txneg output pins. additionally, the receive section of the device will receive data from the liu via rxpos and rxneg input pins. setting this bit-field to 1 configures the XRT72L13 to operate in the single-rail mode. in this mode, the transmit section of the XRT72L13 m13 device will output data to the liu, in a binary data stream man- ner via the txpos output pin. additionally, the re- ceive section of the device will receive data from the liu, in a binary data stream manner, via the rxpos input pin. bit 2 - txclkinv this read/write bit-field permits the user to config- ure the XRT72L13 m13 device to output data, via the txpos and txneg output pins, upon the rising or falling edge of txlineclk. setting this bit-field to 0 configures the XRT72L13 m13 device to output data via the txpos and tx- neg output pins, on the rising edge of txlineclk. setting this bit-field to 1 configures the XRT72L13 m13 device to output data via the txpos and tx- neg output pins, on the falling edge of txlineclk. bit 1 - rxclkinv t im r ef s el [1:0] f raming r eference t iming r eference 00 asynchronous rxlineclk input signal 01 txframeref rxlineclk input signal 10 asynchronous txinclk input signal 11 asynchronous txinclk input signal i/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/b3zs* line code single-rail/ dual-rail* txclkinv rxclkinv reframe] r/w ro r/w r/w r/w r/w r/w r/w 10100000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 192 this read/write bit-field permits the user to config- ure the XRT72L13 m13 device to latch data on the rxpos and rxneg input pins input pins, into the XRT72L13 m13 device, on the rising or falling edge of rxlineclk. setting this bit-field to 0 configures the XRT72L13 m13 device to latch the data on the rxpos and rxneg input pins, into the device, on the rising edge of rxlineclk. setting this bit-field to 1 configures the XRT72L13 m13 device to latch the data on the rxpos and rxneg input pins, into the device, on the falling edge of rxlineclk. bit 0 - reframe this read/write bit-field permits the user to config- ure the receive section of the XRT72L13 m13 de- vice to start a new frame search. a 0 to 1 transi- tion in this bit-field will force the chip to start a new frame search. 3.3.2.3 part number register the part number register (within the XRT72L13 m13 device) contains the fixed value of 0x22. this part number value permits the user to read out the con- tents of this register and to uniquely identify this de- vice as the XRT72L13 m13 device. 3.3.2.4 version number register the version number register (within the XRT72L13 m13 device) contains a value which corresponds to the revision number. the very first revision of the XRT72L13 (revision a) will contain the fixed value 0x01. the contents of the version number regis- ter will be incremented for subsequent version (if needed). 3.3.2.5 block interrupt enable register bit 7 - rx ds3 interrupt enable part number register (address = 0x02) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 part number value ro ro ro ro ro ro ro ro 00100010 version number register (address = 0x03) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 version number value ro ro ro ro ro ro ro ro 00000001 block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx ds3 interrupt enable not used not used m13 interrupt enable not used not used tx ds3 interrupt enable] one second interrupt enable] r/w r/o r/o r/w r/o r/o r/w r/w 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 193 this read/write bit-field permits the user to enable or disable all receive ds3 framer related interrupts (within the XRT72L13) at the block level. setting this bit-field to 0 disables all receive ds3 framer related interrupts within the XRT72L13 m13 device. setting this bit-field to 1 enables all receive ds3 framer related interrupts (within the XRT72L13 m13 device) at the block level. n ote : setting this bit-field to 1 does not enable all receive ds3 framer related interrupts. each of these interrupts can still be disabled at the source level. how- ever, setting this bit-field to 0 does disable all receive ds3 framer related interrupt. bit 4 - m13 interrupt enable this read/write bit-field permits the user to enable- or disable all m13 multiplexer related interrupts (within the XRT72L13) at the block level. setting this bit-field to 0 disables all m13 multiplex- er related interrupts within the XRT72L13 m13 de- vice. setting this bit-field to 1 disables all m13 multiplex- er related interrupts (within the XRT72L13 m13 de- vice) at the block level. bit 1 - tx ds3 interrupt enable this read/write bit-field permits the user to enable or disable the transmit ds3 framer related inter- rupts (within the XRT72L13) at the block level. setting this bit-field to 0 disables all transmit ds3 framer related interrupts within the XRT72L13 m13 device. setting this bit-field to 1 disables all transmit ds3 framer related interrupts (within the XRT72L13 m13 device) at the block level. bit 0 - one second interrupt enable this read/write bit-field permits the user to enable or disable the one second interrupt, within the XRT72L13. if this interrupt is enabled then the XRT72L13 will generate interrupts to the micropro- cessor/microcontroller at one-second intervals. setting this bit-field to 0 disables the one second interrupt. conversely, setting this bit-field to 1 en- ables the one second interrupt. 3.3.2.6 block interrupt status register bit 7 - rx ds3 interrupt status this read-only bit-field indicates whether or not a receive ds3 framer related interrupt has been re- quested and is awaiting service. if this bit-field is set to 0, then there are no receive ds3 framer related interrupts awaiting service. conversely, if this bit-field is set to 1, then there is at least one receive ds3 framer related interrupt, awaiting service. bit 4 - m13 multiplexer interrupt status this read-only bit-field indicates whether or not an m13 multiplexer related interrupt has been request- ed and is awaiting service. if this bit-field is set to 0, then there are no m13 multiplexer related interrupts awaiting service. con- versely, if this bit-field is set to 1, then there is at least one m13 multiplexer related interrupt, awaiting service. bit 1 - tx ds3 interrupt status this read-only bit-field indicates whether or not a transmit ds3 framer related interrupt has been re- quested and is awaiting service. block interrupt status register (address = 0x05) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx ds3 interrupt status not used not used m13 interrupt status not used not used tx ds3 interrupt status one second interrupt status r/o r/o r/o r/o r/o r/o r/o rur 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 194 if this bit-field is set to 0, then there are no transmit ds3 framer related interrupts awaiting service. conversely, if this bit-field is set to 1, then there is at least one transmit ds3 framer related interrupt, awaiting service. bit 0 - one second interrupt status this reset-upon-read bit-field indicates whether or not a one second interrupt has been requested and is awaiting service. if this bit-field is set to 0, then the one second in- terrupt is not awaiting service. conversely, if this bit- field is set to 1, then the one second interrupt is awaiting service. n ote : this bit-field will be cleared immediately after the microprocessor/microcontroller has read this register. 3.3.2.7 rxfifo control register bit 1 - rxfifo32 - 32/64 operating depth select this read/write bit-field permits the user to config- ure the operating depth of the de-jitter fifo to be ei- ther 32 or 64 bits. setting this bit-field to 0 configures the operating depth of the de-jitter fifo to be 64 bits. setting this bit-field to 1 configures the operating depth of the de-jitter fifo to be 32 bits. n ote : this bit-field is ignored if the de-jitter fifo is dis- abled. bit 0 - rxfif0 enable this read/write bit-field permits the user to enable or disable the de-jitter fifo within the XRT72L13. setting this bit-field to 0 disables the de-jitter fifo. setting this bit-field to 1 enables the de-jitter fifo 3.3.2.8 m23 configuration register bit 6 - payload hdlc controller enable this bit-field along with m13 disable (bit 4) pemits the user to specify whether the XRT72L13 m13 de- vice is to operate in either of the following modes. ? the m13/channelized mode ? the ds3 clear channel framer mode ? the high speed hdlc controller mode. the relationship between these two bit-fields and the resulting operating operating mode of the XRT72L13 m13 device is tabulated below. rxfifo control register (address = 0x06) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used not used not used not used not used not used rxfifo32 rxfifo enable r/o r/o r/o r/o r/o r/o r/w r/w 00000000 m23 configuration register (address = 0x07) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used payload hdlc controller enable rxds1clk gapped (crc-32) m13 disable m13 loopback/ (remote loopback) tr i b u t a r y polarity m23 loopback code[1] m23 loopback code[0] r/o r/o r/o r/o r/o r/o r/o rur 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 195 bit 5 - rxds1clk gapped (crc-32) select the exact functionality of this bit-field depends upon whether the user is operating the XRT72L13 in the m13-channelized or in the high speed hdlc con- troller mode. m13-channelized mode - rxds1 gapped clock select in the m13-channelized mode, then this bit-field permits the user to either enable or disable the 28 digital pll blocks within the XRT72L13 m13 device. setting this bit-field to 0 enables all 28 of these dig- ital pll blocks. in this mode, all 28 (or 21) of the rxds1clk and rxds1data output signals will be smoothed by an internal digital pll. this permits the user to interface the receive ds1/e1 output inter- face to an external ds1 or e1 liu ic. setting this bit-field to 1 disables all 28 of these dig- ital pll blocks. in this mode, all 28 (or 21) of the rxds1clk and rxds1data output signals will not be smoothed by an internal digital pll, and will con- tain gaps. hdlc controller mode - crc16/32 select in the high speed hdlc controller mode, this bit- field permits the user to configure the XRT72L13 to compute and verify a crc-16 or crc-32 value within the hdlc frame. setting this bit-field to 0 configures the XRT72L13 to compute and verify a crc-16 value in each hdlc frame. setting this bit-field to 1 configures the XRT72L13 to compute and verify a crc-32 value in each hdlc frame. bit 4 - m13 disable this bit-field along with payload hdlc controller en- able (bit 6) pemits the user to specify whether the XRT72L13 m13 device is to operate in either of the following modes. ? the m13/channelized mode ? the ds3 clear channel framer mode ? the high speed hdlc controller mode. the relationship between these two bit-fields and the resulting operating operating mode of the XRT72L13 m13 device is tabulated below. bit 3 - m13loopback/remote loopback the exact functionality of this bit-field depends upon whether the user is operating the XRT72L13 in the m13-channelized or in the high speed hdlc con- troller mode. m13-channelized mode - m13 loopback select if the XRT72L13 is operating in the m13 channel- ized mode, then this bit-field functions as the m13 loopback select bit-field. setting this bit-field to 0 disables the m13 loop- back mode. in this mode, the receive m13 block will accept data from the rx ds3 framer block (normal operation). p ayload hdlc c ontroller e nable m13 d isable resulting o perating m ode 0 0 m13/ channelized mode 0 1 ds3 clear channel framer mode 1 0 m13/ channelized mode 1 1 high speed hdlc controller mode p ayload hdlc c ontroller e nable m13 d isable resulting o perating m ode 00m13/ channelized mode 0 1 ds3 clear channel framer mode 10m13/ channelized mode 1 1 high speed hdlc controller mode XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 196 setting this bit-field to 1 enables the m13 loop- back mode. in this mode, the receive m13 block ac- cepts data from the transmit m13 block (the trans- mit and receive ds3 framer blocks are bypassed). high speed hdlc controller mode - remote loopback select if the XRT72L13 is operating in the high speed hdlc controller mode, then this bit-field functions as the remote loopback select bit-field. setting this bit-field to 0 disables the remote loop- back mode. setting this bit-field to 1 enables the remote loop- back mode. bit 2 - tributary polarity this read/write bit-field permits the user to select the clock edge at which (a) the XRT72L13 m13 de- vice will sample and latch the transmit ds1/e1 and transmit hdlc data, and (b) the XRT72L13 will out- put the receive ds1/e1 and receive hdlc data. setting this bit-field to 0 configures the XRT72L13 m13 device to (a) sample and latch the transmit ds1/e1 and transmit hdlc data on the rising edge of the appropriate clock signal; and (b) to output the receive ds1/e1 and receive hdlc data on the rising edge of the appropriate clock signal. setting this bit-field to 1 configures the XRT72L13 m13 device to (a) sample and latch the transmit ds1/e1 and transmit hdlc data on the falling edge of the appropriate clock signal; and (b) to output the receive ds1/e1 and receive hdlc data on the falling edge of the appropriate clock signal. bits 1 and 0 - m23lbcode[1, 0] n otes : these two read/write bits permit the user to define which c-bit pattern (in the inbound ds3 data stream) will function as the loopback command. these reg- ister bits are only used if the XRT72L13 m13 device is oper- ating in the m13 framing format. these register bits are ignored if the XRT72L13 m13 device is operating in the c- bit parity framing format. the following table related the contents of these two bit-fields to the m23 loopback code. a more detailed description of these loopback codes will be presented in section _. 3.3.2.9 m23 ds3 ais register bits 6 thru 0 - txds2 ais channel[6:0] these seven (7) read/write bit-fields permits the user to specify which outbound ds2 channel will transmit an ais (all ones) pattern. for example, setting bit 5 (within this register) to 1 configures the XRT72L13 m13 device to transmit an ais pattern via the outbound (transmit) ds2 chan- nel 5. in this mode, the content of the lower tributary t able 9: m23l b c ode [1] m23 lb c ode [0] resulting m 23 loopback code 0 0 cj1 = cj2 = *cj3 0 1 cj1 = *cj2 = cj3 1 0 *cj1 = cj2 = cj3 1 1 cj1 = cj2 = *cj3 m23 tx ds2 ais register (address = 0x08) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txds2 ais channel 6 txds2 ais channel 5 txds2 ais channel 4 txds2 ais channel 3 txds2 ais channel 2 txds2 ais channel 1 txds2 ais channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 197 txds1/e1 signals will be over-written by this ais pattern. setting bit 5 to 0 configures the transmit ds2 channel 5 to carry normal traffic (as determined by the lower ds1 or e1 tributaries). 3.3.2.10 m23 request loopback register bits 6 thru 0 - ds2 loopback request channel [6:0] these seven (7) read/write bit-field permits the us- er to request that the remote terminal equipment configure one of their ds2 channels to operate in the remote loopback mode. setting any one of these bit-fields to 1 will cause the XRT72L13 m13 device to insert a ds2 remote loopback command request (for the corresponding ds2 channel) to be inserted into the outbound ds3 data stream. the remote terminal equipment should respond by executing the appropriate loop- back command. for example, setting bit 5 (within this register) will cause the XRT72L13 m13 device to insert the chan- nel 5 ds2 remote loopback command register in- to the outbound ds3 data stream. the remote ter- minal equipment will be expected to respond by con- figuring ds2 channel 5, into the remote loopback mode. n ote : this registert is only active if the XRT72L13 m13 device has been configured to operate in the m13/chan- nelized mode. 3.3.2.11 m23 loopback activation register bits 6 thru 0 - ds2 loopback activation channel [6:0] these seven (7) read/write bit-fields permit the us- er to configure any of the seven ds2 channels into the remote loopback mode. setting any one of these bit-fields to 1 will cause the corresponding ds2 channel to operate in the re- mote loopback mode. setting any one of these bit-fields to 0 will cause the corresponding ds2 channel to terminate remote loopback mode operation. 3.3.2.12 m23 rxais register m23 request loopback register (address = 0x09) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ds2 loopback request channel 6 ds2 loopback request channel 5 ds2 loopback request channel 4 ds2 loopback request channel 3 ds2 loopback request channel 2 ds2 loopback request channel 1 ds2 loopback request channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 m23 loopback activation register (address = 0x0a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used ds2 loopback activation channel 6 ds2 loopback activation channel 5 ds2 loopback activation channel 4 ds2 loopback activation channel 3 ds2 loopback activation channel 2 ds2 loopback activation channel 1 ds2 loopback activation channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 198 bits 6 thru 0 - rxds2 ais channel [6:0] these seven (7) read/write bit-fields permits the user to specify which inbound ds2 channel (which is demultiplexed from the inbound ds3 channel) will carry an ais (all ones) pattern. for example, setting bit 5 (within this register) to 1 configures the XRT72L13 m13 device to overwrite the contents of the de-multiplexed ds2 channel (corre- sponding to channel 5) with the ais (all ones) pat- tern. setting bit 5 to 0 configures the receive ds2 channel 5 to carry normal traffic (as de-multiplexed from the inbound ds3 data stream). 3.3.2.13 ds3 test register bit 6 - rx payload clock enable this read/write bit-field permits the user to config- ure the receive payload data output interface (of the XRT72L13 m13 device) to generate either (a) a gapped-serial clock signal or (b) an ungapped-serial clock, along with an rxohind output signal. setting this bit-field to 0 configures the XRT72L13 to generate an ungapped (44.736mhz) clock sjgnal via the rxclk output pin, and to pulse the rxohind output pin, coincident with an overhead bit being out- put via the rxser output pin. setting this bit-field to 1 configures the XRT72L13 to generate a gapped clock signal (e.g., a clock edge for each payload bit) via the rxohind output pin. n ote : this feature is only applicable if the XRT72L13 has been configured to operate in the ds3 clear channel framer mode. bit 5 - tx payload clock enable this read/write bit-field permits the user to config- ure the transmit payload data input interface (or the XRT72L13 m13 device) to generate either (a) a gapped-serial clock signal or (b) an ungapped-serial clock, along with the txohind output signal. setting this bit-field to 0 configurese the XRT72L13 to accept an ungapped clock (44.736mhz) signal via the txinclk input pin (or to output an ungapped clock signal via the rxoutclk output pin). further, in this mode, the XRT72L13 will pulse the txohind output pin one bit period prior to the processing of an overhead bit. setting this bit-field to 1 configures the XRT72L13 to generate a gapped clock signal (e.g., a clock edge for each payload bit) via the txohind output pin. n ote : this feature is only applicable if the XRT72L13 has been configured to operate in the ds3 clear channel framer mode. bit 4 - rx prbs lock indicator this read-only bit-field indicates whether or not the prbs checker/receiver has acquired prbs lock with the payload portion of the inbound ds3 data stream. m23 rx ds2 ais register (address = 0x0b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxds2 ais channel 6 rxds2 ais channel 5 rxds2 ais channel 4 rxds2 ais channel 3 rxds2 ais channel 2 rxds2 ais channel 1 rxds2 ais channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 ds3 test register (address = 0x0c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rx payload clock enable tx payload clock enable rx prbs lock indicator rx prbs enable tx prbs enable rx ds3 bypass tx ds3 bypass r/o r/w r/w r/o r/w r/w r/w r/w 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 199 if this bit-field is set to 0 then the prbs checker/ receiver has not acquired prbs lock with the payload portion of the inbound ds3 data stream. conversely, if this bit-field is set to 1, then the prbs checker/receiver has acquired prbs lock (or pattern sync) with the payload portion of the in- bound ds3 data stream. n ote : the contents of this bit-field are valid only if the prbs checker/receiver is enabled. bit 3 - rx prbs enable this read/write bit-field permits the user to enable the prbs checker/receiver block within the XRT72L13 m13 device. setting this bit-field to 0 disables the prbs check- er/receiver block. setting this bit-field to 1 enables the prbs check- er/receiver block. bit 2 - tx prbs enable this read/write bit-field permits the user to enable or disable the prbs generator/transmitter block within the XRT72L13 m13 device. setting this bit-field to 0 disables the prbs gener- ator/transmitter block. setting this bit-field to 1 enables the prbs genera- tor/transmitter block. bit 1 - rxds3 bypass to be defined in the next revision bit 0 - txds3 bypass to be defined in the next revision 3.3.2.14 rx ds3 configuration and status reg- siter bit 7 - rx ais (receive ais pattern) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is currently receiving an ais pattern or not. the XRT72L13 will set this bit-field to 0 if it is not currently detecting an ais pattern in the incoming da- ta stream. conversely, the XRT72L13 will set this bit- field to 1 if it is currently receiving an ais pattern in the incoming data stream. n ote : for a detailed discussion on the ais pattern please see section _. bit 6 - rx los (receive los condition) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is currently declaring an los (loss of signal) condition of the incoming ds3 data stream. if this bit-field is set to 0, then the receive ds3 framer block (within the chip) is currently not declar- ing an los condition. if this bit-field is set to 1, then the receive ds3 framer block (within the chip) is currently declaring an los condition. n ote : for more information on the los declaration crite- ria, please see section _. bit 5 - rx idle (receive idle pattern) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is currently detecting the idle pattern in the incoming ds3 data stream. if this bit-field is set to 0, then the receive ds3 framer block (within the chip) is currently not detect- ing the idle pattern. if this bit-field is set to 1, then the receive ds3 framer block (within the chip) is currently detecting the idle pattern. n ote : for more information about the idle pattern, please see section _. bit 4 - rx oof (receive out-of-frame) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 rx ds3 configuration and status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx ais rx los rx idle rx oof reserved framing on parity fsync algo msync algo r/o r/o r/o r/o r/w r/w r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 200 m13 device) is currently declaring an oof (out of frame) condition. if this bit-field is set to 0, then the receive ds3 framer block (of the chip) is currently not declaring the oof condition. if this bit-field is set to 1, then the receive ds3 framer block is currently declaring the oof condi- tion. n ote : for more information on the oof and in-frame declaration criteria (for ds3) please see section _. bit 2 - framing on parity on/off select this read/write bit-field permits the user to require that the receive ds3 framer block include p-bit verification as a condition for declaring itself in- frame, during frame acquisition. this feature also imposes an additional frame main- tenance requirement on the receive ds3 framer block. in particular, if this additional requirement is implemented, the receive ds3 framer block will perform a frame search if it detects p-bit errors in at least 2 out of 5 ds3 frames. setting this bit-field to 1 imposes this additional re- quirement. conversely, setting this bit-field to 0 configures the receive ds3 framer block to waive this require- ment. n ote : for more information on framing with parity, please see section _. bit 1 - fsync algo(rithm) select this read/write bit-field, in conjunction with bits 0 and 2 of this register, allows the user to completely define the frame maintenance criteria of the re- ceive ds3 framer block (within the chip). this par- ticular bit-field permits the user to define the frame maintenance criteria, as it applies to f-bits. setting this bit-field to 0 configures the receive ds3 framer block to declare an oof (out of frame condition) if it determines that 6 out of the last 16 f-bits are in error. setting this bit-field to 1 configures the receive ds3 framer block to declare an oof (out of frame condition) if it determines that 3 out of the last 16 f-bits are in error. bit 0 - msync algo(rithm) select this read/write bit-field, in conjunction with bits 1 and 2 of this register, allows the user to completely define the frame maintenance criteria of the re- ceive ds3 framer block (within the chip). this par- ticular bit-field permits the user to define the frame maintenance criteria, as it applies to m-bits. setting this bit-field to 0 configures the receive ds3 framer block to ignore the occurrence of m-bit errors. setting this bit-field to 1 configures the receive ds3 framer block to declare an oof condition if it determines that 3 out of 4 m-bits are in error. 3.3.2.15 rxds3 status register bit 4 - rxferf (far-end receive failure) indicator this read-only bit-field indicates whether or not the receive ds3 framer block (within the XRT72L13 m13 device) is declaring a ferf (far-end receive failure) condition. if this bit-field is set to 0, then the receive ds3 framer block (of the chip) is currently not declaring an los condition. conversely, if this bit-field is set to 1, then the re- ceive ds3 framer block is currently declaring an los condition. n ote : for more information how the receive ds3 framer block declares a ferf condition, please see section _. bit 3 - rxaic (application identification channel) indi- cator this read-only bit-field reflects the value of the aic bit-field, within the incoming ds3 frames, as detected by the receive ds3 framer block. rx ds3 status register (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used not used not used rxferf rxaic rxfebe[2] rxfebe[1] rxfebe[0] r/o r/w r/w r/o r/o r/o r/o r/o 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 201 this bit-field is set to 1 if the incoming ds3 data stream is determined to be in the c-bit parity format (aic bit = 1) for at least 63 consecutive frames. this bit-field is set to 0 if the incoming ds3 data stream is determined to be in the m13 format (aic bit = 0). bits 2 thru 0 - rxfebe[2:0] these read-only bit-fields reflect the febe (far- end block error) value, within the most recently re- ceived ds3 frame. if these bit-fields are set to 111, then it indicates that the remote receiving terminal is receiving ds3 frames in an un-erred manner. conversely, if these bit-fields are set to any value oth- er than 111, then it indicates that the remote re- ceiving terminal has detected framing or parity bit errors in the ds3 frames that it is receiving. n ote : for more information on febe (far-end-block error), please see section _. 3.3.2.16 rxds3 interrupt enable register bit 7 - detection of cp-bit error interrupt enable this read/write bit-field permits the user to enable or disable the detection of cp-bit error interrupt. setting this bit-field to 0 disables the detection of cp-bit error interrupt. setting this bit-field to 1 enables the detection of cp-bit error interrupt. bit 6 - change in los condition interrupt enable this read/write bit-field permits the user to enable or disable the change in los condition interrupt. setting this bit-field to 0 disables the change in los condition interrupt. setting this bit-field to 1 enables the change in los condition interrupt. bit 5 - change in ais condition interrupt enable this read/write bit-field permits the user to enable or disable the change in ais condition interrupt. setting this bit-field to 0 disables the change in ais condition interrupt. setting this bit-field to 1 enables the change in ais condition interrupt. bit 4 - change in idle pattern condition interrupt enable this read/write bit-field permits the user to enable or disable the change in idle pattern condition in- terrupt. setting this bit-field to 0 disables the change in idle pattern condition interrupt. setting this bit-field to 1 enables the change in idle pattern condition interrupt. bit 3 - change in ferf condition interrupt enable this read/write bit-field permits the user to enable or disable the change in ferf condition interrupt. setting this bit-field to 0 disables the change in ferf condition interrupt. setting this bit-field to 1 enables the change in ferf condition interrupt. bit 2 - change in aic state interrupt enable this read/write bit-field permits the user to enable or disable the change in aic state interrupt. setting this bit-field to 0 disables the change in aic state interrupt. setting this bit-field to 1 enables the change in aic state interrupt. bit 1 - change in oof condition interrupt enable rx ds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 detection of cp-bit error interrupt enable change in los condition interrupt enable change in ais condition interrupt enable change in idle pattern interrupt enable change in ferf condition interrupt enable change in aic state interrupt enable change in oof condition interrupt enable detection of p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 202 this read/write bit-field permits the user to enable or disable the change in oof condition interrupt. setting this bit-field to 0 disables the change in oof condition interrupt. setting this bit-field to 1 enables the change in oof condition interrupt. bit 0 - detection of p-bit error interrupt enable this read/write bit-field permits the user to enable or disable the detection of p-bit error interrupt. setting this bit-field to 0 disables the detection of p-bit error interrupt. setting this bit-field to 1 enables the detection of p- bit error interrupt. 3.3.2.17 rxds3 interrupt status register bit 7 - detection of cp-bit error interrupt status this reset-upon-read bit-field indicates whether or not the receive ds3 framer block has detected a cp-bit error in the inbound ds3 data stream, since the last time this register was read. this bit-field will be 0 if the detection of cp-bit er- ror interrupt has not occured since the last read of this register. this bit-field will be 1 if the interrupt has occurred since the last read of this register. bit 6 - change in los (loss of signal) condition interrupt status this reset-upon-read bit-field will be set to 1 if the receive ds3 framer block has detected a change in los condition, since the last time this register was read. if the change in los condition interrupt is enabled, then this bit-field will be asserted under either of the following conditions. a. when the receive ds3 framer block detects the occurrence of an los condition (e.g., the occurrence of 180 consecutive spaces in the incoming ds3 data stream), and b. when the receive ds3 framer block detects the end of an los condition (e.g., when the receive ds3 framer block detects at least 60 mark pulses in the last 180 bit periods). the microprocessor/microcontroller can determine the state of the los condition by reading bit 6, within the rx ds3 configuration and status register (ad- dress location = 0x10). n ote : for more information about the los condition please see section _. bit 5 - change in ais (alarm indication signal) condition interrupt status this reset-upon-read bit-field will be set to 1 if the receive ds3 framer block has detected a change in ais condition, since the last time this reg- ister was read. if the change in ais condition inter- rupt is enabled, then this bit-field will be asserted un- der either of the following conditions. a. when the receive ds3 framer block first detects an ais condition in the inbound ds3 data stream. b. when the receive ds3 framer block has detected the end of an ais condition. the microprocessor/microcontroller can determine the state of the ais condition by reading bit 7, within the rx ds3 configuration and status register (ad- dress location = 0x10). n ote : for more information about the ais condition please see section _. bit 4 - change in idle pattern condition interrupt status this reset-upon-read bit-field is set to 1 when the receive ds3 framer block detects a change in idle condition in the incoming ds3 data stream. specifi- rx ds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 detection of cp-bit error interrupt status change in los condition interrupt status change in ais condition interrupt status change in idle pattern condition interrupt status change in ferf condition interrupt status change in aic state interrupt status change in oof condition interrupt status detection of p-bit error interrupt status rurrurrurrurrurrurrurrur 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 203 cally, the receive ds3 framer block will assert this bit-field under either of the following two conditions. a. when the receive ds3 framer block initially detects the idle pattern in the inbound ds3 data stream. b. when the receive ds3 framer block ceases to detect the idle pattern in the inbound ds3 data stream. the microprocessor/microcontroller can determine the state of the idle pattern condition by reading bit 5, within the rx ds3 configuration and status regis- ter (address location = 0x10). n ote : for more information about the idle pattern please see section _. bit 3 - change in ferf condition interrupt status this reset-upon-read bit-field is set to 1 if the receive ds3 framer block (within the XRT72L13 m13 device) has detected a change in the ferf condition, since the last time this register was read. this bit-field will be asserted under either of the fol- lowing conditions. a. when the receive ds3 framer block first detects the occurrence of a ferf condition in the inbound ds3 data stream (e.g., all x-bits are set to 0). b. when the receive ds3 framer block no longer detects the ferf condition in the inbound ds3 data stream (e.g., all x-bits are set to 1). the microprocessor/microcontroller can determine the state of the of the ferf condition by reading bit 4 within the rx ds3 status register (address loca- tion = 0x11). n ote : for more information about the ferf condition, please see section _. bit 2 - change in aic state interrupt status this reset-upon-read bit-field is set to 1 if the aic bit-field, within the incoming ds3 data stream, has changed state since the last read of this register. the microprocessor/microcontroller can determine the state of the aic bit-field by reading bit 3, within the rx ds3 status register (address location = 0x11). n ote : for more information on this interrupt condition, please see section _. bit 1 - change in oof condition interrupt status the reset-upon-read bit-field is set to 1 if the receive ds3 framer block (within the XRT72L13) has detected a change in the out-of-frame (oof) condition, since the last time this register was read. this bit-field will be asserted under either of the fol- lowing conditions. a. when the receive ds3 framer block has detected the appropriate condition to declare an oof condition. b. when the receive ds3 framer block has tran- sitioned from the oof condition (frame acquisi- tion mode). the microprocessor/microcontroller can detemine the state of the oof condition by reading bit 4 within the rx ds3 configuration and status register (ad- dress location = 0x10). n ote : for more information about the oof condition, please see section _. bit 0 - detection of p-bit error interrupt status this reset-upon-read bit-field indicates whether or not the detection of p-bit error interrupt has oc- curred since the last read of this register. this bit-field will be 0 if the receive ds3 framer block (within the XRT72L13 m13 device) has not de- tected a p-bit error since the last read of this register. conversely, this bit-field will be 1 if the receive ds3 framer block (within the XRT72L13 m13 de- vice) has detected a p-bit error since the last read of this register. 3.3.2.18 rxds3 sync detect register bit 1 - f algorithm bit 0 - one and only one rx ds3 sync detect register (address = 0x14) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used not used not used reserved reserved reserved f algorithm one and only one r/o r/o r/o r/o r/o r/o r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 204 3.3.2.19 rxds3 feac register this "read/write" register contains the latest 6-bit feac code that has been "validated" by the receive feac processor. the contents of this register will be cleared if the previously "validated" code has been "removed" by the feac processor. 3.3.2.20 rxds3 feac interrupt enable/status register bit 4 - feac valid this "read only" bit is set to "1" when an incoming feac message code has been validated by the re- ceive ds3 framer. this bit is cleared to "0" when the feac code is removed. n ote : for more information on the role of this bit-field and the receive feac processor, please see section _. bit 3 - rxfeac remove interrupt enable this "read/write" bit-field allows the user to enable/ disable the "rxfeac removal" interrupt. writing a "1" to this bit enables this interrupt. likewise, writing a "0" to this bit-field disables this interrupt. n ote : for more information on the role of this bit-field and the receive feac processor, please see section _. bit 2 - rxfeac remove interrupt status a "1" in this "read only" bit-field indicates that the last "validated" feac message has now been re- moved by the receive feac processor. the re- ceive feac processor will remove a validated feac message if 3 out of the last 10 received feac mes- sages differ from the latest valid feac message. n ote : for more information on this bit-field and the receive feac processor, please see section _. bit 1 - rxfeac valid interrupt enable this "read/write" bit-field allows the user to enable/ disable the "rx feac valid" interrupt. writing a "1" to this bit-field enables this interrupt. whereas, writing a "0" disables this interrupt. the value of this bit-field is "0" following power up or reset. n ote : for more information on this bit-field and the receive feac processor, please see section _. bit 0 - rxfeac valid interrupt status a "1" in this "read only" bit-field indicates that a new- ly received feac message has been validated by the receive feac processor. n ote : for more information on this bit-field and the receive feac processor, please see section _. 3.3.2.21 rxds3 lapd control register rxds3 feac register (address = 0x16) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxfeac[5:0] not used r/o r/o r/o r/o r/o r/o r/o r/o 01111110 rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status r/o r/o r/o r/o r/w rur r/w rur 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 205 bit 3 rxlapd any bit 2 rxlapd enable this "read/write" bit-field allows the user to enable or disable the lapd receiver. the lapd receiver must be enabled before it can begin to receive and process any lapd message frames from the incom- ing ds3 data stream. writing a "0" to this bit-field disables the lapd re- ceiver (the default condition). writing a "1" to this bit- field enables the lapd receiver. bit 1 rxlapd (message frame reception com- plete) interrupt enable this "read/write" bit-field allows the user to enable or disable the "lapd message frame reception complete" interrupt. if this interrupt is enabled, then the uni will generate this interrupt to the local p, once the last bit of a lapd message frame has been received and the pmdl message has been extracted and written into the "receive lapd message" buffer. writing a "0" to this bit-field disables this interrupt (the default condition). writing a "1" to this bit-field en- ables this interrupt. bit 0 rxlapd (message reception complete) in- terrupt status this "read-only" bit field indicates whether or not the "lapd message reception complete" interrupt has occurred since the last read of this register. the "lapd message reception complete" interrupt will occur once the lapd receiver has received the last bit of a complete lapd message frame, extracted the pmdl message from this lapd message frame and has written this (pmdl) message frame into the "re- ceive lapd message" buffer. the purpose of this in- terrupt is to notify the local p that the "receive lapd message" buffer contains a new pmdl mes- sage, that needs to be read and/or processed. a "0" in this bit-field indicates that the "lapd mes- sage reception complete" interrupt has not oc- curred since the last read of this register. a "1" in this bit-field indicates that the "lapd message reception complete" interrupt has occurred since the last read of this register. n ote : for more information on the lapd receiver, please see section _. 3.3.2.22 rxds3 lapd status register bit 6 - rxabort (receive abort sequence) this "read-only" bit-field indicates whether or not the lapd receiver has detected the occurrence of an "abort sequence" (e.g., a string of seven or more consecutive "1s") from the "far-end" lapd transmit- ter. a "0" in this bit-field indicates that no "abort-se- quence" has been detected. a "1" in this bit-field indi- cates that the "abort-sequence" has been detected. n ote : for more information on the lapd receiver, please see section _. bits, 5 and 4 - rxlapdtype[1, 0] rxds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd any rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 00000000 rxds3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxabort rxlapdtype[1:0} rxcr type rxfcs error end of message flag present ro ro ro ro ro ro ro ro 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 206 these two "read only" bit-fields combine to indicate the "type" of lapd message frame that has been re- ceived by the lapd receiver. the relationship be- tween these two bit-fields and the lapd message type follows: bit 3 - rxcr (command/response) type this "read only" bit field indicates the value of the c/ r (command/response) bit-field of the latest re- ceived lapd message. bit 2 - rx fcs (frame check sequence) error this "read-only" bit-field indicates whether or not the lapd receiver has detected a "frame check se- quence" (fcs) error in the newly received lapd message frame. a "0" in this bit-field indicates that the fcs for the latest received lapd message frame is correct. a "1" in this bit-field indicates that the fcs for the latest received lapd message frame is incor- rect. n ote : for more information on the lapd receiver, please see section _. bit 1 - end of message this "read-only" bit-field indicates whether or not the lapd receiver has completed its reception of the lat- est incoming lapd message frame. the local p can poll the progress of the lapd receiver by peri- odically reading this bit-field. a "0" in this bit-field indicates that the lapd receiver is still receiving the latest message from the "far end" lapd transmitter. a "1" in this bit-field indicates that the lapd receiver has finished receiving the com- plete lapd message frame. bit 0 - flag present this "read-only" bit-field indicates whether or not the lapd receiver has detected the occurrence of the flag sequence byte (0x7e). a "0" in this bit-field indi- cates that the lapd receiver does not detect the oc- currence of the flag sequence byte. a "1" in this bit- field indicates that the lapd receiver does detect the occurrence of the flag sequence byte. n ote : for more information on the lapd receiver, please see section _. 3.3.2.23 m12 ds2 # 1 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 1. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk3 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_3 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk3 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 1 via the rxds1data3 output pin. setting this bit-field to 1 configures m12 mux # 1 and m12 demux # 1 to be bypassed. setting this bit-field to 0 enables m12 mux # 1 and m12 demux # 1. b it 5b it 4m essage t ype m essage length test signal identification 76 bytes 0 1 idle signal identification 76 bytes cl path identification 76 bytes itu-t path identification 82 bytes m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 207 bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 1 and demux # 1 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 1 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data0 thru txds1data3) and will muitiplex these signals into a ds2 signal. like- wise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multiplex this signal into 4 ds1 signals. these four ds1 sig- nals will be output via the rxds1data0 thru rxds1data3 output pins. setting this bit-field to 1 configures m12 # 1 to support itu-t g.747. in this mode, the m12 mux will accept 3 e1 signals (via txds1data0 thru txds1data2) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data0 thru rxds1data2 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 1 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 3.3.2.24 m12 ds2 # 2 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 1. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk7 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_7 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk7 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 2 via the rxds1data7 output pin. setting this bit-field to 1 configures m12 mux # 1 and m12 demux # 2 to be bypassed. setting this bit-field to 0 enables m12 mux # 1 and m12 demux # 2. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 2 and demux # 2 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 1 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data0 thru txds1data3) and will muitiplex these signals into a ds2 signal. like- wise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multiplex this signal into 4 ds1 signals. these four ds1 sig- nals will be output via the rxds1data0 thru rxds1data3 output pins. m12 ds2 # 2 configuration register (address = 0x1b) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 208 setting this bit-field to 1 configures m12 # 2 to support itu-t g.747. in this mode, the m12 mux will accept 3 e1 signals (via txds1data4 thru txds1data6) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data4 thru rxds1data6 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 2 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 3.3.2.25 m12 ds2 # 3 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 3. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk11 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_11 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk11 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 2 via the rxds1data11 output pin. setting this bit-field to 1 configures m12 mux # 3 and m12 demux # 3 to be bypassed. setting this bit-field to 0 enables m12 mux # 3 and m12 demux # 3. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 3 and demux # 3 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 3 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data8 thru txds1data11) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data8 thru rxds1data11 output pins. setting this bit-field to 1 configures m12 # 3 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data8 thru txds1data10) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data8 thru rxds1data10 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 3 to transmit a ferf (far-end-receive m12 ds2 # 3 configuration register (address = 0x1c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 209 failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 3.3.2.26 m12 ds2 # 4 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 4. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk15 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_15 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk15 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 4 via the rxds1data15 output pin. setting this bit-field to 1 configures m12 mux # 4 and m12 demux # 4 to be bypassed. setting this bit-field to 0 enables m12 mux # 4 and m12 demux # 4. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 4 and demux # 4 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 4 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data12 thru txds1data15) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data12 thru rxds1data15 output pins. setting this bit-field to 1 configures m12 # 4 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data12 thru txds1data14) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data12 thru rxds1data14 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 4 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] m12 ds2 # 4 configuration register (address = 0x1d) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 210 3.3.2.27 m12 ds2 # 5 configuration register ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 5. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk19 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_19 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk19 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 2 via the rxds1data19 output pin. setting this bit-field to 1 configures m12 mux # 5 and m12 demux # 5 to be bypassed. setting this bit-field to 0 enables m12 mux # 5 and m12 demux # 5. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 5 and demux # 5 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 5 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data16 thru txds1data19) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data16 thru rxds1data19 output pins. setting this bit-field to 1 configures m12 # 5 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data16 thru txds1data18) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data16 thru rxds1data18 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 5 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 3.3.2.28 m12 ds2 # 6 configuration register m12 ds2 # 5 configuration register (address = 0x1e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 211 ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 6. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk23 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_23 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk23 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 6 via the rxds1data23 output pin. setting this bit-field to 1 configures m12 mux # 6 and m12 demux # 6 to be bypassed. setting this bit-field to 0 enables m12 mux # 6 and m12 demux # 6. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 6 and demux # 6 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 6 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data20 thru txds1data23) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data20 thru rxds1data23 output pins. setting this bit-field to 1 configures m12 # 6 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data20 thru txds1data22) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data20 thru rxds1data22 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 6 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 3.3.2.29 m12 ds2 # 7 configuration register m12 ds2 # 6 configuration register (address = 0x1f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 212 ) bit 7 - reserved this bit-field must be set to 0, in order for the XRT72L13 m13 device to function properly. bit 6 - reserved this bit-field must be set to 0 in order for the XRT72L13 m13 device to function properly. bit 5 - m12 bypass this read/write bit field permits the user to bypass m12 multiplexer/de-multiplexer # 6. by doing this the following will happen. in the transmit direction ? the XRT72L13 m13 device will accept a ds2 clock signal (6.312mhz) via the txds1clk23 input pin. ? the XRT72L13 m13 device will accept a ds2 sig- nal via the txds1data_23 input pin in the receive direction ? the XRT72L13 m13 device will output a ds2 clock signal (6.312mhz) via the rxds1clk23 output pin. ? XRT72L13 m13 device will output the contents of ds2 channel # 6 via the rxds1data23 output pin. setting this bit-field to 1 configures m12 mux # 6 and m12 demux # 6 to be bypassed. setting this bit-field to 0 enables m12 mux # 6 and m12 demux # 6. bit 4 - m12 g.747 this read/write bit-field permits the user to config- ure m12 mux # 6 and demux # 6 to support either a ds2 signal or an itu-t g.747 signal. setting this bit-field to 0 configures m12 # 6 to sup- port ds2. in this mode, the m12 mux will accept four ds1 signals (via txds1data20 thru txds1data23) and will muitiplex these signals into a ds2 signal. likewise, the m12 demux will accept an incoming ds2 signal (from the m23 demux) and will de-multi- plex this signal into 4 ds1 signals. these four ds1 signals will be output via the rxds1data20 thru rxds1data23 output pins. setting this bit-field to 1 configures m12 # 6 to sup- port itu-t g.747. in this mode, the m12 mux will ac- cept 3 e1 signals (via txds1data20 thru txds1data22) and will multiplex these signals into an itu-t g.747 signal. likewise, the m12 demux will accept an incoming itu-t g.747 signal (from the m23 demux) and will de-multiplexe this signal into 3 e1 signals. these three e1 signals will output via the rxds1data20 thru rxds1data22 output pins. bit 3 - m12g.747 reserved bit 2 - m12 ferf this read/write bit-field permits the user to force m12 mux # 6 to transmit a ferf (far-end-receive failure) indicator to the m23 mux (and in turn to the remote terminal equipment). setting this bit-field to 1 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 0. this signaling will be interpreted (by the remote terminal equipment) as a ferf indicator. settiing this bit-field to 0 configures the m12 mux to set the x-bits (within the outbound ds2 data stream) to 1. this signaling will be interpreted (by the remote terminal equipment) as an indication of no ferf. bits 1 and 0 m12 lb code[1:0] 3.3.2.30 m12 ds2 # 1 ais register m12 ds2 # 7 configuration register (address = 0x20) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 213 ) bit 7 - insert ais rx ds1 channel 3 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 3 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data3 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 6 - insert ais rx ds1 channel 2 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 2 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data2 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 5 - insert ais rx ds1 channel 1 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 1 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data1 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 4 - insert ais rx ds1 channel 0 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 0 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data0 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 3 - insert ais tx ds1 channel 3 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 3 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 3 to be transmitted as received (via the txds1data3 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 2 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 3 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 2 to be transmitted as received (via the txds1data2 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 1 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 1 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 1 to be transmitted as received (via the txds1data1 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 0 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 0 to be overwritten with an all ones pattern. m12 ds2 # 1 ais register (address = 0x21) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 3 insert ais rx ds1 channel 2 insert ais rx ds1 channel 1 insert ais rx ds1 channel 0 insert ais tx ds1 channel 3 insert ais tx ds1 channel 2 insert ais tx ds1 channel 1 insert ais tx ds1 channel 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 214 setting this bit-field to 0 permits the contents of ds1 channel 0 to be transmitted as received (via the txds1data0 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 3.3.2.31 m12 ds2 # 2 ais register ) bit 7 - insert ais rx ds1 channel 7 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 7 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data7 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 6 - insert ais rx ds1 channel 6 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 6 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data6 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 5 - insert ais rx ds1 channel 5 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 5 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data5 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 4 - insert ais rx ds1 channel 4 this read/write bit-field permits the user to config- ure the contents of the inbound ds1 channel 4 to be overwritten with an all ones pattern. setting this bit-field to 0 permits data to be output (via the rxds1data4 output pin, as demultiplexed via the inbound ds2 and ds3 data streams. setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 3 - insert ais tx ds1 channel 7 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 7 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 7 to be transmitted as received (via the txds1data7 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 2 - insert ais tx ds1 channel 6 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 6 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 6 to be transmitted as received (via the txds1data2 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 1 - insert ais tx ds1 channel 5 m12 ds2 # 2 ais register (address = 0x21) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 7 insert ais rx ds1 channel 6 insert ais rx ds1 channel 5 insert ais rx ds1 channel 4 insert ais tx ds1 channel 7 insert ais tx ds1 channel 6 insert ais tx ds1 channel 5 insert ais tx ds1 channel 4 r/w r/w r/w r/w r/w r/w r/w r/w 00000111 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 215 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 5 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 5 to be transmitted as received (via the txds1data1 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). bit 0 - insert ais tx ds1 channel 4 this read/write bit-field permits the user to config- ure the contents of the output ds1 channel 4 to be overwritten with an all ones pattern. setting this bit-field to 0 permits the contents of ds1 channel 4 to be transmitted as received (via the txds1data0 input pin). setting this bit-field to 1 configures the XRT72L13 m13 device to overwrite this data with an ais (all ones pattern). 3.3.2.32 m12 ds2 # 3 ais register 3.3.2.33 m12 ds2 # 4 ais register 3.3.2.34 m12 ds2 # 5 ais register 3.3.2.35 m12 ds2 # 6 ais register 3.3.2.36 m12 ds2 # 7 ais register 3.3.2.37 m12 ds2 # 1 loopback request regis- ter 3.3.2.38 m12 ds2 # 2 loopback request regis- ter 3.3.2.39 m12 ds2 # 3 loopback request regis- ter 3.3.2.40 m12 ds2 # 4 loopback request regis- ter 3.3.2.41 m12 ds2 # 5 loopback request regis- ter 3.3.2.42 m12 ds2 # 6 loopback request regis- ter 3.3.2.43 m12 ds2 # 7 loopback request regis- ter 3.3.2.44 tx ds3 configuration register) ) bit 7 - tx yellow alarm this "read/write" bit-field allows the local p to com- mand the transmit ds3 framer to transmit a "yellow alarm" (e.g., x bits are all "0") in the outgoing ds3 data stream. writing a "0" to this bit-field disables this feature (the default condition). in this condition, the x-bits in the out-bound ds3 frame, are internally generated (based upon receiver conditions). writing a "1" to this bit-field invokes this command. in this condition, the transmit ds3 framer will override the internally-generated x-bits and force all of the x- bits of each outbound ds3 frame to "0". n ote : for more information in this feature, please see sec- tion _. n ote : this bit-setting is ignored if bits 3, 4 or 5 (within this register) are set to "1". bit 6 - tx x-bit (force x bits to "1") this "read/write" bit-field allows the user to com- mand the transmit ds3 framer to force all of the x- bits, in the outbound ds3 frames, to "1". writing a "0" to this bit-field disables this feature (the default condition). in this case, the transmit ds3 tx ds3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 tx yellow alarm tx x bits tx idle tx ais tx los ferf on los ferf on oof ferf on ais r/w r/w r/w r/w r/w r/w r/w r/w 00000111 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 216 framer will generate x-bits based upon the receive conditions. writing a "1" to this bit-field invokes this command. in this case, the transmit ds3 framer will overwrite the internally-generated x-bits and set them all to "1". n ote : for more information on this feature, please see section _. n ote : this bit-setting is ignored if bits 3, 4, 5, or 7 (within this register) are set to "1". bit 5 - tx idle (pattern) this "read/write" bit-field allows the user to com- mand the transmit ds3 framer to transmit the "idle condition" pattern. if the user invokes this com- mand, then the transmit ds3 framer will force the outbound ds3 frames to have the following patterns. ? valid m-bits, f-bits and p-bits ? the three cp-bits (f-frame #3) are "0" ? the x-bits are set to "1" ? a repeating "1100..." pattern in written into the pay- load portion of the ds3 frames. writing a "1" to this bit-field invokes this command. writing a "0" allows the transmit ds3 framer to func- tion normally (e.g., the transmit ds3 framer will transmit its payload and internally generated over- head bits). n ote : for more information on this feature, please see section _. n ote : this bit-setting is ignored if bits 3 or 4 (within this register) are set to "1". bit 4 - tx ais (pattern) this "read/write" bit-field allows the user to com- mand the transmit ds3 framer to transmit an "ais" pattern. if the user invokes this command, then the transmit ds3 framer will force the outbound ds3 frames to have the following patterns. ? valid m-bits, f-bits, and p-bits ? all c-bits are set to '0' ? all x-bits are set to '1' ? a repeating '1010...' pattern is written into the pay- load of the ds3 frames. writing a "1' to this bit-field invokes this command. writing a "0" allows the transmit ds3 framer to func- tion normally (e.g., the transmit ds3 framer will transmit its payload and internally generated over- head bits). n ote : for more information on this feature, please see section _. bit 3 - tx los (loss of signal) this "read/write" bit-field allows the user to com- mand the transmit ds3 framer to simulate an "los condition". if the user invokes this command, then the transmit ds3 framer will stop sending "mark" pulses out on the line; and will transmit an all-zero pattern. writing a '0' to this bit-field disables (or shuts off) this feature, thereby allowing internally generated ds3 frames to be generated and transmitted over the line. writing a '1' to this bit-field invokes this command, causing the transmit ds3 framing to generate an all '0' pattern. n ote : for more information on this feature, please see section _. bit 2 - ferf on los this "read/write" bit-field allows the user to config- ure the transmit ds3 framer to generate a "yellow alarm" if the near-end receive ds3 framer detects a "los" (loss of signal) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section _. bit 1 - ferf on oof this "read/write" bit-field allows the user to config- ure the transmit ds3 framer to generate a "yellow alarm" if the near-end receive ds3 framer detects an "oof (out-of-frame) condition". writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section _. bit 0 - ferf on ais this "read/write" bit-field allows the user to config- ure the transmit ds3 framer to generate a "yellow alarm" if the near-end receive ds3 framer detects an ais (alarm indication signal) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. n ote : for more information on this feature, please see section _. 3.3.2.45 txds3 feac configuration and status register ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 217 ) bit 4 - tx feac interrupt enable this read-write bit-field permits the user to enable or disable the transmit feac interrupt. setting this bit-field to 0 disables this interrupt. conversely, setting this bit-field to 1 enables this in- terrupt. bit 3 - txfeac interrupt status this "read-only" bit-field indicates whether or not the "feac message transmission complete" interrupt has occurred since the last read of this register. this interrupt will occur once the transmit feac proces- sor has finished its 10th transmission of the 16 bit feac message (6 bit feac code word + 10 framing bits). the purpose of this interrupt is to let the local p know that the transmit feac processor has com- pleted its transmission of its latest feac message and is now ready to transmit another feac message. if this bit-field is "0", then the "feac message trans- mission complete" interrupt has not occurred since the last read of this register. if this bit-field is "1", then the "feac message trans- mission complete" interrupt has occurred since the last read of this register. n ote : for more information on the transmit feac proces- sor, please see section _. bit 2 - txfeac enable this "read/write" bit-field allows the user to enable or disable the transmit feac processor. the trans- mit feac processor will not function until it has been enabled. writing a "0" to this bit-field disables the transmit feac processor. writing a "1" to this bit-field en- ables the transmit feac processor. bit 1 - txfeac go this bit-field allows the user to invoke the "transmit feac message" command. once this command has been invoked, the transmit feac processor will do the following: ? encapsulate the 6 bit feac code word, from the tx ds3 feac register (address = 1dh) into a 16 bit feac message ? serially transmit this 16-bit feac message to the far-end receiver via the "outbound" ds3 data- stream, 10 consecutive times. n ote : for more information on the transmit feac proces- sor, please see section _. bit 0 - txfeac busy this "read-only" bit-field allows the local p to "poll" and determine if the transmit feac processor has completed its 10th transmission of the 16-bit feac message. this bit-field will contain a "1", if the trans- mit feac processor is still transmitting the feac message. this bit-field will toggle to "0", once the transmit feac processor has completed its 10th transmission of the feac message. n ote : for more information on the transmit feac proces- sor, please see section _. 3.3.2.46 txds3 feac register ) transmit ds3 configuration & status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used tx feac interrupt enable txfeac interrupt status txfeac enable txfeac txfeac busy ro ro ro r/w rur r/w r/w ro 00000000 tx ds3 feac regiser (address = 0x32) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txfeac[5:0] not used ro r/wr/wr/wr/wr/wr/w ro 01111110 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 218 this register contains a six (6) bit "read/write" field that allows the user to write in the six-bit feac code word, that he/she wishes to transmit to the "far end receive feac processor", via the outgoing ds3 data stream. the transmit feac processor will encapsu- late this six-bit code into a 16-bit feac message, and will proceed to transmit this message to the "far end receiver" via the feac bit-field within each out-going ds3 frame. n ote : for more information on the operation of the trans- mit feac processor, please see section _. 3.3.2.47 txds3 lapd configuration register ) bit 3 - auto retransmit this "read/write" bit-field allows the user to config- ure the lapd transmitter to either transmit the lapd message frame only once; or repeatedly at one-sec- ond intervals. writing a "0" to this bit-field configures the lapd transmitter to transmit the lapd message frame once. afterwards, the lapd transmitter will halt transmission, until it has commanded to transmit an- other lapd message frame. writing a "1" to this bit-field configures the lapd transmitter to transmit the lapd message frame re- peatedly at one second intervals. in this configura- tion, the lapd transmitter will repeat its transmission of the lapd message frame until it has been dis- abled. bit 1 - txlapd message length select this "read/write" bit-field permits the user to select the length of the "outbound" lapd message frame. setting this bit-field to "0" configures the "outbound" lapd message frame to be 76 bytes in length. set- ting this bit-field to "1" configures the "outbound" lapd message frame to be 82 bytes in length. bit 0 - txlapd enable this "read/write" bit-field allows the user to enable or disable the lapd transmitter. the lapd trans- mitter must be enabled before it can be commanded to transmit a lapd message frame (containing a pm- dl message) via the outbound ds3 frames, to the "far-end" terminal. writing a "0" disables the lapd transmitter (default condition). writing a "1" enables the lapd transmit- ter. n ote : for information on the lapd transmitter, please see section _. 3.3.2.48 txds3 lapd status/interrupt register ) bit 3 - txdl start this "read/write" bit-field allows the user to invoke the "transmit lapd message" command. once the user invokes this command, the lapd transmitter will do the following: ? read in the pmdl message from the "transmit lapd message" buffer. ? encapsulate the pmdl message into a complete lapd message frame by including the necessary txds3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable ro r/wr/wr/wr/wr/wr/wr/w 00001000 txds3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 219 header and trailer bytes (e.g., flag sequence bytes, sapi, cr, ea values, etc.). ? compute the frame check sequence word (16 bit value) ? insert the frame check sequence value into the 2 octet slot after the payload section of the message. ? proceed to transmit the lapd message frame to the "far end" terminal via the outgoing ds3 frames. writing a "1" to this bit-field start the transmission of the lapd message frame, via the lapd transmitter. n ote : for more information on the lapd transmitter, please see section _. bit 2 - txdl busy this "read-only" bit-field allows the local p to "poll" and determine if the lapd transmitter has completed its transmission of the lapd message frame. this bit-field will contain a "1", if the lapd transmitter is still transmitting the lapd message frame to the "far- end" terminal. this bit-field will toggle to "0", once the lapd transmitter has completed its transmission of the lapd message frame. n ote : for more information on the lapd transmitter, please see section _. bit 1 - txlapd interrupt enable this "read/write" bit-field allows the user to enable or disable the "lapd message frame transmission complete" interrupt. writing a "0" to this bit-field disables this interrupt. writing a "1" to this bit-field enables this interrupt. bit 0 - txlapd interrupt status this "reset upon read" bit-field indicates whether or not the "lapd message frame transmission com- plete" interrupt has occurred since the last read of this register. the purpose of this interrupt is to let the local p know that the lapd transmitter has com- pleted its transmission of the lapd message frame (containing the latest pmdl message); and is now ready to transmit another lapd message frame. a "0" in this bit-field indicates that the "lapd mes- sage frame transmission complete" interrupt has not occurred since the read of this register. a "1" in this bit-field indicates that this interrupt has occurred since the last read of this register. n ote : for more information on the lapd transmitter, please see section _. 3.3.2.49 txds3 m-bit mask register ) bit 7 - 5: txfebedat[2:0] these three (3) "read/write" bit-fields, along with bit 4 of this register, allows the user to configure and trans- mit his/her choice for febe bits in each outgoing ds3 frame. the user will write his/her value for the febe bits into these bit-fields. the transmit ds3 framer will insert these values into the febe bit-fields of each outgoing ds3 frame, once the user has written a "1" to bit 4 (febe register enable). n ote : for more information on this feature, please see section _. bit 4 - febe register enable this "read/write" bit-field allows the user to config- ure the transmit ds3 framer to insert the contents of txfebedat[2:0] into the febe bit-fields each outgo- ing ds3 frame. writing a "0" to this bit-field disables this feature (e.g., the transmit ds3 framer will transmit the internally generated febe bits). writing a "1" to this bit-field enables this features (e.g., the internally generated febe bits are overwritten by the contents of the txfebedat[2:0] bit-field). n ote : for more information on this feature, please see section _. bit 3 - transmit erred p-bit this "read/write bit-field allows the user to insert er- rors into the p-bits of the outgoing ds3 frames (via the transmit ds3 framer block). if the user enables this feature, then the transmit ds3 framer will pro- ceed to invert each and every p-bit, from its comput- ed value, prior to transmission to the "far-end" termi- nal. writing a "0" to this bit-field (the default condition) dis- ables this feature (e.g., the correct p-bits are sent). txds3 m-bit mask register (address = 0x35) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 txfebedat[2:0] febe reg enable tx error p-bit mbit mask[2] mbit mask[1] mbit mask[0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 220 writing a "1" to this bit-field enables this feature (e.g., the incorrect p-bits are sent). n ote : for more information on this feature, please see section _. bit 2 - 0 m-bit mask[2:0] these "read/write" bit-fields allow the user to insert errors in the m-bits for test and diagnostic purposes. the transmit ds3 framer automatically performs an xor operation on the actual contents of the m-bit fields to these register bit-fields. therefore, for every '1' that exists in these bit-fields, will result in a change of state of the corresponding m-bit, prior to being transmitted to the far end receive ds3 framer. if the user wishes to operate the transmit ds3 fram- er in the normal mode (e.g., when no errors are being injected into the m-bit fields of the outbound ds3 frame), then he/she must ensure that these bit-fields are all '0'. 3.3.2.50 tx ds3 f-bit mask1 register ) bits 3 - 0 f-bit mask[27:24] these "read/write" bit-fields allow the user to insert errors into the first four f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3 framer block (within the chip) automatically performs an xor operation on the actual contents of these f- bit fields to these register bit-fields. therefore, for ev- ery "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the far-end receive ds3 fram- er. if the user wishes to operate the transmit ds3 fram- er block in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then he/she must ensure that all of these bit-fields are "0s". 3.3.2.51 txds3 f-bit mask2 register ) bits 7 - 0 f-bit mask[23:16] these "read/write" bit-fields allow the user to insert errors into the fifth through twelfth f-bits of a ds3 m- frame, for test and diagnostic purposes. the trans- mit ds3 framer block automatically performs an xor operation on the actual contents of these f-bit fields to these register bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the remote receive ds3 fram- er. if the user wishes to operate the transmit ds3 fram- er block in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then he/she must ensure that all of these bit-fields are "0s". 3.3.2.52 txds3 f-bit mask3 register tx ds3 f-bit mask register - 1 (address = 0x36) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used fbit mask[27] fbit mask[26] fbit mask[25] fbit mask[24] ro ro ro ro r/w r/w r/w r/w 00000000 txds3 f-bit mask register - 2 (address = 0x37) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[23] fbit mask[22] fbit mask[21] fbit mask[20] fbit mask[19] fbit mask[18] fbit mask[17] fbit mask[16] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 221 ) bits 7 - 0 f-bit mask[15:8] these "read/write" bit-fields allow the user to insert errors into the thirteenth through twentieth f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3 framer automatically performs an xor operation on the actual contents of these f-bit fields to these register bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the far-end receive ds3 fram- er. if the user wishes to operate the transmit ds3 fram- er in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 frames), then he/she must ensure that all of these bit- fields are "0s". 3.3.2.53 txds3 f-bit mask4 register ) bits 7 - 0 f-bit mask[7:0] these "read/write" bit-fields allow the user to insert errors into the last eight f-bits of a ds3 m-frame, for test and diagnostic purposes. the transmit ds3 framer automatically performs an xor operation on the actual contents of these f-bit fields to these regis- ter bit-fields. therefore, for every "1" that exists in these bit-fields, this will result in a change of state for the corresponding f-bit, prior to being transmitted to the far-end receive ds3 framer. if the user wishes to operate the transmit ds3 fram- er in the normal mode (e.g., when no errors are being injected into these f-bit fields of the outbound ds3 3.3.2.54 m12 ds2 # 1 framer configuration register 3.3.2.55 m12 ds2 # 2 framer configuration register 3.3.2.56 m12 ds2 # 3 framer configuration register 3.3.2.57 m12 ds2 # 4 framer configuration register 3.3.2.58 m12 ds2 # 5 framer configuration register 3.3.2.59 m12 ds2 # 6 framer configuration register 3.3.2.60 m12 ds2 # 7 framer configuration register 3.3.2.61 pmon lcv event count register - msb tx ds3 f-bit mask register - 3 (address = 0x38) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[15] fbit mask[14] fbit mask[13] fbit mask[12] fbit mask[11] fbit mask[10] fbit mask[9] fbit mask[8] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 txds3 f-bit mask register - 4 (address = 0x39) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask[7] fbit mask[6] fbit mask[5] fbit mask[4] fbit mask[3] fbit mask[2] fbit mask[1] fbit mask[0] r/w r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 222 this "reset-upon-read" register, along with the "pmon lcv event count register - lsb" (address = 0x51) contains a 16-bit representation of the number of "line code violations" that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expres- sion. 3.3.2.62 pmon lcv event count register - lsb this "reset-upon-read" register, along with the "pmon lcv event count register - lsb" (address = 0x50) contains a 16-bit representation of the number of "line code violations" that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expres- sion. 3.3.2.63 pmon framing bit error event count register - msb this "reset-upon-read" register, along with the "pmon framing bit error count register - lsb" (ad- dress = 0x53) contains a 16-bit representation of the number of "framing bit errors" that have been de- tected by the receive ds3 framer block (within the chip), since the last read of these registers. this reg- ister contains the msb (or upper-byte) value of this 16 bit expression. 3.3.2.64 pmon framing bit error event count register - lsb pmon lcv event count register - msb (address = 0x50) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv count - high byte rurrurrurrurrurrurrurrur 00000000 pmon lcv event count register - lsb (address = 0x51) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 lcv count - low byte rurrurrurrurrurrurrurrur 00000000 pmon framing bit error count register - msb (address = 0x52) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit error count - high byte rurrurrurrurrurrurrurrur 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 223 this "reset-upon-read" register, along with the "pmon framing bit error count register - msb" (ad- dress = 0x52) contains a 16-bit representation of the number of "framing bit errors" that have been detect- ed by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. 3.3.2.65 pmon p-bit error event count regis- ter - msb this "reset-upon-read" register, along with the "pmon p-bit error count register - lsb" (address = 0x55) contains a 16-bit representation of the number of "p-bit errors that have been detected by the re- ceive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 3.3.2.66 pmon p-bit error event count regis- ter - lsb this "reset-upon-read" register, along with the "pmon p-bit error count register - msb" (address = 0x54) contains a 16-bit representation of the number of "p-bit errors that have been detected by the re- ceive ds3 framer block (within the chip), since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. 3.3.2.67 pmon febe event count register - msb pmon framing bit error count register - lsb (address = 0x53) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 framing bit error count - low byte rur rur rur rur rur rur rur rur 00000000 pmon p-bit error count register - msb (address = 0x54) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 p-bit error count - high byte rur rur rur rur rur rur rur rur 00000000 pmon p-bit error count register - lsb (address = 0x55) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 p-bit error count - low byte rur rur rur rur rur rur rur rur 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 224 this "reset-upon-read" register, along with the "pmon febe event count register - lsb" (address = 0x57) contains a 16-bit representation of the num- ber of "febe events that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 3.3.2.68 pmon febe event count register - lsb this "reset-upon-read" register, along with the "pmon febe event count register - msb" (address = 0x56) contains a 16-bit representation of the num- ber of "febe events that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the lsb (or lower-byte) value of this 16 bit expression. 3.3.2.69 pmon cp-bit error event count regis- ter - msb this "reset-upon-read" register, along with the "pmon cp-bit error count register - lsb" (address = 0x59) contains a 16-bit representation of the num- ber of "cp-bit errors that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 3.3.2.70 pmon cp-bit error event count regis- ter - lsb pmon febe event count register - msb (address = 0x56) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 febe event count - high byte rurrurrurrurrurrurrurrur 00000000 pmon febe event count register - lsb (address = 0x57) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 febe event count - low byte rurrurrurrurrurrurrurrur 00000000 pmon cp-bit error count register - msb (address = 0x58) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error count - high byte rurrurrurrurrurrurrurrur 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 225 this "reset-upon-read" register, along with the "pmon cp-bit error count register - msb" (address = 0x58) contains a 16-bit representation of the num- ber of "cp-bit errors that have been detected by the receive ds3 framer block (within the chip), since the last read of these registers. this register contains the msb (or upper-byte) value of this 16 bit expression. 3.3.2.71 pmon ds2 # 1 framing bit error counter 3.3.2.72 pmon ds2 # 2 framing bit error counter 3.3.2.73 pmon ds2 # 3 framing bit error counter 3.3.2.74 pmon ds2 # 4 framing bit error counter 3.3.2.75 pmon ds2 # 5 framing bit error counter 3.3.2.76 pmon ds2 # 6 framing bit error counter 3.3.2.77 pmon ds2 # 7 framing bit error counter 3.3.2.78 pmon itu-t g.747 # 1 parity bit error counter 3.3.2.79 pmon itu-t g.747 # 2 parity bit error counter 3.3.2.80 pmon itu-t g.747 # 3 parity bit error counter 3.3.2.81 pmon itu-t g.747 # 4 parity bit error counter 3.3.2.82 pmon itu-t g.747 # 5 parity bit error counter 3.3.2.83 pmon itu-t g.747 # 6 parity bit error counter 3.3.2.84 pmon itu-t g.747 # 7 parity bit error counter 3.3.2.85 pmon holding register each of the pmon registers are 16 bit "reset-upon- read" registers. more specifically, whenever the mi- croprocessor intends to read a pmon register, there are two things to bear in mind. 1. this microprocessor is going to require two read accesses in order read out the full 16-bit expres- sion of these pmon registers. 2. the entire 16-bit expression (of a given pmon register) is going to be reset, immediately after pmon cp-bit error count register - lsb (address = 0x59) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error count - low byte rur rur rur rur rur rur rur rur 00000000 pmon holding register (address = 0x6c) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 pmon holding value rur rur rur rur rur rur rur rur 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 226 the microprocessor has completed its first read access to the pmon register. hence, the contents of the other byte (of the partially read pmon register) will reside within the pmon holding register. 3.3.2.86 one second error status register 3.3.2.87 lcv one second accumulator regis- ter - msb 3.3.2.88 lcv one second accumulator regis- ter - lsb 3.3.2.89 p-bit error one second accumulator register - msb 3.3.2.90 p-bit error one second accumulator register - lsb 3.3.2.91 cp-bit error one second accumulator register - msb 3.3.2.92 cp-bit error one second accumulator register - lsb 3.3.2.93 line interface drive register 3.3.2.94 line interface scan register ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 227 4.0 clear channel framer operation of the XRT72L13 the XRT72L13 m13/framer ic can be configured to operate in any of the following modes: ? clear-channel framer mode ? channelized (m13) mode ? high-speed hdlc controller mode. as a consequence, the discussion of the XRT72L13 will be organized as follows: section 4.0 - clear channel framer mode operation of the XRT72L13. section 5.0 - channelized (m13) mode operation of the XRT72L13. section 5.0 - high-speed hdlc controller (e.g., frame-relay over ds3) mode. section 6.0 - diagnostic features of the XRT72L13. this section will discuss clear-channel framer mode operation of the XRT72L13, in detail. configuring the XRT72L13 to operate in the clear-channel framer mode the XRT72L13 can be configured to operate in the "clear-channel framer" mode by writing a "0" into bit- field 6 (payload hdlc controller enable) and bit 4 (m13 disable) within the m23 configuration" register; as illustrated below. the XRT72L13 can be configured to support either the ds3 m13 or the ds3 c-bit parity framing for- mats. prior to describing the functional blocks within the transmit and receive sections of the XRT72L13; it is important to describe these following two framing formats. ? m13 ? c-bit parity 4.1 d escription of the ds3 f rames and a ssoci - ated o verhead b its the role of the various overhead bits are best de- scribed by discussing the ds3 frame format as a whole. the ds3 frame contains 4760 bits, of which 56 bits are overhead and the remaining 4704 bits are "payload" bits. the "payload" data is formatted into packets of 84 bits and the overhead (oh) bits are in- serted between these payload packets. the XRT72L13 framer device supports the following two ds3 framing formats: ? c-bit parity ? m13 figures 59 and 60 present the ds3 frame format for c-bit parity and m13, respectively. m23 configuration register (address = 0x07) b it 7 b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused payload hdlc controller enable rxds1clk gapped (crc-32) m13 disable m13 loop-back (remote loop-back) tr i b u t a r y polarity m23 loop-back code[1:0] r/o r/wr/wr/wr/wr/wr/wr/w x 0x1xxxx XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 228 x = signaling bit for network control i = payload information (84 bit packets) fi = frame synchronization bit with logic value i p = parity bit mi = multiframe synchronization bit with logic value i aic = application identification channel na = reserved for network application feac = far end alarm and control dl = data link cp = cp (path)-bit parity febe = far end block error udl = user data link x = signaling bit for network control i = payload information (84 bit packets) fi = frame synchronization bit with logic value i cij = jth stuff code bit of ith channel p = parity bit mi = multiframe synchronization bit with logic values i the user can choose between these two framing for- mats, by writing the appropriate data to bit 2 of the "operating mode" register (address = 0x00), as de- picted below. f igure 59. ds3 f rame f ormat for c- bit p arity x if1 iaic if0 ina if0 i feac if1 i i x if1 i udl if0 ina if0 i feac if1 i p if1 icp if0 icp if0 icp if1 i p if1 i febe if0 i febe if0 i febe if1 i m0 if1 idl if0 idl if0 idl if1 i m1 if1 i udl if0 iudl if0 i udl if1 i m0 if1 i udl if0 iudl if0 i udl if1 i f igure 60. ds3 f rame f ormat for m13 x if1 ic11 if0 ic12 if0 ic13 if1 i i x if1 ic21 if0 ic22 if0 ic23 if1 i p if1 ic31 if0 ic32 if0 ic33 if1 i p if1 ic41 if0 ic42 if0 ic43 if1 i m0 if1 ic51 if0 ic52 if0 ic53 if1 i m1 if1 ic61 if0 ic62 if0 ic63 if1 i m0 if1 ic71 if0 ic72 if0 ic73 if1 i ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 229 table 10 lists the relationship between the value of the this bit-field and the resulting ds3 frame format. n ote : this bit setting also configures the frame format for both the transmit and receive section of the XRT72L13. each of the two ds3 frame formats, as presented in figure 59 and figure 60 , constitute an m-frame (or a full ds3 frame). each m-frame consists of 7 - 680 bit f-frames (sometimes referred to as, subframes). in figure 59 and 60 , each f-frame is represented by the individual rows of payload and overhead bits. each f-frame can be further divided into 8 blocks of 85 bits, with 84 of the 85 bits available for payload in- formation and the remaining one bit used for frame overhead. differences between the m13 and c-bit parity frame formats the frame formats for m13 and c-bit parity are very similar. however, the main difference between these two framing formats is in the use of the c-bits. m13 framing format in the m13 format, the c-bits typically reflect the sta- tus of stuff-opportunities that either were or were not used while multiplexing the 7 ds2 signals into this ds3 signal. if two of the three stuff bits, within a f- frame, are "1", then the associated stuff bit, si (not shown in figure 60 ), is interpreted as being a stuff bit. n otes : 1. for clear-channel framing applications, each of these 21 c-bits will automatically set to 0. 2. for channelized applications, then these c-bits will reflect the stuff-bit status of the composite ds2/itu-t g.747 signals, wiithin the ds3 signal. c-bit parity framing format in the c-bit parity framing format, the "c" bits take on different roles, as presented in table 11 . operating mode register (address = 0x00) b it 7 b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w x 1x0x xxx t able 10: t he r elationship between the content of b it 2, (c-b it p arity */m13) within the "f ramer o perating m ode " r egister and the resulting ds3 f raming f ormat b it 2 ds3 f rame f ormat 0 c-bit parity 1m13 t able 11: c- bit f unctions for the c- bit p arity ds3 f rame f ormat c - b it f unction of c- bits while in the c-b it p arity f raming f ormat c11 aic (c-bit parity mode) c12 na (reserved for network application) c13 feac (far end alarm & control) c21, c22, c23 user data link (undefined for ds3 frame) c31,c32, c33 c-bit parity bits c41, c42, c43 febe (far end block error) indicators c51, c52, c53 path maintenance data link c61, c62, c63, c71, c72, c73 user data link (undefined for ds3 frame) XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 230 definition of the ds3 frame overhead bits in general, the ds3 frame overhead bits serve the following three purposes: 1. support frame synchronization between the local and remote ds3 terminals 2. provide parity bits in order to facilitate perfor- mance monitoring and error detection. 3. support the transmission of alarms, status, and data link information to the remote ds3 termi- nal. the overhead bits supporting each of these purpos- es are further defined below. 4.1.1 frame synchronization bits (applies to both m13 and c-bit parity framing formats) each ds3 frame (m-frame) contains a total of 31 bits that support frame synchronization. each ds3 m- frame contains three m-bits. according to figure 59 and figure 60 , these m-bits are the first bits in f- frames 5, 6 and 7. these three bits appear in each m-frame with the repeating pattern of "010". this fact is also presented in figure 59 and figure 60 , which contains bit-fields that are designated as: m0, m1, and m0 (where m0 = "0", and m1 = "1"). each f-frame contains four f-bits; which also aid in synchronization between the local and the "remote" ds3 terminals. therefore, each ds3 "m-frame" con- sists of a total of 28 f-bits. these f-bits exhibit a re- peating pattern of "1001" within each f-frame. this fact is also presented in figure 59 and figure 60 , which contains bit-fields that are designated as: f1, f0, f0, and f1 (where f0 = "0", and f1 = "1"). each of these bit-fields will be used by the receive ds3 framer block, within the remote terminal equip- ment, to perform frame acquisition and frame main- tenance functions. n ote : for more information on how the receive ds3 framer uses these bit-fields, please see section 3.3.2. 4.1.2 performance monitoring/error detection bits (parity) the ds3 frame uses numerous bit fields to support performance monitoring of the transmission link be- tween the "local" transmitting terminal and the "re- mote" receiving terminal. the ds3 frame can con- tain two types of parity bits, depending upon the fram- ing format chosen. p-bits are available in both the m13 and c-bit parity formats. however, the c-bit parity format also includes additional "cp-parity" bits. p-bits (applies to m13 and c-bit parity frame for- mats) each ds3 "m-frame" consists of two (2) p-bits. these two p-bits carry the parity information of the previous ds3 frame for performance monitoring. these two p-bits must be identical, within a given ds3 frame. the transmit section will compute the even parity over all 4704 payload bits within a given ds3 frame, and insert the resulting parity information in the p-bit fields of the very next ds3 frame. the two p-bits are set to "1" if the payload of the previous ds3 frame consists of an odd number of "ones" in the frame. conversely, the two p-bits are set to zero if an even number of "ones" is found in the payload of the previous ds3 frame. for information on how the re- ceive ds3 framer handles p-bits, please see section 3.3.2.6.1. 4.1.3 alarm and signaling-related overhead bits the alarm indication signal (ais) pattern (c-bit pari- ty framing format only) the alarm indication signal (ais) pattern is an alarm signal that is inserted into the "outbound" ds3 stream when a failure is detected by the local" terminal. the transmit ds3 framer will generate the ais pat- tern as defined in ansi.t1.107a-1990, which is de- scribed as follows. v alid m- bits , f- bits , and p- bits ? all c-bits are zeros ? all x-bits are set to "1" ? a repeating "1010..." pattern is written into the pay- load of the ds3 frames. consequently, no user (or "payload") data will be transmitted while the transmit section of the chip is transmitting the ais pattern. the idle condition signal the idle condition signal is used to indicate that the ds3 channel is functionally sound, but has not yet been assigned any traffic. the transmit section will transmit the idle condition signal as defined in ansi t1.107a-1990, which is described as follows. ? valid m-bits, f-bits, and p-bits ? the three cp-bits (f-frame #3) are zeros ? the x-bits are set to "1" ? a repeating "1100.." pattern is written into the pay- load of the ds3 frames. feac - far end alarm & control (only available for the c-bit parity frame format) the third c-bit (c13 or feac) in the first f-frame is used as the "far end alarm and control" (feac) channel between the "near-end" ds3 terminal and the "remote" ds3 terminal. the feac channel car- ries: ? alarm and status information ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 231 ? loopback commands to initiate and deactivate ds3 and ds1 loopbacks at the distant terminals. the feac message consists of a six (6) bit code word of the form [d5, d4, d3, d2, d1 d0]. this mes- sage is encapsulated with 10 framing bits to form a 16 bit "feac message"; as illustrated below. the feac signals are encoded into repeating 16 bit mes- sage of the form: since each ds3 frame carries only one feac bit, 16 ds3 frames are required to deliver 1 complete feac message. the six bits labeled "dx" can represent up- to 64 distinct messages, of which 43 have been de- fined in the standards. for a more detailed discus- sion on the transmission of feac messages, please see section 3.2.3.1. febe - far end block error (only available for the c-bit parity frame format) f-frame # 4 consists of 3 bit fields for the febe (far- end block error) channel. if the (local) receive sec- tion (within the framer ic) detects p-bit parity errors, cp-bit errors or a framing error on the incoming (re- ceived) ds3 stream it will inform the transmit section of this fact. the transmit section will, in turn, set the three febe bits (within an outgoing ds3 frame) to any pattern other than "111" to indicate an error. the transmit section will then transmit this information out to the "remote" terminal (e.g., the source of the errored-data). the febe bits, in the outbound ds3 frames, are set to "111" only if both of the following conditions are true: ? the receive ds3 framer has detected no m-bit or f-bit framing errors, and ? no p-bit parity errors have been detected. ? no cp-bit errors have been detected. n ote : a more detailed discussion on the transmit sec- tion's handling of the "febe" bit-fields can be found in sec- tion 3.2.4.2.1.9. the yellow alarm or ferf (far-end receive fail- ure) indicator the x-bits are used for sending "yellow alarms" or the ferf (far-end receive failure) indication. when the receive section (of the XRT72L13), within the "remote" receiving terminal equipment, cannot identify valid framing, or detects an ais pattern in the incoming ds3 data-stream, the framer ic can be configured such that the transmit section will send a "yellow alarm" or a ferf (far-end receive failure) indication to the "remote" terminal by setting both of the x-bits to zero in the outbound (returning) ds3 path. the x-bits are set to "1" during non-alarm con- ditions. 4.1.4 the "data link" related overhead bits udl: user data link (c-bit parity frame format only) these bit-fields are not used by the framer and are set to "1" by default. however, these bits may be used for the transmission of data via a proprietary da- ta link. the user can access these bit-fields via the transmit overhead data input interface and the re- ceive overhead data output interface blocks. dl: path maintenance data link (c-bit parity frame format only) the lapd transceiver block uses these bit-fields for the transmission and reception of path maintenance data link (pmdl) messages via itu-t q.921 (lap-d) message frames. please see sections 3.2.3.2 and 3.3.3.2 for more information on the operation and function of the lapd transmitter. 4.2 t he t ransmit s ection of the XRT72L13 (c lear -c hannel f ramer m ode o peration ) when the XRT72L13 has been configured to operate in the clear-channel framer mode, the transmit sec- tion of the XRT72L13 consists of the following func- tional blocks. ? transmit payload data input interface block ? transmit overhead data input interface block ? transmit ds3 framer block ? transmit ds3 hdlc controller block ? transmit liu interface block figure 61 presents a simple illustration of the trans- mit section of the XRT72L13 framer ic. 0 d5 d4 d3 d2 d1 d0011111111 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 232 each of these functional blocks will be discussed in detail in this document. 4.2.1 the "transmit payload data input inter- face" block figure 62 presents a simple illustration of the "trans- mit payload data input interface" block. f igure 61. a s imple i llustration of the t ransmit s ection , within the XRT72L13; when it has been con - figured to operate in the c lear -c hannel f ramer m ode transmit payload data input interface block transmit ds3/e3 framer block transmit liu interface block txser txnib[3:0] txinclk txpos txneg txlineclk transmit overhead input interface block txohclk txohins txohind txoh txohenable txohframe txnibclk txframe tx ds3 hdlc controller/buffer tx ds3 hdlc controller/buffer from microprocessor interface block ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 233 each of the input and output pins of the "transmit payload data input interface" are listed in table 12 and described below. the exact role that each of these inputs and output pins assume, for a variety of operating scenarios, are described throughout this section. f igure 62. a s imple i llustration of the t ransmit p ayload d ata i nput i nterface b lock transmit payload data input interface block transmit payload data input interface block txoh_ind txser txnib[3:0] txinclk txnibclk txframe txframeref to transmit ds3 framer block XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 234 t able 12: l isting and d escription of the pins associated with the "t ransmit p ayload d ata i nput i nterface s ignal n ame t ype d escription txser input transmit serial payload data input pin: if the user opts to operate the XRT72L13 in the "serial" mode, then the terminal equipment is expected to apply the payload data (that is to be transported via the "outbound" ds3 data stream) to this input pin. the XRT72L13 will sample the data that is at this input pin; upon the rising edge either the "rxoutclk" or the "txinclk" signal (whichever is appropriate). n ote : this signal is only active if the "nibint" input pin is pulled "low". txnib[3:0] input transmit nibble-parallel payload data input pins: if the user opts to operate the XRT72L13 in the "nibble-parallel" mode, then the terminal equipment is expected to apply the payload data (that is to be transported via the "outbound" ds3 data stream) to these input pins. the XRT72L13 will sample the data that is at these input pins; upon the rising edge of the "txnibclk" signal. n ote : these pins are only active if the "nibint" input pin is pulled "high". txinclk input transmit section timing reference clock input pin: the transmit section of the XRT72L13 can be configured to use this clock signal as the "tim- ing reference". if the user has made this configuration selection, then the XRT72L13 will use this clock signal to sample the data on the txser input pin. n ote : if the user has made this configuration selection; then he/she must insure that a 44.736 mhz clock signal is applied to this input pin. txnibclk output transmit nibble mode output if the user opts to operate the XRT72L13 in the "nibble-parallel" mode, then the XRT72L13 will derive this clock signal from the selected "timing reference" for the transmit section of the chip (e.g., either the txinclk or the rxlineclk signals). the XRT72L13 will use this signal to sample the data on the "txnib[3:0]" input pins. txohind output transmit overhead bit indicator output: this output pin will pulse "high" one-bit period prior to the time that the transmit section of the XRT72L13 will be processing an overhead bit. the purpose of this output pin is to warn the terminal equipment that, during the very next bit-period, the XRT72L13 is going to be pro- cessing an "overhead" bit and will be ignoring any data that is applied to the "txser" input pin. for ds3 applications, this output pin is only active if the XRT72L13 is operating in the "serial" mode. this output pin will be pulled "low" if the device is operating in the "nibble-parallel" mode. txframe output transmit "end of frame" output indicator: the transmit section of the XRT72L13 will pulse this output pin "high" (for one bit-period), when the transmit payload data input interface is processing the last bit of a given ds3 frame. the purpose of this output pin is to alert the terminal equipment that it needs to begin trans- mission of a new ds3 frame to the XRT72L13 (e.g., to permit the XRT72L13 to maintain transmit ds3 framing alignment control over the terminal equipment). txframeref input transmit frame reference input: the XRT72L13 permits the user to configure the transmit section to use this input pin as a "frame reference". if the user makes this configuration selection, then the transmit section will initiate its transmission of a new ds3 frame, upon the rising edge of this signal. the purpose of this input pin is to permit the terminal equipment to maintain transmit ds3 framing alignment control over the XRT72L13. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 235 operation of the "transmit payload data input in- terface" the transmit payload data input interface is ex- tremely flexible, in that it permits the user to make the following configuration options. ? the "serial" or the "nibble-parallel" interface mode ? the "loop-timing" or the "txinclk" (local timing) mode further, if the XRT72L13 has been configured to op- erate in the "txinclk" (local timing) mode, then the user has two additional options. ? the XRT72L13 functions as the "frame master" (e.g., it dictates when the terminal equipment will initiate the transmission of data within a new ds3 frame). ? the XRT72L13 functions as the "frame slave" (e.g., the terminal equipment will dictate when the XRT72L13 initiates the transmission of a new ds3 frame). given these three set of options, the transmit termi- nal input interface can be configured to operate in one of the six (6) following modes. ? mode 1 - "serial/loop-timed" mode ? mode 2 - "serial/local-timed/frame slave" mode ? mode 3 - "serial/local-timed/frame master" mode ? mode 4 - "nibble/loop-timed" mode ? mode 5 - "nibble/local-timed/frame slave" mode ? mode 6 - "nibble/local-timed/frame master" mode each of these modes are described, in detail, below. 4.2.1.1 mode 1 - the "serial/loop-timing" mode the behavior of the XRT72L13 if the XRT72L13 has been configured to operate in this mode, then the XRT72L13 will behave as follows. a. loop-timing (uses the "rxlineclk" signal as the timing reference) since the XRT72L13 is configured to operate in the "loop-timed" mode, the transmit section (of the XRT72L13) will use the "rxlineclk" input clock signal (e.g., the recovered clock signal, from the liu) as its timing source. when the XRT72L13 is operating in this mode it will do the following. 1. it will ignore any signal at the "txinclk" input pin. 2. the XRT72L13 will output a 44.736mhz clock signal via the "rxoutclk" output pin. this clock signal functions as the "transmit payload data input interface" block clock signal. 3. the XRT72L13 will use the rising edge of the "rxoutclk" signal to latch in the data residing on the txser input pin. b. serial mode the XRT72L13 will accept the "ds3" payload data from the terminal equipment, in a serial-manner, via the "txser" input pin the "transmit payload data in- put interface" block will latch this data into its circuitry, on the rising edge of the "rxoutclk" output clock sig- nal. c. delineation of "outbound" ds3 frames the XRT72L13 will pulse the "txframe" output pin "high" for one bit-period; coincident with the XRT72L13 processing the last bit of a given ds3 frame. d. sampling of payload data, from the terminal equipment in mode 1, the XRT72L13 will sample the data at the "txser" input, on the rising edge of "rxoutclk". interfacing the "transmit payload data input in- terface" block (of the XRT72L13) to the terminal equipment for mode 1 operation figure 63 presents an illustration of the "transmit payload data input interface" block (within the XRT72L13) being interfaced to the terminal equip- ment, for "mode 1" operation. rxoutclk output loop-timed timing reference clock output pin: the transmit section of the XRT72L13 can be configured to use the "rxlineclk" signal as the "timing reference" (e.g., loop-timing). if the user has made this configuration selection, then the XRT72L13 will: ? output a 44.736 mhz clock signal via this pin, to the terminal equipment. ? sample the data on the "txser" input pin, upon the rising edge of this clock signal. t able 12: l isting and d escription of the pins associated with the "t ransmit p ayload d ata i nput i nterface s ignal n ame t ype d escription XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 236 mode 1, operation of the terminal equipment when the XRT72L13 is operating in this mode; it will function as the source of the 44.736mhz clock signal (via the rxoutclk signal). this clock signal will be used as the "terminal equipment interface" clock by both the XRT72L13 ic and the terminal equipment. the terminal equipment will serially output the "pay- load data" of the "outbound" ds3 data stream via its "ds3_data_out" pin. the terminal equipment will update the data on the "ds3_data_out" pin upon the rising edge of the 44.736 mhz clock signal, at its "ds3_clock_in" input pin (as depicted in figure 63 and figure 64 ). the XRT72L13 will latch the "outbound" ds3 data stream (from the terminal equipment) on the rising edge of the "rxoutclk" signal. the XRT72L13 will indicate that it is processing the last bit, within a given "outbound" ds3 frame, by puls- ing its "txframe" output pin "high" for one bit-period. when the terminal equipment detects this pulse at its "tx_start_of_frame" input, it is expected to begin transmission of the very next outbound ds3 frame to the XRT72L13 via the "ds3_data_out" (or "txser" pin). finally, the XRT72L13 will indicate that it is about to process an overhead bit by pulsing the "txoh_ind" output pin "high" one bit period prior to its processing of an oh (overhead) bit. in figure 63 , the "txoh_ind" output pin is connected to the "ds3_overhead_ind" input pin; of the terminal equipment. whenever the "ds3_overhead_ind" pin is pulsed "high" the terminal equipment is expected to not transmit a ds3 payload bit upon the very next clock edge. instead, the terminal equipment is ex- pected to delay its transmission of the very next pay- load bit, by one clock cycle. the behavior of the signals, between the XRT72L13 and the terminal equipment, for ds3 mode 1 opera- tion is illustrated in figure 64 . f igure 63. i llustration of the "t erminal e quipment " being interfaced to the "t ransmit p ayload d ata i nput i nterface " block ( of the XRT72L13) for m ode 1(s erial /l oop -t iming ) o peration terminal equipment XRT72L13 ds3 framer ds3_data_out ds3_clock_in tx_start_of_frame ds3_overhead_ind txser rxoutclk txframe txoh_ind nibint 44.736 mhz ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 237 . how to configure the XRT72L13 into the "serial/ loop-timed/non-overhead interface" mode 1. set the "nibintf" input pin "low". 2. set the "timrefsel[1:0]" bit fields (within the "framer operating mode register") to "00"; as illustrated below. 3. interface the XRT72L13, to the terminal equip- ment, as illustrated in figure 63 . n ote : the XRT72L13 framer ic cannot support the framer local loop-back mode of operation, when operat- ing in the loop-timing mode. the user must configure the XRT72L13 framer ic into any of the following modes, prior to configuring the framer local loop-back mode. ? mode 2 - serial/local-timed/frame-slave mode. ? mode 3 - serial/local-timed/frame-master mode. ? mode 5 - nibble-parallel/local-timed/frame-slave mode. ? mode 6 - nibble-parallel/local-timed/frame-mas- ter mode. for more detailed information on framer local loop- back mode of operation, please see section 6.0. 4.2.1.2 mode 2 - the "serial/local-timed/ frame-slave" mode behavior of the XRT72L13 f igure 64. b ehavior of the "t erminal i nterface " signals between the "t ransmit p ayload d ata i nput i nterface " block ( of the XRT72L13) and the t erminal e quipment ( for m ode 1 o peration ) terminal equipment signals ds3_clock_in ds3_data_out tx_start_of_frame ds3_overhead_ind XRT72L13 transmit payload data i/f signals rxoutclk txser txframe txoh_ind payload[4702] payload[4703] x-bit payload[0] payload[4702] payload[4703] x-bit payload[0] note: x-bit will not be processed by the transmit payload data input interface. ds3 frame number n ds3 frame number n + 1 note: txframe pulses high to denote ds3 frame boundary. note: txoh_ind pulses high to denote overhead data (e.g., the x-bit). operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 0 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 238 if the XRT72L13 has been configured to operate in this mode, then the XRT72L13 will function as fol- lows. a. local-timing - uses the "txinclk" signal as the timing reference in this mode, the transmit section of the XRT72L13 will use the txinclk signal as its timing reference. b. serial mode the XRT72L13 will receive the ds3 payload data, in a serial manner, via the "txser" input pin. the "transmit payload data input interface" (within the XRT72L13) will latch this data into its circuitry, on the rising edge of the "txinclk" input clock signal. c. delineation of "outbound" ds3 frames (frame slave mode) the transmit section (of the XRT72L13) will use the "txinclk" input as its timing reference, and will use the "txframeref" input signal as its "framing refer- ence". in other words, the transmit section of the XRT72L13 will initiate frame generation upon the ris- ing edge of the "txframeref" input signal). d. sampling of payload data, from the terminal equipment in mode 2, the XRT72L13 will sample the data, at the "txser" input pin, on the rising edge of "txinclk". interfacing the "transmit payload data input in- terface" block (of the XRT72L13) to the terminal equipment for mode 2 operation figure 65 presents an illustration of the "transmit payload data input interface" block (within the XRT72L13) being interfaced to the terminal equip- ment, for "mode 2" operation. mode 2, operation of the terminal equipment as shown in figure 65 , both the terminal equipment and the XRT72L13 will be driven by an external 44.736mhz clock signal. the terminal equipment will receive the 44.736mhz clock signal via its "ds3_clock_in" input pin, and the XRT72L13 framer ic will receive the 44.736mhz clock signal via the "txinclk" input pin. the terminal equipment will serially output the "pay- load data" of the "outbound" ds3 data stream, via the "ds3_data_out" output pin, upon the rising edge of the signal at the "ds3_clock_in" input pin. (note: the "ds3_data_out" output pin of the terminal equipment is electrically connected to the "txser" in- put pin). the XRT72L13 framer ic will latch the data, residing on the "txser" input line, on the rising edge of the "txinclk" signal. in this case, the terminal equipment has the respon- sibility of providing the "framing reference" signal by pulsing its "tx_start_of_frame" output signal (and in f igure 65. i llustration of the "t erminal e quipment " being interfaced to the "t ransmit p ayload d ata i nput i nterface " block ( of the XRT72L13) for m ode 2 (s erial /l ocal -t imed /f rame -s lave ) o peration terminal equipment XRT72L13 ds3 framer ds3_data_out ds3_clock_in tx_start_of_frame ds3_overhead_ind txser txinclk txframeref txoh_ind nibint 44.736 mhz clock source ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 239 turn, the "txframeref" input pin of the XRT72L13), "high" for one-bit period, coincident with the first bit of a new ds3 frame. once the XRT72L13 detects the rising edge of the input at its "txframeref" input pin; it will begin generation of a new ds3 frame. n otes : 1. in this case, the terminal equipment is controlling the "start" of frame generation, and is therefore referred to as the "frame master". conversely, since the XRT72L13 does not control the genera- tion of a new ds3 frame, but is rather driven by the "terminal equipment". hence, the XRT72L13 is referred to as the "frame slave". 2. if the user opts to configure the XRT72L13 to oper- ate in mode 2, it is imperative that the "tx_start_of_frame" (or "txframeref") signal is synchronized to the "txinclk" input clock signal. finally, the XRT72L13 will pulse its "txoh_ind" out- put pin, one bit-period prior to it processing a given "overhead" bit, within the "outbound" ds3 frame. since the "txoh_ind" output pin (of the XRT72L13) is electrically connected to the "ds3_overhead_ind"; whenever the XRT72L13 pulses the "txoh_ind" out- put pin "high", it will also be driving the "ds3_overhead_ind" input pin (of the terminal equipment) "high". whenever the terminal equip- ment detects this pin toggling "high", it should delay transmission of the very next "ds3 frame" payload bit by one clock cycle. the behavior of the signals between the XRT72L13 and the terminal equipment for ds3 mode 2 opera- tion is illustrated in figure 66 . how to configure the XRT72L13 to operate in this mode. 1. set the "nibintf" input pin "low". 2. set the "timrefsel[1:0] bit-fields (within the "framer operating mode register") to "01" as depicted below. f igure 66. b ehavior of the "t erminal i nterface " signals between the XRT72L13 and the t erminal e quipment (m ode 2 o peration ) terminal equipment signals ds3_clock_in ds3_data_out tx_start_of_frame ds3_overhead_ind XRT72L13 transmit payload data i/f signals txinclk txser txframeref txoh_ind payload[4702] payload[4703] x-bit payload[1] payload[4702] payload[4703] x-bit payload[1] note: x-bit will not be processed by the transmit payload data input interface. ds3 frame number n ds3 frame number n + 1 note: txframe pulses high to denote ds3 frame boundary. note: txoh_ind pulses high to denote overhead data (e.g., the x-bit). XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 240 3. interface the XRT72L13, to the terminal equip- ment, as illustrated in figure 65 . 4.2.1.3 mode 3 - the "serial/local-timed/ frame-master" mode behavior of the XRT72L13 if the XRT72L13 has been configured to operate in this mode, then the XRT72L13 will function as fol- lows. a. local timing - (uses the "txinclk" signal as the timing reference) in this mode, the transmit section of the XRT72L13 will use the "txinclk" signal as its timing reference. b. serial mode the XRT72L13 will receive the ds3 payload data, in a serial manner, via the "txser" input pin. the "transmit payload data input interface" (within the XRT72L13) will latch this data into its circuitry, on the rising edge of the "txinclk" input clock signal. c. delineation of "outbound" ds3 frames (frame master mode) the transmit section of the XRT72L13 will use the "txinclk" signal as its timing reference, and will ini- tiate ds3 frame generation, asynchronously with re- spect to any externally applied signal. the XRT72L13 will pulse its "txframe" output pin "high" whenever its it processing the very last bit-field within a given ds3 frame. d. sampling of payload data, from the terminal equipment in mode 3, the XRT72L13 will sample the data, at the "txser" input pin, on the rising edge of "txinclk". interfacing the "transmit payload data input in- terface" block (of the XRT72L13) to the terminal equipment for mode 3 operation figure 67 presents an illustration of the "transmit payload data input interface" block (within the XRT72L13) being interfaced to the terminal equip- ment, for "mode 3" operation. operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 1 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 241 mode 3 operation of the terminal equipment in figure 67 , both the terminal equipment and the XRT72L13 are driven by an external 44.736mhz clock signal. this clock signal is connected to the "ds3_clock_in" input of the terminal equipment; and the "txinclk" input pin of the XRT72L13. the terminal equipment will serially output the pay- load data on its "ds3_data_out" output pin, upon the rising edge of the signal at the "ds3_clock_in" input pin. similarly, the XRT72L13 will latch the data, resid- ing on the "txser" input pin, on the rising edge of "tx- inclk". the XRT72L13 will pulse the "txframe" output pin "high" for one bit-period, coincident while it is pro- cessing the last bit-field within a given "outbound" ds3 frame. the terminal equipment is expected to monitor the "txframe" signal (from the XRT72L13) and to place the first bit, within the very next "out- bound" ds3 frame on the "txser" input pin. (note: in this case, the XRT72L13 dictates exactly when the very next ds3 frame will be generated. the terminal equipment is expected to respond appropriately by providing the XRT72L13 with the first bit of the new ds3 frame, upon demand. hence, in this mode, the XRT72L13 is referred to as the "frame master" and the "terminal equipment" is referred to as the "frame slave". finally, the XRT72L13 will pulse its "txoh_ind" out- put pin, one bit-period prior to it processing a given "overhead" bit, within the "outbound" ds3 frame. since the "txoh_ind" output pin (of the XRT72L13) is electrically connected to the "ds3_overhead_ind"; whenever the XRT72L13 pulses the "txoh_ind" out- put pin "high", it will also be driving the "ds3_overhead_ind" input pin (of the terminal equipment) "high". whenever the terminal equip- ment detects this pin toggling "high", it should delay transmission of the very next "ds3 frame" payload bit by one clock cycle. the behavior of the signal between the XRT72L13 and the terminal equipment for ds3 mode 3 opera- tion is illustrated in figure 68 . f igure 67. i llustration of the "t erminal e quipment " being interfaced to the "t ransmit p ayload d ata i nput i nterface " block ( of the XRT72L13) for m ode 3 (s erial /l ocal -t imed /f rame -m aster ) o peration terminal equipment XRT72L13 ds3 framer ds3_data_out ds3_clock_in tx_start_of_frame ds3_overhead_ind txser txinclk txframe txoh_ind nibint 44.736 mhz clock source XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 242 how to configure the XRT72L13 to operate in this mode. 1. set the "nibintf" input pin "low". 2. set the "timrefsel[1:0] bit-fields (within the "framer operating mode register") to "10 or 11" as depicted below. 3. interface the XRT72L13, to the terminal equip- ment, as illustrated in figure 67 . 4.2.1.4 mode 4 - the "nibble-parallel/loop- timed" mode behavior of the XRT72L13 if the XRT72L13 has been configured to operate in this mode, then the XRT72L13 devide will behave as follows. a. looped timing (uses the rxlineclk as the timing reference) f igure 68. b ehavior of the t erminal i nterface signals between the XRT72L13 and the t erminal e quipment (ds3 m ode 3 o peration ) terminal equipment signals ds3_clock_in ds3_data_out tx_start_of_frame ds3_overhead_ind XRT72L13 transmit payload data i/f signals txinclk txser txframe txoh_ind payload[4702] payload[4703] x-bit payload[1] payload[4702] payload[4703] x-bit payload[1] note: x-bit will not be processed by the transmit payload data input interface. ds3 frame number n ds3 frame number n + 1 note: txframe pulses high to denote ds3 frame boundary. note: txoh_ind pulses high to denote overhead data (e.g., the x-bit). operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 1 x ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 243 in this mode, the transmit section of the XRT72L13 will use the "rxlineclk" signal as its timing reference. when the XRT72L13 is operating in the "nibble- mode", it will "internally" divide the rxlineclk signal, by a factor of four (4) and will output this signal via the "txnibclk" output pin. b. nibble-parallel mode the XRT72L13 will accept the "ds3" payload data, from the terminal equipment in a "nibble-parallel" manner, via the txnib[3:0] input pins. the "transmit terminal equipment input interface" block will latch this data into its circuitry, on the rising edge of the tx- nibclk output signal. c. delineation of the "outbound" ds3 frames the XRT72L13 will pulse the "txnibframe" output pin "high" for one bit-period; coincident with the XRT72L13 processing the last nibble of a given ds3 frame. d. sampling of payload data, from the terminal equipment in mode 4, the XRT72L13 will sample the data, at the txnib[3:0] input pins, on the third rising edge of the "rxoutclk" clock signal, following a pulse in the "tx- nibclk" signal (see figure 70 ). n ote : the "txnibclk" signal, from the XRT72L13; oper- ates nominally at 11.184 mhz (e.g., 44.736 mhz divided by 4). however, for reasons described below, "txnibclk" effectively operates at a lower clock frequency. the trans- mit payload data input interface is only used to accept the payload data, which is intended to be carried by "outbound" ds3 frames. the transmit payload data input interface is not designed to accommodate the entire ds3 data stream. the ds3 frame consists of 4704 payload bits or 1176 nibbles. therefore, the XRT72L13 will supply 1176 "txnibclk" pulses between the rising edges of two consecutive "txnibframe" pulses. the ds3 frame repetition rate is 9.398khz. hence, 1176 "txnibclk" pulses for each ds3 frame period amounts to "txnib- clk" running at approximately 11.052 mhz. the method by which the 1176 "txnibclk" pulses are dis- tributed throughout the ds3 frame period is present- ed below. nominally, the "transmit section" within the XRT72L13 will generate a "txnibclk" pulse for every 4 "rxoutclk" (or "txinclk") periods. however, in 14 cases (within a ds3 frame period), the transmit pay- load data input interface will allow 5 "txinclk" peri- ods to occur between two consecutive "txnibclk" pulses. interfacing the "transmit payload data input in- terface" block (of the XRT72L13) to the terminal equipment for mode 4 operation figure 69 presents an illustration of the "transmit payload data input interface" block (within the XRT72L13) being interfaced to the terminal equip- ment, for "mode 4" operation. mode 4 operation of the terminal equipment when the XRT72L13 is operating in this mode, it will function as the source of the 11.184mhz (e.g., the 44.736mhz clock signal divided by "4") clock signal; that will be used as the "terminal equipment" inter- face clock by both the XRT72L13 and the terminal equipment. the terminal equipment will output the payload data of the "outbound" ds3 data stream via its "ds3_data_out[3:0]" pins on the rising edge of the "11.184mhz clock signal at the "ds3_nib_clock_in" input pin. the XRT72L13 will latch the "outbound" ds3 data stream (from the terminal equipment) on the rising edge of the "txnibclk" output clock signal. the f igure 69. i llustration of the "t erminal e quipment " being interfaced to the "t ransmit p ayload d ata i nput i nterface " block ( of the XRT72L13) for m ode 4 (n ibble -p arallel /l oop -t imed ) o peration terminal equipment XRT72L13 ds3 framer ds3_data_out[3:0 ] ds3_nib_clock_in tx_start_of_fram txnib[3:0] txnibclk txnibframe nibint vcc 4 rxlineclk 44.736mhz 11.184mhz XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 244 XRT72L13 will indicate that it is processing the last nibble, within a given ds3 frame, by pulsing its "tx- nibframe" output pin "high" for one "txnibclk" clock period. when the terminal equipment detects a pulse at its "tx_start_of_frame" input pin, it is ex- pected to transmit the first nibble, of the very next "outbound" ds3 frame" to the XRT72L13 via the "ds3_data_out[3:0]" (or "txnib[3:0]" pins). finally, for the "nibble-parallel" mode operation, the XRT72L13 will continuously pull the "txohind" out- put pin "low". the behavior of the signals between the XRT72L13 and the terminal equipment for "ds3 mode 4" opera- tion is illustrated in figure 70 . how to configure the XRT72L13 into mode 4 1. set the "nibintf" input pin "high". 2. set the timrefsel[1:0] bit-fields (within the "framer operating mode" register) to "00" as illustrated below. f igure 70. b ehavior of the t erminal i nterface signals between the XRT72L13 and the t erminal e quipment (m ode 4 o peration ) terminal equipment signals XRT72L13 transmit payload data i/f signals ds3 frame number n ds3 frame number n + 1 note: txnibframe pulses high to denote ds3 frame boundary. rxoutclk tx_start_of_frame ds3_nib_clock_in ds3_data_out[3:0] nibble [1175] nibble [0] rxoutclk txnibframe txnibclk txnib[3:0] nibble [1175] nibble [0] sampling edge of XRT72L13 device operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 0 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 245 3. interface the XRT72L13, to the terminal equip- ment, as illustrated in figure 69 . n ote : the XRT72L13 framer ic cannot support the framer local loop-back mode of operation. the user must configure the XRT72L13 framer ic into any of the fol- lowing modes, prior to configuring the framer local-loop- back mode operation. ? mode 2 - serial/local-timed/frame-slave mode. ? mode 3 - serial/local-timed/frame-master mode. ? mode 5 - nibble-parallel/local-timed/frame-slave mode. ? mode 6 - nibble-parallel/local-timed/frame-mas- ter mode. for more detailed information on the framer local loop-back mode operation, please see section 6.0. 4.2.1.5 mode 5 - the "nibble-parallel/local- timed/frame-slave" interface mode behavior of the XRT72L13 if the XRT72L13 has been configured to operate in this mode, then the XRT72L13 will function as fol- lows: a. local-timed (uses the "txinclk" signal as the timing reference) in this mode, the transmit section of the XRT72L13 will use the txinclk signal at its timing reference. further, the chip will internally divide the "txinclk" clock signal by a factor of "4" and will output this divid- ed clock signal via the "txnibclk" output pin. the "transmit terminal equipment input interface" block (within the XRT72L13) will use the rising edge of the "txnibclk" signal, to latch the data, residing on the "txnib[3:0] into its circuitry. b. nibble-parallel mode the XRT72L13 will accept the "ds3 payload" data, from the terminal equipment, in a parallel manner, via the "txnib[3:0]" input pins. the "transmit termi- nal equipment input interface" will latch this data into its circuitry, on the rising edge of the "txnibclk" out- put signal. c. delineation of "outbound" ds3 frames the transmit section will use the "txinclk" input sig- nal as its timing reference; and will use the "tx- frameref" input signal as its "framing reference" (e.g., the transmit section of the XRT72L13 initiates frame generation upon the rising edge of the "tx- frameref" signal). n ote : in this case, the terminal equipment should pulse the txframeref input signal (of the XRT72L13 framer ic) coincident with it applying the first payload nibble, within a given outbound ds3 frame. hence, the duration of this pulse should be one nibble-period of the ds3 signal (see figure 33). d. sampling of payload data, from the terminal equipment in mode 5, the XRT72L13 will sample the data, at the "txnib[3:0]" input pins, on the third rising edge of the "txinclk" clock signal, following a pulse in the "txnib- clk" signal (see figure 72 ). n ote : the "txnibclk" signal, from the XRT72L13; oper- ates nominally at 11.184 mhz (e.g., 44.736 mhz divided by 4). however, for reasons described below, "txnibclk" effectively operates at a lower clock frequency. the trans- mit payload data input interface is only used to accept the payload data, which is intended to be carried by "outbound" ds3 frames. the transmit payload data input interface is not designed to accommodate the entire ds3 data stream. the ds3 frame consists of 4704 payload bits or 1176 nibbles. therefore, the XRT72L13 will supply 1176 "txnibclk" pulses between the rising edges of two consecutive "txnibframe" pulses. the ds3 frame repetition rate is 9.398khz. hence, 1176 "txnibclk" pulses for each ds3 frame period amounts to "txnib- clk" running at approximately 11.052 mhz. the method by which the 1176 "txnibclk" pulses are dis- tributed throughout the ds3 frame period is present- ed below. nominally, the "transmit section" within the XRT72L13 will generate a "txnibclk" pulse for every 4 "rxoutclk" (or "txinclk") periods. however, in 14 cases (within a ds3 frame period), the transmit pay- load data input interface will allow 5 "txinclk" peri- ods to occur between two consecutive "txnibclk" pulses. interfacing the "transmit payload data input in- terface" block (of the XRT72L13) to the terminal equipment for mode 5 operation figure 71 presents an illustration of the "transmit payload data input interface" block (within the XRT72L13) being interfaced to the terminal equip- ment, for "mode 5" operation. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 246 mode 5 operation of the terminal equipment in figure 71 both the terminal equipment and the XRT72L13 will be driven by an external 11.184mhz clock signal. the terminal equipment will receive the 11.184mhz clock signal via the "ds3_nib_clock_in" input pin. the XRT72L13 will output the 11.184mhz clock signal via the "txnibclk" output pin. the terminal equipment will serially output the data on the "ds3_data_out[3:0]" pins, upon the rising edge of the signal at the "ds3_clock_in" input pin. (note: the "ds3_data_out[3:0]" output pins of the terminal equipment is electrically connected to the "txnib[3:0] input pins.). the XRT72L13 will latch the data, residing on the "txnib[3:0] input pins, on the ris- ing edge of the "txnibclk" signal. in this case, the terminal equipment has the respon- sibility of providing the "framing reference" signal by pulsing the "tx_start_of_frame" output pin (and in turn, the "txframeref" input pin of the XRT72L13) "high" for one bit-period, coincident with the first nib- ble of a new ds3 frame. once the XRT72L13 detects the rising edge of the input at its "txframeref" input pin; it will begin generation of a new ds3 frame. finally, the XRT72L13 will always internally generate the "overhead" bits, when it is operating in both the "ds3" and "nibble-parallel" modes. the XRT72L13 will pull the "txohind" input pin "low". the behavior of the signals between the XRT72L13 and the terminal equipment for ds3 mode 5 opera- tion is illustrated in figure 72 . f igure 71. i llustration of the "t erminal e quipment " being interfaced to the "t ransmit p ayload d ata i nput i nterface " block ( of the XRT72L13) for m ode 5 (n ibble -p arallel /l ocal -t imed /f rame -s lave ) o peration terminal equipment XRT72L13 ds3 framer ds3_data_out[3:0] ds3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txframeref nibint vcc 4 44.736mhz clock source txinclk 11.184mhz ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 247 how to configure the XRT72L13 into mode 5 1. set the "nibintf" input pin "high". 2. set the timrefsel[1:0] bit-fields (within the "framer operating mode" register) to "01" as illustrated below. 3. interface the XRT72L13, to the terminal equip- ment, as illustrated in figure 71 . 4.2.1.6 mode 6 - the "nibble-parallel/txinclk/ frame-master" interface" mode behavior of the XRT72L13 if the XRT72L13 has been configured to operate in this mode, then the XRT72L13 will function as fol- lows: a. local-timed (uses the "txinclk" signal as the timing reference) in this mode, the transmit section of the XRT72L13 will use the txinclk signal at its timing reference. f igure 72. b ehavior of the "t erminal i nterface " signals between the XRT72L13 and the t erminal e quipment (ds3 m ode 5 o peration ) terminal equipment signals XRT72L13 transmit payload data i/f signals ds3 frame number n ds3 frame number n + 1 note: txframeref is pulsed high to denote first nibble within a new ds3 frame txinclk tx_start_of_frame ds3_nib_clock_in ds3_data_out[3:0] nibble [0] nibble [1] txinclk txframeref txnibclk txnib[3:0] nibble [0] nibble [1] nibble [1175] nibble [1175] sampling edge of the XRT72L13 operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 0 1 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 248 further, the chip will internally divide the "txinclk" clock signal by a factor of "4" and will output this divid- ed clock signal via the "txnibclk" output pin. the "transmit terminal equipment input interface" block (within the XRT72L13) will use the rising edge of the "txnibclk" signal, to latch the data, residing on the "txnib[3:0] into its circuitry. b. nibble-parallel mode the XRT72L13 will accept the "ds3 payload" data, from the terminal equipment, in a parallel manner, via the "txnib[3:0]" input pins. the "transmit termi- nal equipment input interface" will latch this data into its circuitry, on the rising edge of the "txnibclk" out- put signal. c. delineation of "outbound" ds3 frames the transmit section will use the "txinclk" input sig- nal as its timing reference; and will initiate the genera- tion of ds3 frames, asynchronous with respect to any external signal. the XRT72L13 will pulse the "tx- frame" output pin "high" whenever it is processing the last nibble, within a given "outbound" ds3 frame. d. sampling of payload data, from the terminal equipment in mode 6, the XRT72L13 will sample the data, at the "txnib[3:0]" input pins, on the third rising edge of the "txinclk" clock signal, following a pulse in the "txnib- clk" signal (see figure 74 ). n ote : the "txnibclk" signal, from the XRT72L13; oper- ates nominally at 11.184 mhz (e.g., 44.736 mhz divided by 4). however, for reasons described below, "txnibclk" effectively operates at a lower clock frequency. the trans- mit payload data input interface is only used to accept the payload data, which is intended to be carried by "outbound" ds3 frames. the transmit payload data input interface is not designed to accommodate the entire ds3 data stream. the ds3 frame consists of 4704 payload bits or 1176 nibbles. therefore, the XRT72L13 will supply 1176 "txnibclk" pulses between the rising edges of two consecutive "txnibframe" pulses. the ds3 frame repetition rate is 9.398khz. hence, 1176 "txnibclk" pulses for each ds3 frame period amounts to "txnib- clk" running at approximately 11.052 mhz. the method by which the 1176 "txnibclk" pulses are dis- tributed throughout the ds3 frame period is present- ed below. nominally, the "transmit section" within the XRT72L13 will generate a "txnibclk" pulse for every 4 "rxoutclk" (or "txinclk") periods. however, in 14 cases (within a ds3 frame period), the transmit pay- load data input interface will allow 5 "txinclk" peri- ods to occur between two consecutive "txnibclk" pulses. interfacing the "transmit payload data input in- terface" block (of the XRT72L13) to the terminal equipment for mode 6 operation figure 73 presents an illustration of the "transmit payload data input interface" block (within the XRT72L13) being interfaced to the terminal equip- ment, for "mode 6" operation. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 249 mode 6, operation of the terminal equipment in figure 73 both the terminal equipment and the XRT72L13 will be driven by an external 11.184mhz clock signal. the teriminal equipment will receive the 11.184mhz clock signal via the "ds3_nib_clock_in" input pin. the XRT72L13 will output the 11.184mhz clock signal via the "txnibclk" output pin. the terminal equipment will serially output the data on the "ds3_data_out[3:0]" pins upon the rising edge of the signal at the "ds3_clock_in" input pin. the XRT72L13 will latch the data, residing on the "txnib[3:0] input pins, on the rising edge of the "tx- nibclk" signal. in this case the XRT72L13 has the responsibility of providing the "framing reference" signal by pulsing the "txframe" output pin (and in turn the "tx_start_of_frame" input pin of the terminal equip- ment) "high" for one bit-period, coincident with the last bit within a given ds3 frame. finally, the XRT72L13 will always internally generate the "overhead" bits, when it is operating in both the "ds3" and "nibble-parallel" modes. the XRT72L13 will pull the "txohind" input pin "low". the behavior of the signals between the XRT72L13 and the terminal equipment for "ds3 mode 6" opera- tion is illustrated in figure 74 . f igure 73. i llustration of the "t erminal e quipment " being interfaced to the "t ransmit p ayload d ata i nput i nterface " block ( of the XRT72L13) for m ode 6 (n ibble -p arallel /l ocal -t imed /f rame -m aster ) o peration terminal equipment XRT72L13 ds3 framer ds3_data_out[3:0] ds3_nib_clock_in tx_start_of_frame txnib[3:0] txnibclk txnibframe nibint vcc 4 44.736mhz clock source txinclk 11.184mhz XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 250 how to configure the XRT72L13 into mode 6 1. set the "nibint" input pin "high". 2. set the "timrefsel[1:0] bit-fields (within the "framer operating mode" register) to "1x" as illustrated below. 3. interface the XRT72L13, to the terminal equip- ment, as illustrated in figure 73 . 4.2.2 the transmit overhead data input inter- face figure 75 presents a simple illustration of the "trans- mit overhead data input interface" block within the XRT72L13. f igure 74. b ehavior of the "t erminal i nterface " signals between the XRT72L13 and the t erminal e quipment (ds3 m ode 6 o peration ) terminal equipment signals XRT72L13 transmit payload data i/f signals ds3 frame number n ds3 frame number n + 1 note: txnibframe pulses high to denote ds3 frame boundary. txinclk tx_start_of_frame ds3_nib_clock_in ds3_data_out[3:0] nibble [1175] nibble [0] txinclk txnibframe txnibclk txnib[3:0] nibble [1175] nibble [0] sampling edge of the XRT72L13 operating mode register (address = 0x00) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1 b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 001010 1 x ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 251 the ds3 frame consists of 4760 bits. of these bits, 4704 bits are "payload" bits and the remaining 56 bits are "overhead" bits. the XRT72L13 has been de- signed to handle and process both the "payload" type and "overhead" type bits for each ds3 frame. within the "transmit section" within the XRT72L13, the "transmit payload data input interface" has been de- signed to handle the "payload" data. likewise, the "transmit overhead data input interface" has been designed to handle and process the overhead bits. the transmit section of the XRT72L13 generates or processes the various overhead bits within the ds3 frame, in the following manner. the frame synchronization overhead bits (e.g., the "f" and "m" bits) the "f" and "m" bits are always internally generated by the "transmit section" of the XRT72L13. these overhead bits are used (by the remote terminal equipment) for frame synchronization purposes. hence, the user cannot insert his/her value for the "f" and "m" bits into the "outbound" ds3 data stream, via the "transmit overhead data input interface". any at- tempt to externally insert values for the f and m bits, will be ignored by the transmit overhead data input interface block. the "performance monitoring" overhead bits (p and cp bits) the p-bits are always internally generated by the transmit section of the XRT72L13. the p bits are used by the remote terminal equipment to perform error-checking/detection of a ds3 data stream, as it is transmitted from one terminal equipment to adja- cent terminal equipment (e.g., point-to-point check- ing). hence, the user cannot insert his/her value for the "p-bits" into the "outbound" ds3 data stream, via the "transmit overhead data input interface". in contrast to p bits, cp bits are used perform er- ror-checking/detection of a ds3 data stream from the source terminal equipment to the sink terminal equipment. in applications where a given ds3 data stream is received via one port, and is output via an- other port; it is necessary that the cp bit-values re- main constant. the only way to insure this to (1) ex- tract out the cp bit values, via the receiving line card and (2) insert these cp-bit values into the out- bound ds3 data stream, via the transmit overhead f igure 75. s imple i llustration of the "t ransmit o verhead d ata i nput i nterface " block transmit overhead data input interface block transmit overhead data input interface block txohframe txohenable txoh txohclk txohins to transmit ds3 framer block XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 252 data input interface block. hence, the transmit overhead data input interface block will permit the user to externally insert the cp bits into the out- bound ds3 data stream. the "alarm" and signaling related overhead bits bits that are used to transport the "alarm" conditions can be either internally generated by the transmit section within the XRT72L13, or can be externally generated and inserted into the "outbound" ds3 data stream, via the transmit overhead data input inter- face. the ds3 frame overhead bits that fall into this category are: ? the "x" bits ? the "feac" bits ? the "febe" bits. the data link related overhead bits the ds3 frame structure also contains bits which can be used to transport "user data link" information and "path maintenance data link" information. the "udl" (user data link) bits are only accessible via the "transmit overhead data input interface. the path maintenance data link (pmdl) bits can either be sourced from the "transmit lapd controller/buff- er" or via the "transmit overhead data input inter- face". table 13 lists the "overhead bits" within the ds3 frame. additionally, this table also indicates whether or not these overhead bits can be sourced by the "transmit overhead data input interface" or not. n otes : * the XRT72L13 contains "mask register bits" that permit the user to alter the state of the internally gen- erated value for these bits. + the transmit lapd controller/buffer can be config- ured to be the source of the dl bits, within the "out- bound" ds3 data stream. in all, the "transmit overhead data input interface" permits the user to insert "overhead data" into the "outbound" ds3 frames via the following two different methods. ? method 1 - using the txohclk clock signal ? method 2 - using the txinclk and the txohen- able signals. each of these methods are described below. 4.2.2.1 4.2.2.1 method 1 - using the txohclk clock signal the "transmit overhead data input interface" con- sists of the five signals. of these five (5) signals, the following four (4) signals are to be used when imple- menting "method 1". ? txoh ? txohclk ? txohframe ? txohins each of these signals are listed and described below. table 14 . t able 13: a l isting of the o verhead bits within the ds3 frame , and their potential sources , within the XRT72L13 o verhead b it i nternally generated a ccessible via the t ransmit o verhead d ata i nput i nterface b uffer /r egister a ccessible pyes no yes* x yes yes yes fyes no yes* myes no yes* feac no yes yes f e b e ye s ye s ye s dl no yes yes+ udl no yes no cp no yes no ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 253 interfacing the "transmit overhead data input in- terface" to the terminal equipment. figure 76 illustrates how one should interface the "transmit overhead data input interface" to the ter- minal equipment, when using "method 1". t able 14: d escription of "m ethod 1" t ransmit o verhead i nput i nterface s ignals n ame t ype d escription txohins input transmit overhead data insert enable input pin. asserting this input signal (e.g., setting it "high") enables the transmit overhead data input inter- face to accept "overhead" data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the "txoh" input pin, on the falling edge of the "txohclk" output signal. conversely, setting this pin "low" configures the "transmit overhead data input interface" to not sample (e.g., ignore) the data at the "txoh" input pin, on the falling edge of the "txohclk" output signal. n ote : if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the "transmit overhead data input interface" (e.g., if the terminal equipment asserts the "txo- hins" signal, at a time when one of these "non-insertable" overhead bits are being processed); that particular insertion effort will be ignored. txoh input transmit overhead data input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the "overhead" bit position within the very next "outbound" ds3 frame. if the "txohins" pin is pulled "high", the transmit overhead data input interface will sample the data at this input pin (txoh), on the falling edge of the "txohclk" output pin. conversely, if the "txohins" pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. txohclk output transmit overhead input interface clock output signal: this output signal serves two purposes: 1. the transmit overhead data input interface will provide a rising clock edge on this signal, one bit-period prior to the instant that the "transmit overhead data input interface" is processing an overhead bit. 2. the transmit overhead data input interface will sample the data at the txoh input, on the fall- ing edge of this clock signal (provided that the txohins input pin is "high"). n ote : the transmit overhead data input interface will supply a clock edge for all overhead bits within the ds3 frame (via the txohclk output signal). this includes those overhead bits that the "transmit overhead data input interface" will not accept from the terminal equipment. txohframe output transmit overhead input interface frame boundary indicator output: this output signal pulses "high" when the XRT72L13 is processing the last bit within a given ds3 frame. the purpose of this output signal is to alert the terminal equipment that the transmit overhead data input interface block is about to begin processing the overhead bits for a new ds3 frame. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 254 method 1 operation of the terminal equipment if the terminal equipment intends to insert any over- head data into the "outbound" ds3 data stream, (via the transmit overhead data input interface), then it is expected to do the following. 1. to sample the state of the "txohframe" signal (e.g., the "tx_start_of_frame" input signal) on the rising edge of the "txohclk" (e.g., the "ds3_oh_clock_in" signal). 2. to keep track of the number of rising clock edges that have occurred, via the "txohclk" (e.g., the "ds3_oh_clock_in" signal) since the last time the "txohframe" signal was sampled "high". by doing this the terminal equipment will be able to keep track of which overhead bit is being pro- cessed by the transmit overhead data input interface block at any given time. when the ter- minal equipment knows which overhead bit is being processed, at a given txohclk period, it will know when to insert a desired overhead bit value into the outbound ds3 data stream. from this, the terminal equipment will know when it should assert the txohins input pin and place the appropriate value on the txoh input pin (of the XRT72L13). table 15 relates the number of rising clock edges (in the "txohclk" signal, since "txohframe" was sam- pled "high") to the ds3 overhead bit, that is being processed. f igure 76. i llustration of the "t erminal e quipment " being interfaced to the "t ransmit o verhead d ata i nput i nterface " (m ethod 1) terminal equipment XRT72L13 ds3 framer ds3_oh_out] ds3_oh_clock_in tx_start_of_frame txohclk txohframe txohins 44.736 mhz clock source txinclk txoh insert_oh rxlineclk 44.736 mhz clock source ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 255 t able 15: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since "t x ohf rame " was last sampled " high ") to the ds3 o verhead b it , that is being processed n umber of r ising c lock e dges in t x ohc lk t he o verhead b it e xpected by the "XRT72L13" c an this overhead bit be accepted by the XRT72L13? 0 (clock edge is coincident with txo- hframe being detected high) x ye s 1 f1 no 2 aic ye s 3 f0 no 4 na ye s 5 f0 no 6 feac ye s 7 f1 no 8 x ye s 9 f1 no 10 udl ye s 11 f0 no 12 udl ye s 13 f0 no 14 udl ye s 15 f1 no 16 p no 17 f1 no 18 cp ye s 19 f0 no 20 cp ye s 21 f0 no 22 cp ye s 23 f1 no 24 p no 25 f1 no 26 febe ye s 27 f0 no 28 febe ye s 29 f0 no XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 256 3. after the terminal equipment has waited the appropriate number of clock edges (from the "txohframe" signal being sampled "high"), it should assert the "txohins" input signal. con- currently, the terminal equipment should also place the appropriate value (of the inserted over- head bit) onto the "txoh" signal. 4. the terminal equipment should hold both the "txohins" input pin "high" and the value of the "txoh" signal, stable until the next rising edge of "txohclk" is detected. case study: the terminal equipment intends to insert the appropriate overhead bits into the "transmit overhead data input interface" (using 30 febe ye s 31 f1 no 32 m0 no 33 f1 no 34 dl ye s 35 f0 no 36 dl ye s 37 f0 no 38 dl ye s 39 f1 no 40 m1 no 41 f1 no 42 udl ye s 43 fo no 44 udl ye s 45 fo no 46 udl ye s 47 f1 no 48 m0 no 49 f1 no 50 udl ye s 51 f0 no 52 udl ye s 53 f0 no 54 udl ye s 55 f1 no t able 15: t he r elationship between the n umber of r ising c lock e dges in t x ohc lk , ( since "t x ohf rame " was last sampled " high ") to the ds3 o verhead b it , that is being processed n umber of r ising c lock e dges in t x ohc lk t he o verhead b it e xpected by the "XRT72L13" c an this overhead bit be accepted by the XRT72L13? ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 257 method 1) in order to transmit a "yellow alarm" to the remote terminal equipment. in this example, the terminal equipment intends to in- sert the appropriate overhead bits, into the "transmit overhead data input interface", such that the XRT72L13 will transmit a "yellow alarm" to the re- mote terminal equipment. recall that, for ds3 appli- cations, a "yellow alarm" is transmitted by setting both of the "x" bits (within each outbound ds3 frame) to "0". if one assumes that the connection between the ter- minal equipment and the XRT72L13 are as illustrated in figure 76 then figure 77 presents an illustration of the signaling that must go on between the terminal equipment and the XRT72L13. in figure 77 the terminal equipment samples the "txohframe" signal being "high" at "rising clock edge # 0". at this point, the terminal equipment knows that the XRT72L13 is just about to process the very first overhead bit within a given "outbound" ds3 frame. additionally, according to table 15 , the very first overhead bit to be processed is the first "x" bit. in order to facilitate the transmission of the "yellow alarm", the terminal equipment must set this "x" bit to "0". hence, the terminal equipments starts this process by implementing the following steps concur- rently. a. assert the "txohins" input pin by setting it "high". b. set the "txoh" input pin to "0". after the terminal equipment has applied these sig- nals, the XRT72L13 will sample the data on both the "txohins" and "txoh" signals upon the very next falling edge of "txohclk" (designated at "0-" in figure 77 . once the XRT72L13 has sampled this data, it will then insert a "0" into the first "x" bit posi- tion, in the "outbound" ds3 frame. f igure 77. i llustration of the signal that must occur between the t erminal e quipment and the XRT72L13, in order to configure the XRT72L13 to transmit a "y ellow a larm " to the " remote termi - nal equipment " terminal equipment/XRT72L13 interface signals txohclk txohins txohframe txoh remaining overhead bits with ds3 frame x bit = 0 x bit = 0 txohframe is sample high terminal equipment asserts txohins and data on txoh line XRT72L13 device samples the txohins and txoh signals. txohframe is sample high terminal equipment asserts txohins and data on txoh line XRT72L13 samples the txohins and txoh signals. 0 0- 1 2 3 4 5 6 7 8 8- XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 258 upon detection of the very next rising edge of the "tx- ohclk" clock signal (designated as "clock edge 1" in figure 77 ), the terminal equipment will negate the "txohins" signal (e.g., toggles it "low") and will cease inserting data into the "transmit overhead data input interface", until "rising clock edge # 8" (of the "txo- hclk" signal). according to table 15 , "rising clock edge # 8" indicates that the XRT72L13 is just about ready to process the second "x" bit within the "out- bound" ds3 frame. once again, in order to facilitate the transmission of the "yellow alarm" this "x-bit" must also be set to "0". hence, the terminal equip- ment will (once again) implement the following steps, concurrently. a. assert the "txohins" input pin by setting it "high". b. set the "txoh" input to "0". once again, after the terminal equipment has ap- plied these signals these signals; the XRT72L13 will sample the data on both the "txohins" and "txoh" signal upon the very next falling edge of "txohclk" (designated as "8-" in figure 77 ). once the XRT72L13 has sampled this data, it will then insert a "0" into the second "x" bit position, in the "outbound" ds3 frame. 4.2.2.2 method 2 - using the txinclk and txo- henable signals method 1 requires the use of an additional clock sig- nal, "txohclk". however, there may be a situation in which the user does not wish to accommodate and process this extra clock signal to their design, in order to use the "transmit overhead data input interface". hence, method 2 is available. when using "method 2", either the "txinclk" or "rxoutclk" signal is used to sample the "overhead" bits and signals which are input to the "transmit overhead data input interface. method 2 involves the use of the following signals: ? txoh ? txinclk ? txohframe ? txohenable each of these signals are listed and described in table 16 . t able 16: d escription of "m ethod 2" t ransmit o verhead i nput i nterface s ignals n ame t ype d escription txohenable output transmit overhead data enable output pin the XRT72L13 will assert this signal, for one txinclk period, just prior to the instant that the "transmit overhead data input interface" is processing an overhead bit. txohframe output transmit overhead input interface frame boundary indicator output: this output signal pulses "high" when the XRT72L13 is processing the last bit within a given ds3 frame. txohins input transmit overhead data insert enable input pin. asserting this input signal (e.g., setting it "high") enables the transmit overhead data input inter- face to accept "overhead" data from the terminal equipment. in other words, while this input pin is "high", the transmit overhead data input interface will sample the data at the "txoh" input pin, on the falling edge of the "txinclk" output signal. conversely, setting this pin "low" configures the "transmit overhead data input interface" to not sample (e.g., ignore) the data at the "txoh" input pin, on the falling edge of the "txohclk" output signal. n ote : if the terminal equipment attempts to insert an overhead bit that cannot be accepted by the "transmit overhead data input interface" (e.g., if the terminal equipment asserts the "txo- hins" signal, at a time when one of these "non-insertable" overhead bits are being processed); that particular insertion effort will be ignored. txoh input transmit overhead data input pin: the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the "overhead" bit position within the very next "outbound" ds3 frame. if the "txohins" pin is pulled "high", the transmit overhead data input interface will sample the data at this input pin (txoh), on the falling edge of the "txohclk" output pin. conversely, if the "txohins" pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 259 interfacing the "transmit overhead data input interface to the terminal equipment figure 78 illustrates how one should interface the "transmit overhead data input interface" to the ter- minal equipment when using method 2. method 2 operation of the terminal equipment if the terminal equipment intends to insert any over- head data into the "outbound" ds3 data stream (via the transmit overhead data input interface), then it is expected to do the following. 1. to sample the state of both the "txohframe" and the "txohenable" input signals, via the "ds3_clock_in" (e.g., either the txinclk or the rxoutclk signal of the XRT72L13) signal. if the terminal equipment samples the "txohenable" signal "high"; then it knows that the XRT72L13 is about to process an overhead bit. further, if the terminal equipment samples both the "txo- hframe" and the "txohenable" pins "high" (at the same time) then the terminal equipment knows that the XRT72L13 is about to process the first overhead bit, within a new ds3 frame. 2. to keep track of the number of times that the "txohenable" signal has been sampled "high" since the last time both the "txohframe" and the "txohenable" signals were sampled "high". by doing this, the terminal equipment will be able to keep track of which overhead bit the "transmit overhead data input interface" is about ready to process. from this, the terminal equipment will know when it should assert the "txohins" input pin and place the appropriate value on the "txoh" input pins (of the XRT72L13). table 17 also relates the number of "txohenable" output pulses (that have occurred since both the "tx- ohframe" and "txohenable" pins were sampled "high") to the ds3 overhead bit, that is being pro- cessed. f igure 78. i llustration of the "t erminal e quipment " being interfaced to the "t ransmit o verhead d ata i nput i nterface " (m ethod 2) terminal equipment XRT72L13 ds3 framer ds3_oh_out ds3_oh_enable tx_start_of_frame txohenable txohframe txohins 44.736 mhz clock source txinclk txoh insert_oh rxlineclk 44.736 mhz clock source ds3_clock_in XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 260 t able 17: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the ds3 o verhead b it , that is being processed by the XRT72L13 n umber of t x ohe nable p ulses t he o verhead b it e xpected by the "XRT72L13" c an this overhead bit be accepted by the XRT72L13? 0 (the txohenable and txo- hframe signals are both sampled high) x ye s 1 f1 no 2 aic ye s 3 f0 no 4 na ye s 5 f0 no 6 feac ye s 7 f1 no 8 x ye s 9 f1 no 10 udl ye s 11 f0 no 12 udl ye s 13 f0 no 14 udl ye s 15 f1 no 16 p no 17 f1 no 18 cp ye s 19 f0 no 20 cp ye s 21 f0 no 22 cp ye s 23 f1 no 24 p no 25 f1 no 26 febe ye s 27 f0 no 28 febe ye s ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 261 3. after the terminal equipment has waited through the appropriate number of pulses via the "txo- henable" pin, it should then assert the "txohins" input signal. concurrently, the terminal equip- ment should also place the appropriate value (of the inserted overhead bit) onto the "txoh" sig- nal. 4. the terminal equipment should hold both the "txohins" input pin "high" and the value of the "txoh" signal stable, until the next "txohen- able" pulse is detected. 29 f0 no 30 febe ye s 31 f1 no 32 m0 no 33 f1 no 34 dl ye s 35 f0 no 36 dl ye s 37 f0 no 38 dl ye s 39 f1 no 40 m1 no 41 f1 no 42 udl ye s 43 fo no 44 udl ye s 45 fo no 46 udl ye s 47 f1 no 48 m0 no 49 f1 no 50 udl ye s 51 f0 no 52 udl ye s 53 f0 no 54 udl ye s 55 f1 no t able 17: t he r elationship between the n umber of t x ohe nable pulses ( since the last occurrence of the t x ohf rame pulse ) to the ds3 o verhead b it , that is being processed by the XRT72L13 n umber of t x ohe nable p ulses t he o verhead b it e xpected by the "XRT72L13" c an this overhead bit be accepted by the XRT72L13? XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 262 case study: the terminal equipment intends to insert the appropriate overhead bits into the "transmit overhead data input interface" (using method 2) in order to transmit a "yellow alarm" to the remote terminal equipment. in this case, the terminal equipment intends to insert the appropriate overhead bits, into the "transmit overhead data input interface" such that the XRT72L13 will transmit a "yellow alarm" to the re- mote terminal equipment. recall that, for ds3 appli- cations, a "yellow alarm" is transmitted by setting all of the "x" bits to "0". if one assumes that the connection between the ter- minal equipment and the XRT72L13s are as illustrat- ed in figure 78 then, figure 79 presents an illustra- tion of the signaling that must go on between the ter- minal equipment and the XRT72L13. 4.2.3 the transmit ds3 hdlc controller the transmit ds3 hdlc controller block can be used to transport either "bit-oriented signaling (bos) or "message-oriented signaling" (mos) type mes- sages or both types of messages to the remote termi- nal equipment. both bos and mos types of hdlc message processing are discussed in detail below. 4.2.3.1 bit-oriented signaling (or feac mes- sage) processing via the "transmit ds3 hdlc controller". the "transmit ds3 hdlc controller" block consists of two major blocks: ? the "transmit feac processor. ? the "lapd transmitter". this section describes how to operate the "transmit feac processor". if the transmit ds3 framer is op- erating in the "c-bit parity" framing format then the feac (far-end alarm & control) bit-field of the ds3 frame can be used to transmit the feac messages (see figure 42). the feac code word is a 6-bit val- ue which is encapsulated by 10 framing bits, forming a 16-bit feac message of the form: f igure 79. b ehavior of "t ransmit o verhead d ata i nput i nterface " signals between the XRT72L13 and the t erminal e quipment ( for m ethod 2) txinclk txohframe txohenable txohins txoh terminal equipment samples txohframe and txohenable being high terminal equipment responds by asserting txohins and placing desired data on txoh. XRT72L13 samples txoh here. txohenable pulse # 8 x bit = 0 x bit = 0 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 263 where '[d5, d4, d3, d2, d1, d0]' is the feac code word. the rightmost bit (e.g., a "1") of the feac message, is transmitted first. since each ds3 frame contains only 1 feac bit, 16 ds3 frames are re- quired to transmit the 16 bit feac code message. the XRT72L13 contains the following two registers that support feac message transmission. ? tx ds3 feac register (address = 0x32) ? tx ds3 feac configuration and status register (address = 0x33) operating the transmit feac processor in order to transmit a feac message to the "remote terminal", the user must execute the following steps. 1. write the 6-bit feac code (to be sent) into the "tx ds3 feac" register. 2. enable the transmit feac processor. 3. initiate the transmission of the feac message. each of these steps will be described in detail below. step 1 - writing in the six bit feac codeword (to be sent) in this step, the p/c writes the six bit feac code word into the "tx ds3 feac" register. the bit for- mat of this register is presented below. step 2 - enabling the transmit feac processor in order to enable the transmit feac processor (within the transmit ds3 hdlc controller block) the user must write a "1" into bit 2 (tx feac enable) within the "tx ds3 feac configuration and status" register, as depicted below. at this point, the "transmit feac processor" can be commanded to begin transmission (see step 3). step 3 - initiate the transmission of the feac message the user can initiate the transmission of the feac code word (residing in the "tx ds3 feac" register) by writing a "1" to bit 1 (tx feac go) within the "tx ds3 feac configuration and status" register, as de- picted below. n ote : while executing this particular write operation, the user should write the binary value "000xx110b" into the "tx ds3 feac configuration and status" register. by doing this the user insures that a "1" is also being written to bit 2 0 d5 d4 d3 d2 d1 d0011111111 tx ds3 feac register (address = 0x32) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1b it 0 not used txfeac[5] txfeac[4] txfeac[3] txfeac[2] txfeac[1] txfeac[0] not used ro r/w r/w r/w r/w r/w r/w r0 0 d5 d4 d3 d2 d1 d0 0 transmit ds3 feac configuration and status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 not used txfeac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w ro r/w r/w r0 xxxxx 1xx transmit ds3 feac configuration and status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 not used not used not used txfeac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w ro r/w r/w r0 xxxxx1 1x XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 264 (tx feac enable) of the register, in order to keep the "transmit feac processor" enabled. once this step has been completed, the transmit feac processor will proceed to transmit the 16 bit feac code via the outbound ds3 frames. this 16 bit feac message will be transmitted repeatedly 10 consecutive times. hence, this process will require a total of 160 ds3 frames. during this process the "tx feac busy" bit (bit 0, within the "transmit ds3 feac configuration and status" register) will be asserted, indicating that the tx feac processor is currently transmitting the feac message to the "remote" ter- minal. this bit-field will toggle to "0" upon completion of the 10th transmission of the feac code message. the transmit feac processor will generate an inter- rupt (if enabled) to the local p/c, upon completion of the 10th transmission of the feac message. the purpose of having the framer ic generating this inter- rupt is to let the local p/c know that the transmit feac processor is now available and ready to trans- mit a new feac message. finally, once the transmit feac processor has completed its 10th transmission of a feac code message it will then begin sending all "1s" in the feac bit-field of each ds3 frame. the receive feac processor (at the remote terminal equipment) will interpret this "all 1s" message as an "idle" feac message. the transmit feac proces- sor will continue sending all "1"s in the feac bit field, for an indefinite period of time, until the local p/c commands it to transmit a new feac message. figure 80 presents a flow chart depicting how to use the transmit feac processor. for a detailed description of the receive feac pro- cessor (within the receive ds3 hdlc controller block), please see section 3.3.3.1. 4.2.3.2 message-oriented signaling (e.g., lap-d) processing via the "transmit ds3 hdlc controller" f igure 80. a f low c hart depicting how to transmit a feac m essage via the feac t ransmitter start start write six-bit outbound feac value into the txds3 feac register this register is located at address 0x1d. write six-bit outbound feac value into the txds3 feac register this register is located at address 0x1d. enable the transmit feac processor. this is accomplished by writing xxxx x1xx into the txds3 feac configuration & status register enable the transmit feac processor. this is accomplished by writing xxxx x1xx into the txds3 feac configuration & status register initiate transmission of the outbound feac message. this is accomplished by writing xxxx xx1x into the txds3 feac configuration & status register. initiate transmission of the outbound feac message. this is accomplished by writing xxxx xx1x into the txds3 feac configuration & status register. transmit feac processor encapsulates the outbound feac value into a 16 bit framing structure . transmit feac processor encapsulates the outbound feac value into a 16 bit framing structure . transmit feac processor proceeds to insert the 16-bit message (in a bit-by-bit manner) into the feac bit-fields of each outbound ds3 frame. transmit feac processor proceeds to insert the 16-bit message (in a bit-by-bit manner) into the feac bit-fields of each outbound ds3 frame. is transmission of the 16 bit feac message complete ? is transmission of the 16 bit feac message complete ? has the 16-bit feac message been transmitted to the remote terminal 10 times ? has the 16-bit feac message been transmitted to the remote terminal 10 times ? generate the transmit feac interrupt generate the transmit feac interrupt invoke the transmit feac interrupt service routine. invoke the transmit feac interrupt service routine. 1 1 1 1 no yes no yes ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 265 the lapd transmitter (within the transmit ds3 hdlc controller block) allows the user to transmit path maintenance data link (pmdl) messages to the remote terminal via the "outbound" ds3 frames. in this case the message bits are inserted into and car- ried by the 3 "dl" bit fields of f-frame #5 within each ds3 m-frame. the on-chip lapd transmitter sup- ports both the 76 byte and 82 byte length message formats, and the framer ic allocates 88 bytes of on- chip ram (e.g., the "transmit lapd message" buffer) to store the message to be transmitted. the mes- sage format complies with itu-t q.921 (lap-d) pro- tocol with different addresses and is presented below in figure 81 . where: flag sequence = 0x7e sapi + cr + ea = 0x3c or 0x3e tei + ea = 0x01 control = 0x03 the following sections defines each of these bit/byte- fields within the lapd message frame format. flag sequence byte the flag sequence byte is of the value 0x7e, and is used to for two purposes 1. to denote the boundaries of the lapd message frame, and 2. to function as the idle pattern (e.g., transmit hdlc controller block transmits a continuous stream of flag sequence octets; whenever no lapd message is being transmitted). sapi - service access point identifier the sapi bit-fields are assigned the value of "001111b" or 15 (decimal). tei - terminal endpoint identifier the tei bit-fields are assigned the value of 0x00. the tei field is used in n-isdn systems to identify a terminal out of multiple possible terminal. however, since the framer ic transmits data in a point-to-point manner, the tei value is unimportant. control the control identifies the type of frame being trans- mitted. there are three general types of frame for- mats: information, supervisory, and unnumbered. the framer assigned the control byte the value 0x03. hence, the framer will be transmitting and receiving unnumbered lapd message frames. information payload the "information payload" is the 76 bytes or 82 bytes of data (e.g., the pmdl message) that the user has written into the on-chip "transmit lapd message" buffer (which is located at addresses 0x86 through 0xdd). it is important to note that the user must write in a specific octet value into the first byte position within the transmit lapd message buffer (located at ad- dress = 0x86, within the framer). the value of this octet depends upon the type of lapd message frame/pmdl message that the user wishes to trans- mit. table 18 presents a list of the various types of lapd message frames/pmdl messages that are supported by the XRT72L13 framer device; and the corresponding octet value that the user must write in- to the first octet position within the "transmit lapd message buffer. f igure 81. lapd m essage f rame f ormat flag sequence (8 bits) sapi (6-bits) c/r ea tei (7 bits) ea control (8-bits) 76 or 82 bytes of information (payload) fcs - msb fcs - lsb flag sequence (8-bits) XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 266 frame check sequence bytes the 16 bit fcs (frame check sequence) is calculat- ed over the lapd message header and information payload bytes, by using the crc-16 polynomial, x 16 + x 12 + x 5 + 1. operation of the lapd transmitter if the user wishes to transmit a message via the lapd transmitter, he/she must write the information portion (or the body) of the message into the transmit lapd message buffer, which is located at 0x86 through 0xdd in on-chip ram via the microprocessor interface. afterwards, the user must do three things: 1. specify the length of lapd message to be trans- mitted. 2. enable the lapd transmitter. 3. initiate the transmission of the pmdl message. each of these steps will be discussed in detail. step 1 - specifying the length of the lapd mes- sage the user can transmit one of two different sizes of lapd messages. he/she can accomplish this by writing the appropriate data to bit 1 within the "tx ds3 lapd configuration" register. the bit-format of this register is presented below. the relationship between the contents of bit-fields 1 and the lapd message size is given in table 19 . n ote : the message type selected must correspond with the contents of the first byte of the information (payload) portion, as presented in table 18 . step 2 - enabling the lapd transmitter prior to the transmission of any data via the lapd transmitter, the user must enable the lapd transmit- ter. he/she can accomplish this by writing a "1" to bit 0 of the tx ds3 lapd configuration register, as de- picted below. t able 18: t he lapd m essage t ype and the c orresponding value of the f irst b yte , within the i nformation p ayload lapd m essage t ype v alue of f irst b yte , within i nformation p ayload of m essage m essage s ize cl path identification 0x38 76 bytes idle signal identification 0x34 76 bytes test signal identification 0x32 76 bytes itu-t path identification 0x3f 82 bytes transmit ds3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 not used auto retransmit not used txlapd msg length txlapd enable r/o r/o r/o r/o r/w r/o r/w r/w 0000x0 xx t able 19: r elationship between t x lapd m sg l ength and the lapd m essage s ize t x lapd m sg l ength lapd m essage l ength 0 lapd message size is 76 bytes 1 lapd message size is 82 bytes transmit ds3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 not used auto retransmit not used txlapd msg length txlapd enable r/o r/o r/o r/o r/w r/o r/w r/w ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 267 bit 0 - txlapd enable this bit-field allow the user to enable or disable the lapd transmitter in accordance with table 20 . prior to executing step 2 (enabling the lapd trans- mitter), the lapd transmitter will be disabled and the transmit ds3 framer block will be setting each of the "dl" bits (within the "outbound" ds3 data stream) to "1". after the user executes this step, the lapd transmitter will begin transmitting the "flag sequence" octet (0x7e) via the "dl" bits. n ote : upon power up or reset, the lapd transmitter is disabled. therefore, the user must set this bit to "1" in order to enable the lapd transmitter. step 3 - initiate the transmission at this point, the lapd transmitter is ready to begin transmission. the user has written the "information portion" of the pmdl message into the on-chip trans- mit lapd message buffer. further, the user has specified the type of lapd message that he/she wishes to transmit, and has enabled the lapd trans- mitter. the only thing remaining to do is to initiate the transmission of this message. the user initiates this process by writing a "1" to bit 3 of the tx ds3 lapd status/interrupt register (txdl start). the bit format of this register is presented below. a "0" to "1" transition of bit 3 (txdl start) in this reg- ister, initiates the transmission of the data link mes- sage. while the lapd transmitter is transmitting the message, the 'txdl busy' (bit 2) bit will be set to "1". this bit-field allows the user to "poll" the status of the lapd transmitter. once the message transfer is completed, this bit-field will toggle back to '0'. the user can configure the lapd transmitter to inter- rupt the c/p upon completion of transmission of the lapd message, by setting bit-field 1 (txlapd in- terrupt enable) of the "tx ds3 lapd status/interrupt" register to "1". the purpose of this interrupt is to let the local c/p know that the lapd transmitter is available and ready to transmit a new message. bit 0 will reflect the interrupt status for the lapd transmit- ter. n ote : this bit-field will be reset on reading this register. details associated with the transmission of a pmdl message once the user has invoked the "txdl start" com- mand, the lapd transmitter will do the following. ? generate the four octets of lapd frame header (e.g., flag sequence, sapi, tei, control, etc.) and insert it into the lapd message, prior to the user's information (see the lapd message frame format in figure 81 ). 0000x0x 1 transmit ds3 lapd configuration register (address = 0x33) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 t able 20: r elationship between t x lapd m sg l ength and the lapd m essage s ize t x lapd e nable r esulting a ction of the lapd t ransmitter 0 the lapd transmitter is disabled and the dl bits, in the ds3 frame, are transmitted as all "1"s. 1 the lapd transmitter is enabled and is transmitting a continuous stream of flag sequence octets (0x7e). transmit ds3 lapd status/interrupt register (address = 0x34) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 not used tx dl start tx dl busy txlapd interrupt enable txlapd interrupt status r/o r/o r/o r/o r/w ro r/w rur 0000 1xxx XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 268 ? compute the 16 bit "frame check sum" (fcs) of the lapd message frame (e.g., of the lapd mes- sage header and information payload) and append this value to the lapd message. ? append a "trailer" flag sequence octet to the end of the message lapd (following the 16 bit fcs value). ? serialize the composite lapd message and begin inserting the lapd message into the "dl" bit fields of each outgoing ds3 frame. ? complete the transmission of the frame overhead, payload, fcs value, and trailer flag sequence octet via the transmit ds3 framer. once the lapd transmitter has completed its trans- mission of the lapd message, the framer will gener- ate an interrupt to the local c/p (if enabled). after- wards, the lapd transmitter will proceed to retrans- mit the lapd message, repeatedly at one second in- tervals. during "idle" periods (e.g., in between these transmission of the lapd message), the lapd transmitter will be sending a continuous stream of "flag sequence bytes". the lapd transmitter will continue this behavior until the user has disabled the lapd transmitter by writing a "0" to bit 0 (txlapd enable) within the tx ds3 lapd configuration reg- ister. if the lapd transmitter is idle, then it will con- tinuously send the flag sequence octets (via the "dl" bits of each outbound ds3 frame) to the remote terminal equipment. n ote : in order to prevent the user's data (e.g., the payload portion of the lapd message frame) from mimicking the "flag sequence" byte, the lapd transmitter will insert a "0" into the lapd data stream immediately following the detec- tion of five (5) consecutive "1s" (this "stuffing" occurs only while the information payload is being transmitted). the 'remote' lapd receiver (see section 4.3.3.2) will have the responsibility of "detecting the 5 consecutive "1s" and removing the subsequent "0" from the payload portion of the incoming lapd message. figure 82 presents a flow chart depicting the proce- dure (in 'white boxes') that the user should use in or- der to transmit a lapd message. this figure also in- dicates (via the "shaded" boxes) what the lapd transmitter circuitry will do before and during mes- sage transmission. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 269 the mechanics of transmitting a new lapd mes- sage as mentioned above, after the lapd transmitter has been enabled, and commanded to transmit the mes- sage, residing in the "transmit lapd message" buff- er; it will continue to transmit this message at one- second intervals. if the user wishes to transmit an- other (e.g., different) pmdl message to the "remote" lapd receiver, he/she will have to write this "new" message into the "transmit lapd message" buffer, via the microprocessor interface section of the fram- er. however, the user must be careful when writing in this new message. if he/she writes this message into the "transmit lapd message" buffer at the "wrong time" (with respect to these "one-second" transmis- sions), the user's action could interfere with these transmissions; thereby causing the lapd transmitter to transmit a "corrupted" message to the "remote" lapd receiver. in order to avoid this problem, while writing the new message into the "transmit lapd message" buffer, the user should do the following: 1. configure the framer to automatically reset acti- vated interrupts the user can do this by writing a "1" into bit 3 of the framer operating mode register, as depicted below. f igure 82. f low c hart depict how to use the lapd t ransmitter start write in data link information the user accomplishes this by writing the information that he/she wishes to transmit (via the lapd transmitter) to locations 86h through ddh, within the uni address space. configure the lapd transmitter for transmission this is accomplished by writing 00000xx1b to the tx ds3 lapd configuration register. (where xx dictates lapd message type) start transmission of lapd message this is accomplished by writing 000010x0b to the tx ds3 lapd status/interrupt register. (where x indicates the users choice to enable/disable lapd message transfer complete interrupt lapd transmitter inserts frame header octets in front of the user payload. lapd transmitter computes the 16 bit fcs (a crc-16 value) and inserts it into the lapd message, following the user payload lapd transmitter appends a flag sequence trailer octet to the end of the lapd message (after the 16 bit fcs). is 5 consecutive 1s detected ? is message transmission complete ? insert a 0 after the string of 5 consecutive 1s end generate interrupt lapd transmitter will continue to transmit flag sequence octets. yes no yes no operating mode register (address = 0x00) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 local loop- back mode line loop- back mode internal los enable reset interrupt enable reset frame format timrefsel[1:0] XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 270 this action will prevent the lapd transmitter from generating its own "one-second" interrupts. 2. enable the "one-second" interrupt this can be done by writing a "1" into bit 0 of the block interrupt enable register, as depicted below. 3. write the new message into the "transmit lapd message" buffer immediately after the occur- rence of the "one-second" interrupt. by timing the writes to the "transmit lapd message" buffer to occur immediately after the occurrence of the "one-second" interrupt, the user avoids conflict- ing with the "one-second" transmissions of the lapd message, and will transmit the correct messages to the "remote" lapd receiver. 4.2.4 the transmit ds3 framer block 4.2.4.1 brief description of the transmit ds3 framer the transmit ds3 framer block accepts data from any of the following three sources, and uses it to form the ds3 data stream. ? the transmit payload data input block ? the transmit overhead data input block ? the transmit hdlc controller block ? the internal overhead data generator the manner in how the transmit ds3 framer block handles data from each of these sources is described below. handling of data from the "transmit payload data input interface for ds3 applications, all data that is input to the "transmit payload data input" interface will be insert- ed into the payload bit positions within the "outbound" ds3 frames. handling of data from the "internal overhead bit" generator by default, the transmit ds3 framer block will inter- nally generate the overhead bits. however, if the ter- minal equipment inserts its own values for the over- head bits (via the "transmit overhead data input in- terface); or if the user enables and employs the "transmit ds3 hdlc controller" block, then these "internally generated" overhead bits will be overwrit- ten. handling of data from the "transmit overhead da- ta input interface for ds3 applications, the transmit ds3 framer block automatically generates and inserts the framing align- ment bits (e.g., the "f" and "m" bits) into the "out- bound" ds3 frames. further, the transmit ds3 fram- er block will automatically compute and insert the p- bits into the "outbound" ds3 frames. hence, the transmit ds3 framer block will not accept data from the "transmit oh data input interface" block for the "f", "m" and "p" bits. however, the transmit ds3 framer block will accept (and insert) data from the "transmit overhead data input" interface for the following bit-fields. ? x-bits ? febe bits ? feac bits ? dl bits ? udl bits ? cp bits if the user's local "data link" equipment activates the "transmit overhead data input interface" block and writes data into this interface for these bits, then the r/w r/w r/w r/w r/w r/w r/w r/w 0110 1xxx operating mode register (address = 0x00) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 rxds3/e3 interrupt enable not used m13 interrupt status not used txds3/e3 interrupt enable one second interrupt enable r/wrororororor/w r/w 0000000 x ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 271 transmit ds3 framer block will insert this data into the appropriate overhead bit-fields, within the "out- bound" ds3 frames. handling of data from the transmit hdlc con- troller block the exact manner in how the transmit ds3 framer handles data from the "transmit hdlc controller" block depends upon whether the "transmit hdlc controller" is transmitting "bos" (bit oriented signal- ing) or "mos" (message oriented signaling) data. if the transmit ds3 hdlc controller block is not acti- vated, then the transmit ds3 framer block will in- sert a 1 into each feac and dl bit-field, within each outbound ds3 frame. if the transmit ds3 hdlc controller block is activat- ed, and is configured to transmit either a bos or mos type message; then data will be inserted into the feac and dl bit-fields as described in section 3.2.3. 4.2.4.2 detailed functional description of the transmit ds3 framer block the transmit ds3 framer receives data from the fol- lowing three sources and combines them together to form a ds3 data stream. ? the transmit payload data input interface block. ? the transmit overhead data input interface block ? the transmit hdlc controller block. afterwards, this ds3 data stream will be routed to the "transmit ds3 liu interface" block, for further pro- cessing. figure 83 presents a simple illustration of the trans- mit ds3 framer block, along with the associated paths to the other functional blocks within the chip. in addition to taking data from multiple sources and multiplexing them, in appropriate manner, to create the "outbound" ds3 frames, the transmit ds3 framer block has the following roles. ? generating alarm conditions ? generating errored frames (for testing purposes) ? routing "outbound" ds3 frames to the "transmit ds3 liu interface" block each of these additional roles are discussed below. 4.2.4.2.1 generating alarm conditions the transmit ds3 framer block permits the user to, by writing the appropriate data into the on-chip regis- ters, to override the data that is being written into the f igure 83. a s imple i llustration of the t ransmit ds3 f ramer b lock and the associated paths to other f unctional b locks transmit ds3 framer block transmit ds3 framer block transmit hdlc controller/buffer transmit overhead data input interface transmit payload data input interface to transmit ds3 liu interface block XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 272 "transmit payload data" and "overhead data input interfaces" and transmit the following alarm condi- tions. ? generate the yellow alarms (or "ferf" indicators) ? manipulate the x-bit (set them to "1") ? generate the ais pattern ? generate the idle pattern ? generate the los pattern ? generate ferf (yellow) alarms, in response to detection of a "red alarm" condition (via the receive section of the XRT72L13). ? generate and transmit a desired value for febe (far-end-block error). the procedure and results of generating any of these alarm conditions is presented below. the user can exercise each of these options by writ- ing the appropriate data to the tx ds3 configuration register (address = 0x30). the bit format of this reg- ister is presented below. the role/function of each of these bit-fields within the register, are discussed below. 4.2.4.2.1.1 transmit yellow alarm - bit 7 this "read/write" bit field permits the user to force the transmission of a "yellow alarm" to the "remote ter- minal equipment" via software control. if the user opts to transmit a "yellow alarm" then both of the x- bits, within the "outbound" ds3 frames will be set to '0'. table 21 relates the content of this bit field to the transmit ds3 framer block's action. n ote : this bit is ignored when either the "txidle", "txais", or the "txlos" bit-fields are set. 4.2.4.2.1.2 transmit x-bit - bit 6 this bit field functions as the logical complement to bit 7 (e.g., "tx yellow alarm). this "read/write" bit field permits the user to force all of the x-bits, in the "outbound" ds3 frames, to "1" and transmit them to the "remote terminal equipment". table 22 relates the content of this bit field to the transmit ds3 framer block's action. tx ds3 configuration register (address = 0x30) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 tx yellow alarm tx x-bit tx idle pattern tx ais pattern tx los pattern ferf on los ferf on oof ferf on ais r/w r/w r/w r/w r/w r/w r/w r/w 0010 1011 t able 21: t he r elationship between the contents of b it 7 (t x y ellow a larm ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction b it 7t ransmit ds3 f ramer ' s a ction 0 normal operation: the x-bits are generated by the transmit ds3 framer block based upon "near end" receiving conditions" (as detected by the receive section of the chip) 1 transmit yellow alarm: the transmit ds3 framer block will overwrite the x-bits by setting them all to "0". the payload information is not modified and is transmitted as normal. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 273 n ote : this bit is ignored when either the transmit yellow alarm, tx ais, tx idle, or txlos bit is set. 4.2.4.2.1.3 transmit idle pattern - bit 5 this "read/write" bit field permits the user to transmit an "idle pattern" to the "remote terminal equipment" upon software control. table 23 relates the contents of this bit field to the transmit ds3 framer's action. n ote : this bit is ignored when either the "tx ais" or the "tx los" bit is set. 4.2.4.2.1.4 transmit ais pattern - bit 4 this "read/write" bit field allows the user to transmit an ais pattern to the "remote terminal equipment", upon software control. table 24 relates the contents of this bit field to the transmit ds3 framer block's ac- tion. t able 22: t he r elationship between the contents of b it 6 (t x x-b its ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction b it 6t ransmit ds3 f ramer ' s a ction 0 normal operation: the x-bits are generated by the transmit ds3 framer block based upon "receiving conditions" (as detected by the receive section of the framer chip). 1 set x-bits to "1": the transmit ds3 framer will overwrite the x-bits by setting them to "1". payload information is not modified and is transmitted as normal. t able 23: t he r elationship between the contents of b it 5 (t x i dle ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer a ction b it 5t ransmit ds3 f ramer ' s a ction 0 normal operation: the overhead bits are either internally generated, or they are inserted via the "transmit overhead data input interface" or the "transmit hdlc controller" blocks. the payload bits are received from the "transmit payload data input interface". 1 transmit idle condition pattern: when this command is invoked, the transmit ds3 framer will do the following: ? set the x-bits to "1" ? set the cp-bits (f-frame #3) to "0" ? generate valid m, f, and p bits overwrite the data in the ds3 payload with a repeating "1100..." pattern. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 274 n ote : this bit is ignored when the txlos bit is set. 4.2.4.2.1.5 transmit los pattern - bit 3 this "read/write" bit field allows the user to transmit an los (loss of signal) pattern to the "remote termi- nal", upon software control. table 25 relates the contents of this bit field to the transmit ds3 framer block's action. n ote : when this bit is set, it overrides all of the other bits in this register. 4.2.4.2.1.6 ferf (far-end receive failure) on los - bit 2 this "read/write" bit-field allows the user to config- ure the transmit ds3 framer block to automatically generate a "yellow alarm" if the near-end receive section (of the XRT72L13) detects a "los" (loss of signal) condition. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. 4.2.4.2.1.7 ferf (far-end receive failure) on oof - bit 1 this "read/write" bit-field allows the user to config- ure the transmit ds3 framer block to automatically generate a "yellow alarm" if the near-end receive section (of the XRT72L13) detects an "oof (out-of- frame) condition". writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. 4.2.4.2.1.8 ferf (far-end receive failure) on ais - bit 0 this "read/write" bit-field allows the user to config- ure the transmit ds3 framer block to automatically generate a "yellow alarm" if the near-end receive section (of the XRT72L13) detects an ais (alarm in- dication signal) pattern. writing a "1" to this bit-field enables this feature. writ- ing a "0" to this bit-field disables this feature. 4.2.4.2.1.9 transmitting febe (far-end block error) values t able 24: t he r elationship between the contents of b it 4 (t x ais p attern ) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction b it 4t ransmit ds3 f ramer ' s a ction 0 normal operation: the overhead bits are either internally generated, or they are inserted via the "transmit overhead data input interface" or the "transmit hdlc controller" blocks. the payload bits are received from the "transmit payload data input interface". 1 transmit ais pattern: when this command is invoked, the transmit ds3 framer block will do the following. ? set the x-bits to "1" ? set all the c-bits to "0" ? generate valid m, f, and p bits overwrite the data in the ds3 payload with a repeating "1010..." pattern t able 25: t he r elationship between the contents of b it 3 (t x los) within the t x ds3 c onfiguration r egister , and the resulting t ransmit ds3 f ramer b lock ' s a ction b it 3t ransmit ds3 f ramer ' s a ction 0 normal operation: the overhead bits are either internally generated, or they are inserted via the "transmit overhead data input interface" or the "transmit hdlc controller" blocks. the payload bits are received from the "transmit pay- load data input interface". 1 transmit los pattern: when this command is invoked the transmit ds3 framer will do the following. ? set all of the overhead bits to "0" (including the m, f, and p bits) overwrite the ds3 payload bits with an "all zeros" pattern. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 275 by default, the transmit ds3 framer block will set the three (3) febe bit-fields to [1, 1, 1] if all of the follow- ing conditions are true. ? the local receive ds3 framer block detects no p-bit errors. ? the local receive ds3 framer block detects no cp-bit errors conversely, the transmit ds3 framer block will set the three (3) febe bit-fields to a value other than [1, 1, 1] if any one of the following conditions are true. ? the local receive ds3 framer block detects a p- bit error in the most recently received ds3 frame. ? the local receive ds3 framer block detects a cp bit error in the most recently received ds3 frame. 4.2.4.2.2 generating errored ds3 frames the transmit ds3 framer block permits the user to insert errors into the framing and error detection over- head bits (e.g., the p, m and f-bits) of the "outbound" ds3 data stream in order to support "far-end" equip- ment testing. the user can exercise this option by writing data to any of the numerous transmit ds3 mask registers. these "mask registers" and their comprising bit-fields are defined below. the bit-fields of the tx ds3 m-bit mask register, that are relevant to error-insertion are shaded. the re- maining bit-fields pertain to the febe bit-fields, and are discussed in section 4.2.4.2.1.9. the tx ds3 m-bit mask register serves two purpos- es 1. it allows the user to transmit his/her own value for febe (3 bits) - please see section 4.2.4.2.1.9. 2. it allows the user to transmit errored p-bits. 3. it allows the user to insert errors into the m-bit (framing bits) in order to support equipment test- ing. each of these bit-fields are discussed below. bit 3 - tx err (transmit errored) p-bit this bit-field allows the user to insert errors into the p-bits, of each outbound ds3 frame, for equipment testing purposes. if this bit-field is "0", then the p-bits are transmitted as calculated from the payload of the previous ds3 frames. however, if this bit-field is "1", then the p-bits are inverted (from their calculated val- ue) prior to transmission. bits 2 - 0: m-bit mask[2:0] the transmit ds3 framer will automatically perform an xor operation with the m-bits (in the ds3 data- stream) and the contents of the corresponding bit- field, within this register. the results of this operation will be written back into the m-bit positions within the "outbound" ds3 frames. therefore, if the user does not wish to insert errors into the m-bits, he/she must make sure that the contents of these bit-fields: m-bit mask[2:0] are "0". f-bit error insertion the remaining mask registers (tx ds3 f-bit mask1 through mask4 registers) contain bit-fields which cor- respond to each of the 28 f-bits, within the ds3 frame. prior to transmission, these bit-fields are auto- matically xored with the contents of the correspond- ing bit fields within these mask registers. the result of this xor operation is written back into the corre- sponding bit-field, within the outgoing ds3 frame, and is transmitted on the line. therefore, if the user does not wish to modify any of these bits, then he/she must insure that these registers contain all "0s" (the default value). tx ds3 m-bit mask register, address = 0x35 b it 7b it 6b it 5b it 4 b it 3 b it 2 b it 1 b it 0 txfebe dat[2] txfebe dat[1] txfebe dat[0] febe reg enable txerr pbit mbit mask(2) mbit mask(1) mbit mask(0) r/w r/w r/w r/w r/w r/w r/w r/w xxxx x x x x tx ds3 f-bit mask1 register, address = 0x36 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused unused unused unused fbit mask(27) fbit mask(26) fbit mask(25) fbit mask(24) ro ro ro ro r/w r/w r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 276 4.2.5 the transmit ds3 line interface block the XRT72L13 framer ic is a digital device that takes ds3 payload and overhead bit information from some terminal equipment, processes this data and ul- timately, multiplexes this information into a series of "outbound" ds3 frames. however, for ds3 coaxial cable applications, the XRT72L13 framer ic lacks the current drive capability to be able to directly trans- mit this ds3 data stream through some transformer- coupled coax cable with enough signal strength for it to comply with the isolated pulse template require- ments and be received by the remote receiver. therefore, in order to get around this problem, the framer ic requires the use of an liu (line interface unit) ic. an liu is a device that has sufficient drive capability, along with the necessary pulse-shaping circuitry to be able to transmit a signal through the transmission medium in a manner that it can (1) com- ply with the dsx-3 isolated pulse template require- ments and (2) be reliably received by the remote ter- minal equipment. figure 84 presents a circuit draw- ing depicting the framer ic interfacing to an liu (xrt7300 ds3/e3/sts-1 transmit liu). tx ds3 f-bit mask2 register, address = 0x37 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask(23) fbit mask(22) fbit mask(21) fbit mask(20) fbit mask(19) fbit mask(18) fbit mask(17) fbit mask(16) r/w r/w r/w r/w r/w r/w r/w r/w 00000000 tx ds3 f-bit mask3 register, address = 0x38 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask(15) fbit mask(14) fbit mask(13) fbit mask(12) fbit mask(11) fbit mask(10) fbit mask(9) fbit mask(8) r/w r/w r/w r/w r/w r/w r/w r/w 00000000 tx ds3 f-bit mask4 register, address = 0x39 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 fbit mask(7) fbit mask(6) fbit mask(5) fbit mask(4) fbit mask(3) fbit mask(2) fbit mask(1) fbit mask(0) r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 277 the "transmit section" of the XRT72L13 contains a block which is known as the "transmit ds3 liu inter- face" block. the purpose of the "transmit ds3 liu interface" block is to take the "outbound" ds3 data stream, from the "transmit ds3 framer" block, and to do the following: 1. encode this data into one of the following line codes a. unipolar (e.g., single-rail) b. ami (alternate mark inversion) c. b3zs (bipolar 3 zero substitution) 2. and to transmit this data to the liu ic. figure 85 presents a simple illustration of the "trans- mit ds3 liu interface" block. f igure 84. a pproach to i nterfacing the XRT72L13 f ramer ic device to the xrt7300 ds3/e3/sts-1 t ransmitter liu 5v u1 XRT72L13 txpos 65 txneg 64 txlineclk 63 dmo 79 extlos 78 rlol 77 lloop 69 rloop 70 taos 68 txlev 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 txser 46 txinclk 43 txframe 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 xrt7300 tpdata 37 tndata 38 tclk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tring 40 mtip 44 mring 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 taos 2 txlev 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 txser txinclk nibbleintf resetb rtip rring csb rw ds as txframe rxser rxclk rxframe rxlos rxoof rxred rxais a[8:0] tring ttip intb d[7:0] intb XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 278 the "transmit ds3 liu interface" block can transmit data to the liu ic or other external circuitry via two different output modes: unipolar or bipolar. if the us- er selects unipolar (or single rail) mode, then the contents of the ds3 frame is output, in a binary (nrz manner) data stream via the txpos pin to the liu ic. the txneg pin will only be used to denote the frame boundaries. txneg will pulse "high" for one bit peri- od, at the start of each new ds3 frame, and will re- main "low" for the remainder of the frame. figure 86 presents an illustration of the txpos and txneg sig- nals during data transmission while the "transmit ds3 liu interface" block is operating in the "unipolar" mode. this mode is sometimes referred to as "single rail" mode because the data pulses only exist in one polarity: positive. when the "transmit ds3 liu interface" block is oper- ating in the "bipolar" (or "dual rail") mode, then the contents of the ds3 frame is output via both the tx- pos and txneg pins. if the user chooses the bi- polar mode, then he/she can transmit the ds3 data to the liu via one of two different line codes: alternate f igure 85. a s imple i llustration of the "t ransmit ds3 liu i nterface " block from transmit ds3 framer block txpos txneg txlineclk transmit ds3 liu interface block f igure 86. t he b ehavior of t x pos and t x neg signals during data transmission while the t ransmit ds3 liu i nterface is operating in the u nipolar m ode txpos txneg txlineclk data 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 frame boundary ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 279 mark inversion (ami) or binary - 3 zero substitution (b3zs). each one of these line codes will be dis- cussed below. bipolar mode is sometimes referred to as "dual rail" because the data pulses occur in two polarities: positive and negative. the role of the tx- pos, txneg and txlineclk output pins, for this mode are discussed below. txpos - transmit positive polarity pulse: the transmit ds3 liu interface block will assert this out- put to the liu ic when it desires for the liu to gener- ate and transmit a "positive polarity" pulse to the re- mote terminal equipment. txneg - transmit negative polarity pulse: the transmit ds3 liu interface block will assert this out- put to the liu ic when it desires for the liu to gener- ate and transmit a "negative polarity" pulse to the re- mote terminal equipment. txlineclk - transmit line clock: the liu ic uses this signal from the "transmit ds3 liu interface" block to sample the state of its txpos and txneg in- puts. the results of this sampling dictates the type of pulse (positive polarity, zero, or negative polarity) that it will generate and transmit to the remote receive ds3 framer. 4.2.5.1 selecting the various line codes the user can select either the "unipolar" mode or "bi- polar" mode by writing the appropriate value to bit 3 of the i/o control register (address = 0x01), as shown below. table 26 relates the value of this bit field to the "transmit ds3 liu interface output" mode. n otes : 1. the default condition is the bipolar mode. 2. this selection also effects the operation of the receive ds3 liu interface block 4.2.5.1.1 the bipolar mode line codes if the user chooses to operate the framer in the bipo- lar mode, then he/she can choose to transmit the ds3 data-stream via the ami (alternate mark inver- sion) or the b3zs line codes. the definition of ami and b3zs line codes follow. 4.2.5.1.1.1 the ami line code ami or alternate mark inversion, means that consec- utive "one's" pulses (or marks) will be of opposite po- larity with respect to each other. the line code in- volves the use of three different amplitude levels: +1, 0, and -1. +1 and -1 amplitude signals are used to represent one's (or mark) pulses and the "0" ampli- tude pulses (or the absence of a pulse) are used to represent zeros (or space) pulses. the general rule for ami is: if a given "mark" pulse is of positive polari- ty, then the very next "mark" pulse will be of negative polarity and vice versa. this alternating-polarity rela- tionship exists between two consecutive mark pulses, independent of the number of 'zeros' that may exist between these two pulses. figure 87 presents an il- lustration of the ami line code as would appear at the txpos and txneg pins of the framer, as well as the output signal on the line. i/o control register (address = 0x01) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010 0000 t able 26: t he r elationship between the content of b it 3 (u nipolar /b ipolar *) within the uni i/o c ontrol r egister and the t ransmit ds3 f ramer l ine i nterface o utput m ode b it 3t ransmit ds3 f ramer liu i nterface o utput m ode 0 bipolar mode: ami or b3zs line codes are transmitted and received 1 unipolar (single rail) mode of transmission and reception of ds3 data is selected. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 280 n ote : one of the main reasons that the ami line code has been chosen for driving transformer-coupled media is that this line code introduces no dc component; thereby minimizing dc distortion in the line. 4.2.5.1.1.2 the b3zs line code the transmit ds3 framer and the associated liu ic combine the data and timing information (originating from the txlineclk signal) into the line signal that is transmitted to the far-end receiver. the far-end re- ceiver has the task of recovering this data and timing information from the incoming ds3 data stream. many clock and data recovery schemes rely on the use of phase locked loop technology. phase- locked-loop (pll) technology for clock recovery re- lies on transitions in the line signal, in order to main- tain "lock" with the incoming ds3 data stream. how- ever, pll-based clock recovery scheme, are vulnera- ble to the occurrence of a long stream of consecutive zeros (e.g., the absence of transitions). this scenario can cause the pll to lose "lock" with the incoming ds3 data, thereby causing the "clock" and data re- covery process of the receiver to fail. therefore, some approach is needed to insure that such a long string of consecutive zeros can never happen. one such technique is b3zs encoding. b3zs (or bipolar 3 zero substitution) is a form of ami line coding that implements the following rule. in general the b3zs line code behaves just like ami; with the exception of the case when a long string of consecutive zeros occur on the line. any string of 3 consecutive zeros will be replaced with either a "00v" or a "b0v" where "b" refers to a bipolar pulse (e.g., a pulse with a polarity that is compliant with the ami coding rule). and "v" refers to a bipolar violation pulse (e.g., a pulse with a polarity that violates the al- ternating polarity scheme of ami.) the decision be- tween inserting an "00v" or a "b0v" is made to insure that an odd number of bipolar (b) pulses exist be- tween any two bipolar violation (v) pulses. figure 88 presents a timing diagram that illustrates examples of b3zs encoding. the user chooses between ami or b3zs line coding by writing to bit 4 of the "i/o control" register (ad- dress = 0x01), as shown below. f igure 87. i llustration of ami l ine c ode data txpos txneg line signal 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 f igure 88. i llustration of two examples of b3zs e ncoding data txpos txneg 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 0 v line signal b 0 v ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 281 table 27 relates the content of this bit-field to the bi- polar line code that ds3 data will be transmitted and received at. n otes : 1. this bit is ignored if the "unipolar" mode is selected. 2. this selection also effects the operation of the "receive ds3 liu interface" block 4.2.5.2 txlineclk clock edge selection the framer also allows the user to specify whether the ds3 output data (via txpos and/or txneg out- put pins) is to be updated on the rising or falling edg- es of the txlineclk signal. the purpose of this fea- ture is to insure that the framer will alway be able to output data to the liu ic, in such a way that the liu set-up and hold time requirements can always be met. this selection is made by writing to bit 2 of the "i/o control" register, as depicted below. table 28 relates the contents of this bit field to the clock edge of txclk that ds3 data is output on the txpos and/or txneg output pins. i/o control register (address = 0x01) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/wr/wr/wr/wr/w 101 00000 t able 27: t he r elationship between b it 4 (ami/b3zs*) within the "i/o c ontrol " r egister and the b ipolar l ine c ode that is output by the t ransmit ds3 liu i nterface b lock b it 4b ipolar l ine c ode 0 b3zs 1 ami ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 disable txloc loc disable rxloc ami/zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 10100 xx0 t able 28: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the "i/o c ontrol " r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on b it 2r esult 0 rising edge: outputs on txpos and/or txneg are updated on the rising edge of txlineclk. see figure 89 for timing relationship between txlineclk, txpos and txneg signals, for this selection. 1 falling edge: outputs on txpos and/or txneg are updated on the falling edge of txlineclk. see figure 90 for timing relationship between txlineclk, txpos and txneg signals, for this selection. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 282 n ote : the user will typically make the selection based upon the "set-up" and "hold" time requirements of the "transmit liu" ic. 4.2.6 transmit section interrupt processing the "transmit section" of the XRT72L13 can gener- ate an interrupt to the microcontroller/microprocessor for the following two reasons. ? completion of transmission of feac message ? completion of transmission of lapd message 4.2.6.1 enabling "transmit section" interrupts as mentioned in section 1.6, the interrupt structure, within the XRT72L13 contains two hierarchical levels: ? block level ? source level the block level the "enable" state of the "block" level for the trans- mit section interrupts dictates whether or not inter- rupts (if enabled at the source level), are actually en- abled. the user can enable or disable these transmit sec- tion interrupts, at the block level by writing the ap- propriate data into bit 1 (tx ds3/e3 interrupt en- f igure 89. w aveform /t iming r elationship between t x l ine c lk , t x pos and t x neg - t x pos and t x neg are configured to be updated on the rising edge of t x l ine c lk txlineclk txpos txneg t32 t30 t33 f igure 90. w aveform /t iming r elationship between t x l ine c lk , t x pos and t x neg - t x pos and t x neg are configured to be updated on the falling edge of t x l ine c lk txlineclk txpos txneg t31 t32 t33 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 283 able) within the block interrupt enable register (ad- dress = 0x04); as illustrated below. setting this bit-field to 1 enables the transmit sec- tion (at the block level) for interrupt generation. conversely, setting this bit-field to 0 disables the transmit section for interrupt generation. what does it mean for the transmit section in- terrupts to be enabled or disabled at the block level? if the transmit section is disabled (for interrupt gen- eration) at the block level; then all transmit sec- tion interrupts are disabled, independent of the in- terrupt enable/disable state of the source level inter- rupts. if the transmit section is enabled (for interrupt gen- eration) at the block level; then a given interrupt will be enabled at the source level. conversely, if the transmit section is enabled (for interrupt genera- tion) at the block level; then a given interrupt will still be disabled, if it is disabled at the source level. as mentioned earlier, the transmit section of the XRT72L13 framer ic contains the following two inter- rupts ? completion of transmission of feac message interrupt. ? completion of transmission of lapd message interrupt. the enabling/disabling and servicing of each of these interrupts is described below. 4.2.6.1.1 the completion of transmission of feac message interrupt. if the transmit section interrupts have been enabled at the block level, then the user can enable or dis- able the completion of transmission of a feac mes- sage interrupt by writing the appropriate value into bit 4 (tx feac interrupt enable) within the transmit ds3 feac configuration & status register (address = 0x31) as illustrated below. setting this bit-field to 1 enables the completion of transmission of a feac message interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. 4.2.6.1.2 servicing the completion of trans- mission of a feac message interrupt as mentioned earlier, once the user commands the transmit feac processor to begin its transmission of a feac message, it will do the following. 1. it will read in the six-bit contents of the tx ds3 feac register (address = 0x32); and encapsu- late these 6 bits into a 16-bit data structure. 2. the transmit feac processor will then begin to transmit this 16-bit data structure (to the remote terminal equipment); repeatedly for 10 consecutive times. 3. upon completion of the 10th transmission, the XRT72L13 framer ic will generate the comple- tion of transmission of a feac message inter- block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used m13 interrupt enable not used txds3/e3 interrupt enable one second interrupt enable r/w r/o r/o r/w ro ro r/w r/w 00000000 transmit ds3 feac configuration & status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used tx feac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w rur r/w r/w ro 000x0000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 284 rupt to the microcontroller/microprocessor. once the XRT72L13 framer ic generates this interrupt, it will do the following. ? assert the interrupt output pin (int) by toggling it low. ? set bit 3 (tx feac interrupt status) within the tx ds3 feac configuration & status register, as illustrated below. the purpose of this interrupt is to alert the microcon- troller/microprocessor that the transmit feac pro- cessor has completed its transmission of a given feac message and is now ready to transmit the next feac message, to the remote terminal equipment. 4.2.6.1.3 the completion of transmission of the lapd message interrupt if the transmit section interrupts have been enabled at the block level, then the user can enable or dis- able the completion of transmission of a lapd mes- sage interrupt; by writing the appropriate value into bit 1 (txlapd interrupt enable) within the tx ds3 lapd status & interrupt register (address = 0x34); as illustrated below. setting this bit-field to 1 enables the completion of transmission of a lapd message interrupt. con- versely, setting this bit-field to 0 disables the com- pletion of transmission of a lapd message inter- rupt. 4.2.6.1.4 servicing the completion of trans- mission of a lapd message interrupt as mentioned earier, once the user commands the lapd transmitter to begin its transmission of a lapd message, it will do the following. 1. it will parse through the contents of the transmit lapd message buffer (located at address loca- tions 0x86 through 0xdd); and search for a string of five (5) consective 1s. if the lapd transmit- ter finds a string of five consecutive 1s (within the content of the lapd message buffer, then it will insert a 0 immediately after this string. 2. it will compute the fcs (frame check sequence) value; and append this value to the back-end of the user-message. 3. it will read out of the content of the user (zero- stuffed) message and will encapsulate this data into a lapd message frame. 4. finally, it will begin transmitting the contents of this lapd message frame via the dl bits, within each outbound ds3 frame. 5. once the lapd transmitter has completed its transmission of this lapd message frame (to the remote terminal equipment), the XRT72L13 framer ic will generate the completion of trans- mission of a lapd message interrupt to the microcontroller/microprocessor. once the XRT72L13 framer ic generates this interrupt, it will do the following. ? assert the interrupt output pin (int) by toggling it low. transmit ds3 feac configuration & status register (address = 0x31) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used tx feac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy ro ro ro r/w rur r/w r/w ro 00011000 txds3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 285 ? set bit 0 (txlapd interrupt status) within the txds3 lapd status and interrupt register, as illustrated below. the purpose of this interrupt is to alert the microcon- troller/microprocessor that the lapd transmitter has completed its transmission of a given lapd (or pmdl) message, and is now ready to transmit the next pmdl message, to the remote terminal equip- ment. 4.3 t he r eceive s ection of the XRT72L13 (ds3 m ode o peration ) when the XRT72L13 has been configured to operate in the ds3 mode, the receive section of the XRT72L13 consists of the following functional blocks. ? receive liu interface block ? receive hdlc controller block ? receive ds3 framer block ? receive overhead data output interface block ? receive payload data output interface block figure 91 presents a simple illustration of the re- ceive section of the XRT72L13 framer ic. txds3 lapd status and interrupt register (address = 0x34) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txdl start txdl busy txlapd interrupt enable txlapd interrupt status ro ro ro ro r/w ro r/w rur 00000001 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 286 each of these functional blocks will be discussed in detail in this document. 4.3.1 the receive ds3 liu interface block the purpose of the receive ds3 liu interface block is two-fold: 1. to receive "encoded" digital data from the ds3 liu ic. 2. to decode this data, convert it into a binary data stream and to route this data to the "receive ds3 framer" block. figure 92 presents a simple illustration of the "re- ceive ds3 liu interface" block. f igure 91. a s imple i llustration of the r eceive s ection of the XRT72L13, when it has been config - ured to operate in the ds3 m ode receive payload data input interface block receive ds3/e3 framer block receive liu interface block rxser rxnib[3:0] rxclk rxpos rxneg rxlineclk receive overhead input interface block rxohclk rxohind rxoh rxohenable rxohframe rxframe rx ds3 hdlc controller/buffer rx ds3 hdlc controller/buffer from microprocessor interface block ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 287 the receive section of the XRT72L13 will via the re- ceive ds3 liu interface block receive timing and data information from the incoming ds3 data stream. the ds3 timing information will be received via the rxli- neclk input pin; and the ds3 data information will be received via the rxpos and rxneg input pins. the receive ds3 liu interface block is capable of re- ceiving ds3 data pulses in unipolar or bipolar format. if the receive ds3 framer is operating in the bipolar format, then it can be configured to decode either ami or b3zs line code data. each of these input formats and line codes will be discussed in detail, below. 4.3.1.1 unipolar decoding if the receive ds3 liu interface block is operating in the unipolar (single-rail) mode, then it will receive the single rail nrz ds3 data pulses via the rxpos in- put pin. the "receive ds3 liu interface" block will also receive its timing signal via the rxlineclk signal. n ote : the "rxlineclk" signal will function as the timing source for the entire receive section of the XRT72L13. no data pulses will be applied to the rxneg input pin. the "receive ds3 liu interface" block receives a logic "1" when a logic "1" level signal is present at the rxpos pin, during the sampling edge of the rxli- neclk signal. likewise, a logic "0" is received when a logic "0" level signal is applied to the rxpos pin. figure 93 presents an illustration of the behavior of the rxpos, rxneg and rxlineclk input pins when the "receive ds3 liu interface" block is operating in the "unipolar" mode. f igure 92. a s imple i llustration of the "r eceive ds3 liu i nterface " b lock rxpos rxneg rxlineclk to receive ds3 framer block receive ds3 liu interface block XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 288 the user can configure the receive ds3 liu inter- face block to operate in either the unipolar or the bi- polar mode by writing the appropriate data to the i/o control register, as depicted below. table 29 relates the value of this bit-field to the re- ceive ds3 liu interface input mode. n otes : 1. the default condition is the bipolar mode. 2. this selection also effects the transmit ds3 framer line interface output mode 4.3.1.2 bipolar decoding if the "receive ds3 liu interface" block is operating in the bipolar mode, then it will receive the ds3 data pulses via both the rxpos, rxneg, and the rxli- neclk input pins. figure 94 presents a circuit dia- gram illustrating how the receive ds3 liu interface block interfaces to the line interface unit while the framer is operating in bipolar mode. the receive ds3 liu interface block can be configured to decode the incoming data from either the ami or b3zs line codes. f igure 93. b ehavior of the r x pos, r x neg and r x l ine c lk signals during data reception of u nipolar d ata rxpos rxneg rxlineclk data 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 disable txloc loc disable rxloc ami/ zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010 0000 t able 29: t he r elationship between the contents of b it 2 (t x l ine c lk i nv ) within the "i/o c ontrol " r egister and the t x l ine c lk clock edge that t x pos and t x neg are updated on b it 3r eceive ds3 liu i nterface i nput m ode 0 . bipolar mode (dual rail): ami or b3zs line codes are transmitted and received. 1 unipolar mode (single rail) mode of transmission and reception of ds3 data is selected.. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 289 4.3.1.2.1 ami decoding ami or alternate mark inversion, means that consec- utive "one's" pulses (or marks) will be of opposite po- larity with respect to each other. this line code in- volves the use of three different amplitude levels: +1, 0, and -1. the +1 and -1 amplitude signals are used to represent one's (or mark) pulses and the "0" ampli- tude pulses (or the absence of a pulse) are used to represent zeros (or space) pulses. the general rule for the ami line code is: if a given "mark" pulse is of positive polarity, then the very next "mark" pulse will be of negative polarity and vice versa. this alternat- ing-polarity relationship exists between two consecu- tive mark pulses, independent of the number of zeros that exist between these two pulses. figure 95 pre- sents an illustration of the ami line code as would appear at the rxpos and rxneg input pins of the framer, as well as the corresponding output signal on the line. n ote : one of the reasons that the ami line code has been chosen for driving copper medium, isolated via trans- formers, is that this line code has no dc component; thereby eliminating dc distortion in the line. f igure 94. i llustration on how the r eceive ds3 f ramer ( within the XRT72L13 f ramer ic) being inter - face to the xrt7300 l ine i nterface u nit , while the f ramer is operating in b ipolar m ode 5v u1 XRT72L13 txpos 65 txneg 64 txlineclk 63 dmo 79 extlos 78 rlol 77 lloop 69 rloop 70 taos 68 txlev 67 encodis 66 reqb 71 rxpos 76 rxneg 75 rxlineclk 74 moto 27 resetb 28 a0 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 d0 32 d1 33 d2 34 d3 35 d4 36 d5 37 d6 38 d7 39 rdy_dtck 6 wrb_rw 7 rdb_ds 10 csb 8 ale_as 9 intb 13 txser 46 txinclk 43 txframe 61 rxser 86 rxclk 88 rxframe 90 rxlos 95 rxoof 94 rxred 93 rxais 87 nibbleintf 25 u2 xrt7300 tpdata 37 tndata 38 tclk 36 rclk1 31 rneg 32 rpos 33 ttip 41 tring 40 mtip 44 mring 43 rring 9 rtip 8 dmo 4 rlos 24 rlol 23 llb 14 rlb 15 taos 2 txlev 1 encodis 21 reqdis 12 t1 1:1 1 5 4 8 t2 1:1 1 5 4 8 r1 36 1 2 r2 36 1 2 r6 37.5 1 2 r3 270 1 2 r4 270 1 2 r5 37.5 1 2 c1 0.01uf 1 2 txser txinclk nibbleintf resetb rtip rring csb rw ds as txframe rxser rxclk rxframe rxlos rxoof rxred rxais a[8:0] tring ttip intb d[7:0] intb f igure 95. i llustration of ami l ine c ode data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 rxpos rxneg line signal XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 290 4.3.1.2.2 b3zs decoding the transmit ds3 liu interface block and the associ- ated liu embed and combine the data and clocking information into the line signal that is transmitted to the remote terminal equipment. the "remote termi- nal" equipment has the task of recovering this data and timing information from the incoming ds3 data stream. most clock and data recovery schemes rely on the use of phase-locked-loop technology. one of the problems of using phase-locked-loop (pll) technology for clock recovery is that it relies on transi- tions in the line signal, in order to maintain lock with the incoming ds3 data-stream. therefore, these clock recovery scheme, are vulnerable to the occur- rence of a long stream of consecutive zeros (e.g., no transitions in the line). this scenario can cause the pll to lose "lock" with the incoming ds3 data, there- by causing the "clock" and data recovery process of the receiver to fail. therefore, some approach is needed to insure that such a long string of consecu- tive zeros can never happen. one such technique is b3zs (or bipolar 3 zero substitution) encoding. in general the b3zs line code behaves just like ami; with the exception of the case when a long string of consecutive zeros occurs on the line. any 3 consecu- tive zeros will be replaced with either a "00v" or a "b0v" where "b" refers to a bipolar pulse (e.g., a pulse with a polarity that is compliant with the alter- nating polarity scheme of the ami coding rule). and "v" refers to a bipolar violation pulse (e.g., a pulse with a polarity that violates the alternating polarity scheme of ami.) the decision between inserting an "00v" or a "b0v" is made to insure that an odd num- ber of bipolar (b) pulses exist between any two bipo- lar violation (v) pulses. the receive ds3 framer, when operating with the b3zs line code is responsi- ble for decoding the b3zs-encoded data back into a unipolar (binary-format). for instance, if the receive ds3 framer detects a "00v" or a "b0v" pattern in the incoming pattern, the receive ds3 framer will re- place it with three consecutive zeros. figure 96 pre- sents a timing diagram that illustrates examples of b3zs decoding. 4.3.1.2.3 line code violations the "receive ds3 liu interface" block will also check the incoming ds3 data stream for line code viola- tions. for example, when the receive ds3 liu inter- face block detects a valid bipolar violation (e.g., in b3zs line code), it will substitute three zeros into the binary data stream. however, if the bipolar violation is invalid, then an lcv (line code violation) is flagged and the "pmon lcv event count" register (address = 0x50 and 0x51) will also be incremented. additionally, the "lcv-one second accumulation" registers (address = 0x6e and 0x6f) will be incre- mented. for example: if the incoming ds3 data is b3zs encoded, the receive ds3 liu interface block will also increment the "lcv one second accumula- tion" register if three (or more) consecutive zeros are received. 4.3.1.2.4 rxlineclk clock edge selection the incoming unipolar or bipolar data, applied to the rxpos and the rxneg input pins are clocked into the receive ds3 liu interface block via the rxli- neclk signal. the framer ic allows the user to spec- ify which edge (e.g, rising or falling) of the rxlineclk signal will sample and latch the signal at the rxpos and rxneg input signals into the framer ic. this feature was included in the XRT72L13 design in order to insure that the user can always meet the rxpos and rxneg to rxlineclk set-up and hold time re- quirements. the user can make this selection by writing the appropriate data to bit 1 of the "i/o con- trol" register, as depicted below. f igure 96. i llustration of two examples of b3zs d ecoding data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 rxpos rxneg 0 0 v line signal b 0 v ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 291 table 30 depicts the relationship between the value of this bit-field to the sampling clock edge of rxli- neclk. figure 97 and figure 98 present the waveform and timing relationships between rxlineclk, rxpos and rxneg for each of these configurations. ii/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 disable txloc loc disable rxloc ami/ zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 101000 00 t able 30: t he r elationship between the contents of b it 1 (r x l ine c lk i nv ) of the i/o c ontrol r egister , and the sampling edge of the r x l ine c lk signal r x clki nv (b it 1) r esult 0 rising edge: rxpos and rxneg are sampled at the rising edge of rxlineclk. see figure 97 for timing relationship between rxlineclk, rxpos, and rxneg. 1 falling edge: rxpos and rxneg are sampled at the falling edge of rxlineclk. see figure 98 for timing relationship between rxlineclk, rxpos, and rxneg. f igure 97. w aveform /t iming r elationship between r x l ine c lk , r x pos and r x neg - w hen r x pos and r x neg are to be sampled on the rising edge of r x l ine c lk rxlineclk rxpos rxneg t38 t39 t42 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 292 4.3.2 the receive ds3 framer block the receive ds3 framer block accepts decoded ds3 data from the "receive ds3 liu interface" block, and routes data to the following destinations. ? the "receive payload data output interface block" ? the receive overhead data output interface" block. ? the receive ds3 hdlc controller block figure 99 presents a simple illustration of the "re- ceive ds3 framer" block; along with the associated paths to the other functional blocks within the framer chip. f igure 98. w aveform /t iming r elationship between r x l ine c lk , r x pos and r x neg - w hen r x pos and r x neg are to be sampled on the falling edge of r x l ine c lk rxlineclk rxpos rxneg t40 t41 f igure 99. a s imple i llustration of the r eceive ds3 f ramer b lock and the a ssociated p aths to the o ther f unctional b locks receive ds3 framer block receive ds3 framer block to receive ds3 hdlc buffer receive overhead data output interface receive payload data output interface from receive ds3 liu interface block ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 293 once the b3zs (or ami) encoded data has been de- coded into a binary data-stream, the "receive ds3 framer" block will use portions of this data-stream in order to synchronize itself to the "remote terminal equipment". at any given time, the "receive ds3 framer" block will be operating in one of two modes. ? the frame acquisition mode: in this mode, the "receive ds3 framer" block is trying to acquire synchronization with the incoming ds3 frames, or ? the frame maintenance mode: in this mode, the "receive ds3 framer" block is trying to maintain frame synchronization with the incoming ds3 frames. figure 100 presents a state machine diagram that depicts the "receive ds3 framer" block's "ds3 frame acquisition/maintenance" algorithm. 4.3.2.1 frame acquisition mode operation the "receive ds3 framer" block will be performing "frame acquisition" operation while it is operating in any of the following states (per the "ds3 frame ac- quisition/maintenance" algorithm state machine dia- gram, as depicted in figure 100 .) ? the "f-bit search" state ? the "m-bit search" state ? the "p-bit check" state (optional) once the "receive ds3 framer" block enters the "in- frame" state (per figure 100 ), then it will begin "frame maintenance" operation. when the "receive ds3 framer" block is in the "frame-acquisition" mode, it will begin to look for valid ds3 frames by first searching for the f-bits in the in- coming ds3 data stream. at this "initial point" the "receive ds3 framer" block will be operating in the "f-bit search" state within the "ds3 frame acquisi- tion/maintenance" algorithm state machine diagram (see figure 100 ). recall from the discussion in sec- f igure 100. t he s tate m achine d iagram for the "r eceive ds3 f ramer " block ' s "f rame a cquisition / m aintenance " a lgorithm f-bit search m-bit search f-bit synch achieved in-frame rxoof pin is negated. 10 consecutive f-bits correctly received parity check (only if framing on parity is selected) m-bits correctly detected for 3 consecutive m-frames (framing on parity is selected) m-bits correctly detected for 3 consecutive m-frames (framing on parity is not selected) oof criteria based upon values for f-sync algo and m-sync algo valid parity parity error in 2 out of 5 frames XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 294 tion 4.1, that each ds3 f-frame consists of four (4) f- bits that occur in a repeating "1001" pattern. the "receive ds3 framer" block will attempt to locate this f-bit pattern by performing five (5) different searches in parallel. the f-bit search has been declared suc- cessful if at least 10 consecutive f-bits are detected. after the f-bit match has been declared, the "receive ds3 framer" block will then transition into the "m-bit search" state within the "ds3 frame acquisition/ maintenance" algorithm (per figure 100 ). when the "receive ds3 framer" block reaches this state, it will begin searching for valid m-bits. recall from the dis- cussion in section 3.1 that each ds3 "m-frame" con- sists of three (3) m-bits that occur in a repeating "010" pattern. the "m-bit" search is declared successful if three consecutive "m-frames" (or 21 "f-frames") are detected correctly. once this occurs an "m-frame lock" is declared, and the "receive ds3 framer" block will then transition to the "in-frame" state. at this point, the "receive ds3 framer" block will de- clare itself in the "in-frame" condition, and will begin "frame maintenance" operations. the "receive ds3 framer" block will then indicate that it has transitioned from the "oof" condition into the "in-frame" condi- tion by doing the following. ? generate a "change in oof condition" interrupt to the local p. ? negate the rxoof output pin (e.g., toggle it "low"). ? negate the "rx oof" bit-field (bit 4) within the receive ds3 configuration and status register. the user can configure the receive ds3 framer to operate such that 'valid parity' (p-bits) must also be detected before the receive ds3 framer can declare itself "in frame". the user can set this configuration by writing the appropriate data to the "rx ds3 config- uration and status" register, as depicted below. table 31 relates the contents of this bit field to the framing acquisition criteria. once the "receive ds3 framer" block is operating in the "in-frame" condition, normal data recovery and processing of the ds3 data stream begins. the max- imum average reframing time is less than 1.5 ms. 4.3.2.2 frame maintenance mode operation when the "receive ds3 framer" block is operating in the "in-frame" state (per figure 100 ), it will then be- gin to perform "frame maintenance" operations; where it will continue to verify that the f- and m-bits are present, at their proper locations. while the "re- ceive ds3 framer" block is operating in the "frame maintenance" mode, it will declare an "out-of-frame" (oof) condition if 3 or 6 f-bits (depending upon user selection) out of 16 consecutive f-bits are in error. the user makes this selection for the "oof declara- tion" criteria by writing the appropriate value to bit 1 (f-sync algo) of the "rx ds3 configuration and sta- tus" register, as depicted below. rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 rx ais rx los rx idle rx oof reserved framing on parity f-sync algo m-sync algo ro ro ro ro r/o r/w r/w r/w xxxxx xxx t able 31: t he r elationship between the contents of b it 2 (f raming on p arity ) within the "r x ds3 c onfiguration and s tatus " r egister , and the resulting "f raming a cquisition c riteria f raming on p arity (b it 2) f raming a cquisition c riteria 0 the "in-frame" is declared after f-bit synchronization (10 f-bit matches) followed by m-bit synchronization (m-bit matches for 3 ds3 m-frames) 1 the "in-frame" condition is declared after f-bit synchronization, followed by m-bit synchronization, with valid parity over the frames. also, the occurrence of parity errors in 2 or more out of 5 frames starts a frame search ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 295 table 32 relates the contents of this bit-field to the "oof declaration" criteria n ote : once the "receive ds3 framer" block has declared an "oof" condition, it will transition back to the "f-bit search" state within the "ds3 frame acquisition/mainte- nance" algorithm (per figure 100 ). in addition to selecting an "oof declaration" criteria for the f-bits, the user has the following options for configuring the "oof declaration" criteria based up- on m-bits. 1. m-bit errors do not cause a "oof" declaration, or 2. "oof" will be declared if 3 out of 4 consecutive m-bits are in error. the user will select between these two options by writing the appropriate value to bit 0 (m-sync algo) within the "receive ds3 configuration and status" register; as depicted below. table 33 relates the contents of this bit field to the "m-bit error" criteria for declaration of oof. the "framing on parity" criteria for oof declara- tion finally, the framer ic offers the "framing on parity" option, which also effects the "oof declaration" cri- teria. as was mentioned earlier, the framer ic allows the user to configure the "receive ds3 framer" block to detect 'valid-parity' before declaring itself "in- frame". this same selection also configures the "re- "rx ds3 configuration and status" register, (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 rx ais rx los rx idle rx oof reserved framing on parity f-sync algo m-sync algo ro ro ro ro r/w r/w r/w r/w xxxxxx xx t able 32: t he r elationship between the contents of b it 1 (f-s ync a lgo ) within the r x ds3 c onfiguration and s tatus r egister , and the resulting "f- bit oof d eclaration criteria " used by the "r eceive ds3 f ramer " block f-s ync a lgo (b it 1) oof d eclaration c riteria 0 "oof" is declared when 6 out of 16 consecutive f-bits are in error. 1 "oof" is declared when 3 out of 16 consecutive f-bits are in error. rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 rx ais rx los rx idle rx oof reserved framing on parity f-sync algo m-sync algo ro ro ro ro r/w r/w r/w r/w xxxxxxx x t able 33: t he r elationship between the contents of b it 0 (m-s ync a lgo ) within the "r x ds3 c onfiguration and s tatus " r egister , and the resulting "m-b it oof d eclaration c riteria " used by the "r eceive ds3 f ramer " block ms ync a lgo oof d eclaration c riteria 0 m-bit errors do not result in the declaration of "oof" 1 "oof" is declared when 3 out of 4 m-bits are in error. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 296 ceive ds3 framer" block to also declare an "oof condition" if a p-bit error is detected in 2 of the last 5 "m-frames". whenever the "receive ds3 framer" block declares "oof" after being in the "in-frame" state the follow- ing will happen. ? the receive ds3 framer will assert the "rxoof" output pin (e.g., toggles it "high"). ? bit 4 (rxoof) within the "rx ds3 configuration and status" register will be set to "1" as depicted below. "rx ds3 configuration and status" register, (ad- dress = 0x10) ? the "receive ds3 framer" block will also issue a "change in oof status" interrupt request, anytime there is a change in the "oof" status. 4.3.2.3 forcing a reframe via software com- mand the framer ic permits the user to force a reframe procedure of the "receive ds3 framer" block via software command. if the user writes a "1" into bit 0 the i/o control register, as depicted below; then the receive ds3 framer will be forced into the "frame acquisition" mode, (or more specifically, in the "f-bit search state" per figure 100 ). afterwards, the "receive ds3 framer" block will begin its search for valid f-bits. the framer ic will also respond to this command by asserting the "rxoof" output pin, and generating a "change in oof status" interrupt. 4.3.2.4 performance monitoring of the receive ds3 framer block the user can monitor the number of framing bit errors (m and f bits) that have been detected by the "re- ceive ds3 framer" block. this is accomplished by periodically reading the "pmon framing bit error count" registers (address = 0x52 and 0x53), as de- picted below. rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 rx ais rx los rx idle rx oof reserved framing on parity f-sync algo m-sync algo r/o r/o r/o r/o r/w r/w r/w r/w xxx xxxxx i/o control register (address = 0x01) b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 disable txloc loc disable rxloc ami/ zerosup* unipolar/ bipolar* txline clk invert rxline clk invert reframe r/w ro r/w r/w r/w r/w r/w r/w 1010000 0 pmon framing bit error event count register - msb (address = 0x52) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 f-bit error count - high byte ro ro ro ro ro ro ro ro 10100000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 297 when the p/c reads these registers, it will read in the number of framing bit errors that have been de- tected since the last read of these two registers. these registers are reset upon read. 4.3.2.5 ds3 receive alarms the receive ds3 framer block is capable of detect- ing any of the following alarm conditions. ? los (loss of signal) ? ais (alarm indication signal) ? the "idle pattern". ? ferf (far-end receive failure) of "yellow alarm" condition. ? febe (far-end-block error) ? change in aic state the methods by which the "receive ds3 framer" block uses to detect and declare each of these alarm conditions are described below. 4.3.2.5.1 the loss of signal (los) alarm the "receive ds3 framer" block will declare a "loss of signal" (los) state when it detects 180 consecu- tive incoming "0s" via the "rxpos" and "rxneg" in- put pins or if the "rlos" input pin (from the xrt7300 ds3 liu or the xrt7295 line receiver ic) is assert- ed (e.g., driven high). the "receive ds3 framer" block will indicate the occurrence of an los condition by: 1. asserting the rxlos output pin (e.g., toggles it "high"). 2. setting bit 6 (rxlos) within the "rx ds3 config- uration and status" register to "1", as depicted below. 3. the "receive ds3 framer" block will generate a "change in los status" interrupt request. (note: the receive ds3 framer will also declare an "oof" condition and perform all of the "notifica- tion procedures" as described in section 3.3.2.2). 4. force the "on-chip" transmit section to transmit a "ferf" (far-end receive failure) indicator back out to the remote terminal. the "receive ds3 framer" block will clear the "los" condition when at least 60 out of 180 consecutive re- ceived bits are "1". n ote : the "receive ds3 framer" block will also generate the "change in los condition" interrupt, when it clears the los condition. the framer chip allows the user to modify the "los declaration criteria" such that an los condition is de- clared only if the "rlos" input pin (from the xrt7300 ds3/e3/sts-1 liu ic) is asserted. in this case, the "internally-generated" los criteria of "180 consecu- tive 0s" will be disabled. the user can accomplish this by writing a "1" to bit 3 (int los disable) of the rx ds3 configuration and status register, as depicted below. pmon framing bit error event count register - lsb (address = 0x53) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 f-bit error count - low byte ro ro ro ro ro ro ro ro 00000000 rx ds3 configuration and status register, (address = 0x10) b it 7 b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx ais rx los rx idle rx oof int los disable framing on parity f-sync algo m-sync algo r/o r/o r/o r/o r/w r/w r/w r/w 0 101xxxx XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 298 n ote : for more information on the "rlos" input pin, please see section 2.1. 4.3.2.5.2 the alarm indication signal (ais) the "receive ds3 framer" block will identify and de- clare an "ais" condition if it detects all of the following conditions in the incoming ds3 data stream: ? valid m-bits, f-bits and p-bits ? all c-bits are zeros. ? x-bits are set to "1" ? the payload portion of the ds3 frame exhibits a repeating "1010..." pattern. the "receive ds3 framer" block contains, within its circuitry, an "up/down" counter that supports the "as- sertion" and "negation" of the ais condition. this counter begins with the value of 0x00 upon power up or reset. the counter is then incremented anytime the "receive ds3 framer" block detects an "ais type" m-frame. this counter is then decremented, or kept at "zero" value, when the "receive ds3 framer" block detects a "non-ais" type m-frame. the "re- ceive ds3 framer" block will declare an "ais condi- tion" if this counter reaches the value of 63 m-frames or greater. explained another way, the ais condition is declared if the number of "ais-type" m-frames is detected, such that it meets the following conditions: nais - nvalid > 63 where: nais = the number of m-frames containing the ais pattern. nvalid = the number of m-frames not containing the ais pattern if at anytime, the contents of this "up/down" counter exceeds 63 m-frames, then the "receive ds3 fram- er" block will: 1. assert the "rxais" output pin by toggling it "high". 2. set bit 7 (rx ais) within the "rx ds3 configura- tion and status" register, to "1" as depicted below. 3. generate a "change in ais status" interrupt request to the p/c. 4. force the "transmit section" to transmit a "ferf" indication back to the remote terminal. the "receive ds3 framer" block will clear the "ais" condition when the following expression is true. nais - nvalid < 0. in other words, once the "receive ds3 framer" block has detected a sufficient number of normal (or "non- ais") m-frames, such that this "up/down" counter reaches "zero", then the "receive ds3 framer" block will clear the "ais condition" indicators. the "re- ceive ds3 framer" block will inform the c/p of this negation of the "ais status" by generating a "change in ais status" interrupt. 4.3.2.5.3 the idle (condition) alarm the "receive ds3 framer" block will identify and de- clare an "idle condition" if it receives a sufficient num- ber of "m-frames" that meets all of the following con- ditions. ? valid m-bits, f-bits, and p-bits ? the 3 cp-bits (in f-frame #3) are zeros. ? the x-bits are set to "1" ? the payload portion of the ds3 frame exhibits a repeating "1100..." pattern. rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 rx ais rx los rx idle rx oof int los disable framing on parity f-sync algo m-sync algo ro ro ro ro r/w r/w r/w r/w xxxx 1xxx rx ds3 configuration and status register, (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rx ais rx los rx idle rx oof int los disable framing on parity f-sync algo m-sync algo 1xxxxxxx ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 299 the "receive ds3 framer" block circuitry includes an "up/down" counter that is used to track the number of "m-frames" that have been identified as exhibiting the "idle condition" by the "receive ds3 framer" block. the contents of this counter are set to zero up- on reset or power up. this counter is then increment- ed whenever the "receive ds3 framer" block detects an "idle-type" m-frame. the counter is decremented, or kept at zero if a "non-idle" m-frame is detected. if the "receive ds3 framer" block detects a sufficient number of "idle-type" m-frames, such that the counter reaches the number "63", then the "receive ds3 framer" block will declare the "idle condition". ex- plained another way, the "receive ds3 framer" block will declare an "idle condition" if the number of "idle- pattern" m-frames is detected such that it meets the following conditions. nidle - nvalid > 63, where: nidle = the number of m-frames containing the "idle pattern" nvalid = the number of m-frames not exhibit the "idle pattern" anytime the contents of this "up/down" counter reaches the number 63, then the "receive ds3 fram- er" block will: 1. set bit 5 (rx idle) within the "rx ds3 configura- tion and status" register, to "1" as depicted below. rx ds3 configuration and status regis- ter, (address = 0x10) 2. generate a "change in idle status" interrupt request to the local p/c. the "receive ds3 framer" block will clear the "idle condition" if it has detected a sufficient number of "non-idle" m-frames, such that this "up/down" counter reaches the value "0". 4.3.2.5.4 the detection of (ferf) or "yellow alarm" condition the "receive ds3 framer" block will identify and de- clare a "yellow alarm" condition or a "far-end re- ceive failure" (ferf) condition, if it starts to receive ds3 frames with both of its x-bits set to "0". when the "receive ds3 framer" block detects a "ferf" condition in the incoming ds3 frames, then it will then do the following. 1. it will assert the "rxferf" (bit-field 4) within the rx ds3 status register, as depicted below. this bit-field will remain asserted for the duration that the "yellow alarm" condition exists. 2. the "receive ds3 framer" block will also gener- ate a "change in ferf status" interrupt to the p/c. consequently, the "receive ds3 framer" block will also assert the "ferf interrupt status" bit, within the rx ds3 interrupt status register, as depicted below. rx ds3 configuration and status register, (address = 0x10) b it 7b it 6 b it 5b it 4b it 3b it 2b it 1b it 0 rx ais rx los rx idle rx oof int los disable framing on parity f-sync algo m-sync algo r/o r/o r/o r/o r/w r/w r/w r/w xx 1xxxxx rx ds3 status register (address = 0x11) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 not used rx ferf rxaic rxfebe [2] rxfebe [1] rxfebe [0] ro ro ro ro ro ro ro ro 000 1xxxx XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 300 the receive ds3 framer block will clear the "ferf" condition, when it starts to receive receive ds3 frames that have its "x" bits set to "1". n ote : the "ferf" indicator is frequently referred to as the "yellow alarm". 4.3.2.5.5 the detection of the febe events as described in section 3.2.4.2.1.9, a given terminal equipment will set the three febe (far-end block er- ror) bit-fields to the value [1, 1, 1] (e.g., all of the febe bits are set to 1) within the outbound ds3 frames; if all of the following conditions are true about the incoming ds3 line signal. ? the receive circuitry (within the terminal equip- ment) detects no p-bit errors. ? the receive circuitry (within the terminal equip- ment) detects no cp-bit errors. if the receive section of the terminal equipment de- tects any p or cp bit errors, then the transmit section of the terminal equipment will set the three febe bits (within the outbound ds3 data stream) to a val- ue other than [1, 1, 1]. how does the receive ds3 framer block (within the XRT72L13) respond when it receives a ds3 frame with all three (3) of its febe bit-fields set to 1? as mentioned above, the terminal equipment will transmit ds3 frames, with the febe bits set to [1, 1, 1], during un-erred conditions. hence, if the receive ds3 framer block (within the XRT72L13 framer ic) receives ds3 frames with the febe bits set to [1, 1, 1] it will interpret this event as an un-erred event, and will continue normal operation. however, if the receive ds3 framer block receives a ds3 frame with the febe bits set to a value other than [1, 1, 1]; then it will increment the pmon febe event count registers (which are located at address locations 0x58 and 0x59 within the framer address space). 4.3.2.5.6 detection of change in the aic state section 3.1 indicates that the aic (application iden- tification channel) bit-field is the third overhead bit, within f-frame # 1. this particular bit-field is set to 1 for the c-bit parity framing format, and is set to 0 for the m13 framing format. hence, a given terminal equipment receiving a ds3 data stream can identify the framing format of this ds3 data stream, by reading the value fo the aic bit-field. the receive ds3 framer block permits the users microcontroller/microprocessor to determine the state of the aic bit-field (within the incoming ds3 data stream) by writing the value of the aic bit- field, within the most recently received ds3 frame, in- to bit 3 (rxaic) within the rx ds3 status register (address = 0x11); as illustrated below. the receive ds3 framer block will also generate an interrupt if it detects a change of state in the aic bit- field (within the incoming ds3 data stream). if this occurs, then the receive ds3 framer block will set rx ds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4 b it 3b it 2b it 1b it 0 cp bit error interrupt status los interrupt status ais interrupt status idle inter- rupt status ferf inter- rupt status aic interrupt status oof inter- rupt status p-bit inter- rupt status ro rur rur rur rurrurrurrur 0xxx 1xxx rxds3 status register (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved rxferf rxaic rxfebe[2:0] ro ro ro ro ro ro ro ro 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 301 bit 2 (aic interrupt status) within the rx ds3 inter- rupt stauts register (address = 0x13) to 1 as illus- trated below.r 4.3.2.6 performance monitoring of the ds3 transport medium the ds3 frame consists of some overhead bits that are used to support performance monitoring of the ds3 transmission link. these bits are the p-bits and the cp-bits. 4.3.2.6.1 p-bit checking/options the "remote" transmit ds3 framer will compute the even parity of the payload portion of an outbound ds3 frame and will place the resulting parity bit value in the 2 p-bit-fields within the very next "outbound" ds3 frame. the value of these two bits fields is ex- pected to be the identical. the "receive ds3 framer" block, while receiving each of these ds3 frames (from the "remote" trans- mit ds3 framer), will compute the even-parity of the payload portion of the frame. the "receive ds3 framer" block will then compare this "locally comput- ed" parity value to that of the p-bit fields within the very next ds3 frame. if the "receive ds3 framer" block detects a parity error, then two things will hap- pen: 1. the "receive ds3 framer" block will inform the p/c of this occurrence by generating a "detec- tion of p-bit error" interrupt; 2. the "receive ds3 framer" block will alter the value of the "febe" bits, (to a pattern other than "111") that the "near-end" transmit ds3 framer will be transmitting back to the "remote" terminal. 3. the XRT72L13 framer ic will increment the "pmon parity error event count" registers (address = 0x54 and 0x55) for each detected parity error, in the incoming ds3 data stream. the bit-format of these two registers follows. when the p reads these registers, it will read in the number of parity-bit errors that have been detected by the "receive ds3 framer" block, since the last time these registers were read. these registers are "reset upon read". rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00000100 pmon parity error event count register - msb (address = 0x54) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - high byte ro ro ro ro ro ro ro ro 00000000 pmon parity error event count register - lsb (address = 0x55) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 parity error count - low byte ro ro ro ro ro ro ro ro 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 302 n ote : when the "framing with parity" option is selected, the "receive ds3 framer" block will declared an "oof" condition if p-bit errors were detected in two out of 5 con- secutive ds3 "m-frames". 3.3.2.6.2 cp-bit checking/options cp-bits are very similar to p-bits except for the follow- ing. 1. cp-bits are used to permit performance monitor- ing over an entire ds3 path (e.g., from the source terminal); through any number of mid- network terminals to the sink terminal). 2. p-bits are used to permit performance monitoring of a ds3 data stream, as it is transmitted from one terminal to an adjacent terminal. how cp-bits are processed the following section describes how the cp-bits are processed at three locations. ? the source terminal equipment ? the mid-network terminal equipment ? the sink terminal equipment figure_62 presents a simple illustration of the loca- tions of these three types of terminal equipment, within the wide-area network. n ote : the user of the terms source and sink terminal equipment are used to simplify this discussion of cp-bit processing. in reality, the source terminal equipment (in figure_62) will also function as the sink terminal equip- ment (for ds3 traffic traveling in the opposite direction). likewise, the sink terminal equipment (in figure_62) will also function as the source terminal equipment. processing at the source terminal equipment the source terminal equipment (located at one edge of the wide-area network) will typically receive its ds3 payload data from some customer premise equipment (cpe). as the source terminal equip- ment receives this data from the cpe, it will compute the even-parity value over all bits within a given out- bound ds3 frame. the terminal equipment will then insert this even parity value into both of the p-bit fields and both the cp-bits fields, within the very next outbound ds3 frame. hence, both the p-bit values and cp-bit values will originate at the source terminal equipment. processing at the mid-network terminal equip- ment the mid-network terminal equipment has the task of doing the following. ? receiving a ds3 data stream, via the receive wan interface line card. f igure 101. a s imple i llustration of the l ocations of the s ource , m id -n etwork and s ink t ermi - nal e quipment ( for cp-b it p rocessing ) source terminal equipment source terminal equipment sink terminal equipment sink terminal equipment mid-network terminal equipment mid-network terminal equipment the wide area network customer premise equipment customer premise equipment customer premise equipment customer premise equipment ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 303 ? transmitting this same ds3 data stream (out to another remote terminal equipment) via the transmit wan interface line card. figure 102 presents an illustration of the basic archi- tecture of the mid-network terminal equipment. operation of the receive wan interface card the receive wan interface card receives a ds3 data stream from some remote terminal equipment. as the receive wan interface card does this, it will also do the following: 1. compute and verify the p-bits of each inbound ds3 frame. 2. compute and verify the cp-bits of each inbound ds3 frame. 3. output both the payload and overhead bits to the system back-plane. operation of the transmit wan interface card the transmit wan interface line card receives the outbound ds3 data stream from the system back- plane. as the transmit wan interface receives this data it will also do the following. 1. extract out the cp-bit values, from the receive wan interface line card (via the system back- plane) and insert these values into the cp-bit fields, within the outbound ds3 data stream; via the transmit overhead data input interface block of the XRT72L13 framer ic. 2. compute the even-parity over all bits, within a given outbound ds3 frame, and insert this value into the p bits within the very next outbound ds3 frame. 3. transmit this resulting ds3 data stream to the remote terminal equipment. processing at the sink terminal the sink terminal equipment (located at the oppo- site edge of the wide-area-network, from the source terminal equipment) will receive and terminate this ds3 data stream. as the sink terminal equipment receives this ds3 data stream; it will also do the fol- lowing. 1. compute and verify the p-bits within each inbound ds3 frame. 2. compute and verify the cp bits within each inbound ds3 frame. 4.3.3 the receive hdlc controller block f igure 102. i llustration of the p resumed c onfiguration of the m id -n etwork t erminal e quipment the receiving ds3 line card the receiving ds3 line card the transmitting ds3 line card the transmitting ds3 line card system back-plane ds3 traffic from source terminal equipment ds3 traffic to sink terminal equipment the mid-network terminal equipment XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 304 the receive ds3 hdlc controller block can be used to receive either "bit-oriented signaling" (bos) or "message-oriented signaling" (mos) type data link messages. the receive ds3 hdlc controller block can also be configured to receive both types of mes- sage from the remote terminal equipment. both "bos" and "mos" types of hdlc message pro- cessing are discussed in detail below. 4.3.3.1 bit-oriented signaling (or feac) pro- cessing via the receive ds3 hdlc controller. the "receive ds3 hdlc controller" block consists of two major "sub-blocks" ? the "receive feac" processor ? the "lapd receiver" this section describes how to operate the "receive feac processor". if the "receive ds3 framer" block is operating in the "c-bit parity" framing format, then the feac bit-field within the ds3 frame can be used to receive feac (far end alarm and control) messages (see figure 103 ). each feac code word is actually six bits in length. however, this six bit feac code word is encapsulated with 10 framing bits to form a 16 bit message of the form: where, "[d5, d4, d3, d2, d1, d0]" is the feac code word. the rightmost bit of the 16-bit data structure (e.g., a "1") will be received first. since each ds3 frame contains only 1 feac bit-field, 16 ds3 frames are required to transmit the 16 bit feac code mes- sage. the six bits, labeled "d5 through d0" can represent 64 distinct messages, of which 43 have been defined in the standards. the receive feac processor frames and "validates" the incoming feac data from the "remote" transmit feac processor via the received feac channel. ad- ditionally, the receive feac processor will write the "received feac code words" into an 8 bit "rx-feac" register. framing is performed by looking for two "0s" spaced 6 bits apart preceded by 8 "1s". the receive ds3 hdlc controller contains two registers that sup- port feac message reception. ? rx ds3 feac register (address = 0x16) ? rx ds3 feac interrupt enable/status register (address = 0x17) the receive feac processor generates an interrupt upon "validation" and "removal" of the incoming feac code words. operation of the receive ds3 feac processor the receive feac processor will "validate" or "re- move" feac code words; that it receives from the "re- mote" transmit feac processor. the "feac code validation" and "removal" functions are described below. feac code validation when the remote terminal equipment wishes to send a feac message to the "local" receive feac pro- cessor, it (the remote terminal equipment) will trans- mit this 16 bit message, repeatedly for a total of 10 times. the receive feac processor will frame to this incoming feac code message, and will attempt to "validate" this message. once the receive feac processor has received the same feac code word in at least 8 out of the last 10 received codes, it will "val- idate" this code word by writing this 6 bit code word into the receive ds3 feac register. the receive feac processor will then inform the c/p of this "receive feac validation" event by generating a "rx feac valid" interrupt and asserting the "feac valid" and the rx feac valid interrupt status bits in the rx ds3 interrupt enable/status register, as depicted below. the bit format of the rx ds3 feac register is presented below. feac c ode w ord f raming 0 d5 d4 d3 d2 d1 d0011111111 rx ds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5 b it 4b it 3b it 2b it 1 b it 0 not used not used not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur xxx 1x01 1 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 305 the bit-format of the "rx ds3 feac" register is pre- sented below. it is important to note that the "last val- idated" feac code word will be written into the "shaded" bit-fields below. the purpose of generating an interrupt to the p, up- on "feac code word validation" is to inform the local p that the framer has a "newly received" feac message that needs to be read. the local p would read-in this feac code word from the rx ds3 feac register (address = 0x16). feac code removal after the 10th transmission of a given feac code word, the remote terminal equipment may proceed to transmit a different feac code word. when the re- ceive feac processor detects this occurrence, it must "remove" the feac codeword that is presently residing in the "rx ds3 feac" register. the re- ceive feac processor will "remove" the existing feac code word when it detects that 3 (or more) out of the last 10 received feac codes are different from the latest "validated" feac code word. the receive feac processor will inform the local p/c of this "removal" event by generating a "rx feac removal" interrupt, and asserting the "rxfeac remove inter- rupt status" bit in the rx ds3 interrupt enable/status register, as depicted below. additionally, the receive feac processor will also denote the "removal" event by setting the "feac val- id" bit-field (bit 4), within the "rx ds3 feac interrupt enable/status" register to "0", as depicted above. the description of bits 0 through 3 within this register, all support interrupt processing, and will therefore be presented in section 3.3.6. figure 103 presents a flow diagram depicting how the receive feac pro- cessor functions. rx ds3 feac register (address = 0x16) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1b it 0 not used rxfeac [5] rxfeac [4] rxfeac [3] rxfeac [2] rxfeac [1] rxfeac [0] not used ro ro ro ro ro ro ro ro 0 d5 d4 d3 d2 d1 d0 0 rx ds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5 b it 4b it 3 b it 2b it 1b it 0 not used not used not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur xxx 01 1x0 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 306 n otes : 1. the white (e.g., unshaded) boxes reflect tasks that the users system must perform in order to con- figure the receive feac processor to receive feac messages. 2. a brief description of the steps that must exist within the feac validation and feac removal interrupt service routines exists in section 3.6 4.3.3.2 the message oriented signaling (e.g., lap-d) processing via the "receive ds3 hdlc controller" block the lapd receiver (within the "receive ds3 hdlc controller" block) allows the user to receive pmdl messages from the remote terminal equipment, via the "inbound" ds3 frames. in this case, the "inbound" message bits will be carried by the 3 "dl" bit-fields of f-frame 5, within each ds3 "m-frame". the remote lapd transmitter will transmit a lapd message to the "near-end" receiver via these three bits within each ds3 frame. the lapd receiver will receive and store the information portion of the received lapd frame into the "receive lapd message" buff- er, which is located at addresses: 0xde through 0x135 within the on-chip ram. the lapd receiver has the following responsibilities. ? framing to the incoming lapd messages ? filtering out stuffed "0s" (within the information pay- load) ? storing the frame message into the "receive lapd message" buffer ? perform frame check sequence (fcs) verification ? provide status indicators for end of message (eom) flag sequence byte detected abort sequence detected message type c/r type the occurrence of fcs errors f igure 103. f low d iagram depicting how the r eceive feac p rocessor f unctions start start enable the feac removal and validation interrupts . this is accomplished by writing xxxx 1010 into the rxds3 feac interrupt/status register (address = 0x13) enable the feac removal and validation interrupts . this is accomplished by writing xxxx 1010 into the rxds3 feac interrupt/status register (address = 0x13) receive feac processor begins reading in the feac bit-fields (of incoming ds3 frames) the receive feac processor checks for the feac framing alignment pattern of 01111110. receive feac processor begins reading in the feac bit-fields (of incoming ds3 frames) the receive feac processor checks for the feac framing alignment pattern of 01111110. is the feac framing alignmentpattern present in the feac channel ? is the feac framing alignmentpattern present in the feac channel ? read in the 6-bit feac code word the 6-bit feac code word immediately follows the feac framing alignment pattern. read in the 6-bit feac code word the 6-bit feac code word immediately follows the feac framing alignment pattern. has this same feac code word been received in 8 out of the last 10 feac message receptions? has this same feac code word been received in 8 out of the last 10 feac message receptions? has a feac code word (other than the last validated code word) been received in 3 out of the last 10 feac message receptions? has a feac code word (other than the last validated code word) been received in 3 out of the last 10 feac message receptions? generate feac validation interrupt generate feac validation interrupt invoke feac validation interruptservice routine . invoke feac validation interruptservice routine . generate feac removal interrupt generate feac removal interrupt invoke feac removal interruptservice routine . invoke feac removal interruptservice routine . 1 1 1 1 1 1 no yes yes no no yes ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 307 the lapd receiver's actions are facilitated via the fol- lowing two registers. ? rx ds3 lapd control register ? rx ds3 lapd status register operation of the lapd receiver the lapd receiver, once enabled, will begin search- ing for the boundaries of the incoming lapd mes- sage. the lapd message frame boundaries are de- lineated via the "flag sequence" octets (0x7e), as depicted in figure 104 . where: flag sequence = 0x7e sapi + cr + ea = 0x3c or 0x3e tei + ea = 0x01 control = 0x03 the 16 bit fcs is calculated using crc-16, x16 + x12 + x5 + 1 the microprocessor/microcontroller (at the remote terminal), while assembling the lapd message frame, will insert an additional byte at the beginning of the information (payload) field. this first byte of the information field indicates the type and size of the message being transferred. the value of this infor- mation field and the corresponding message type/ size follow: cl path identification = 0x38 (76 bytes) idle signal identification = 0x34 (76 bytes) test signal identification = 0x32 (76 bytes) itu-t path identification = 0x3f (82 bytes) the lapd receiver must be enabled before it can begin receiving any lapd messages. the lapd re- ceiver can be enabled by writing a "1" into bit 2 (rx- lapd enable) within the "rx ds3 lapd control" register. the bit format of this register is depicted below. once the lapd receiver has been enabled, it will be- gin searching for the flag sequence octets (0x7e), in the "dl" bit-fields, within the incoming ds3 frames. when the lapd receiver finds the flag sequence byte, it will assert the "flag present" bit (bit 0) within the "rx ds3 lapd status" register, as depicted be- low. f igure 104. lapd m essage f rame f ormat flag sequence (8 bits) sapi (6-bits) c/r ea tei (7 bits) ea control (8-bits) 76 or 82 bytes of information (payload) fcs - msb fcs - lsb flag sequence (8-bits) rx ds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 not used not used not used not used not used rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 00000 1xx XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 308 the receipt of the flag sequence octet can mean one of two things. 1. the flag sequence byte marks the beginning or end of an incoming lapd message. 2. the received flag sequence octet could be just one of many flag sequence octets that are trans- mitted via the ds3 transport medium, during idle periods between the transmission of lapd mes- sages. the lapd receiver will clear the "flag present" bit as soon as it has received an octet that is something other than the "flag sequence" octet. at this point, the lapd receiver should be receiving either octet #2 of the incoming lapd message, or an abort se- quence (e.g., a string of seven or more consecutive "1s"). if this next set of data is an abort sequence, then the lapd receiver will assert the rxabort bit (bit 6) within the "rx ds3 lapd status" register. however, if this next octet is octet #2 of an incoming lapd message, then the "rx ds3 lapd status" register will begin to present some additional status information on this incoming message. each of these indicators is presented below in sequential order. bit 3 - rxcr type - c/r (command/response) type this bit-field reflects the contents of the c/r bit-field within octet #2 of the lapd frame header. when this bit is "0" it means that this message is originating from a customer installation. when this bit is "1" it means that this message is originating from a net- work terminal. bit 4,5 - rxlapd type[1, 0] - lapd message type the combination of these two bit fields indicate the message type and the message size of the incoming lapd message frame. table 34 relates the values of bits 4 and 5 to the incoming lapd message type/ size. n ote : the message size pertains to the size of the "infor- mation portion" of the lapd message frame (as presented in figure 104 ). bit 3 - flag present the lapd receiver should receive another "flag se- quence" octet, which marks the end of the message. therefore, this bit field should be asserted once again. bit 1 - endofmessage - end of lapd message frame upon receipt of the closing "flag sequence" octet, this bit-field should be asserted. the assertion of this bit-field indicates that a lapd message frame has been completely received. additionally, if this newly received lapd message is different from the previ- ous message, then the lapd receiver will inform the c/p of the "endofmessage" event by generating an interrupt. bit 2 - rxfcserr - frame check sequence error indicator the lapd receiver will take the incoming lapd message and compute its own version of the frame check sequence (fcs) word. afterwards, the lapd receiver will compare its computed value with that it has received from the remote lapd transmitter. if these two values match, then the lapd receiver will presume that the lapd message has been properly received; and the contents of the received lapd message (payload portion) will be retained at loca- tions 0xde through 0x135 in on-chip ram. the rx ds3 lapd status register (address = 0x19) b it 7b it 6b it 5b it 4b it 3 b it 2b it 1b it 0 not used rxabort rxlapd type[1, 0] rxcr type rxfcs error end of message flag present xxxxx xx1 t able 34: t he r elationship between r x lapdt ype [1:0] and the resulting lapd m essage type and size r x lapd t ype [1, 0] m essage t ype m essage s ize 00 test signal identification 76 bytes 01 idle signal identification 76 bytes 10 cl path identification 76 bytes 11 tu-t path identification 82 bytes ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 309 lapd receiver will indicate an "error-free" reception of the lapd message by keeping this bit field negat- ed (bit 2 = 0). however, if these two fcs values do not match, then the received lapd message is cor- rupted; and the user is advised not to process this er- roneous information. the lapd receiver will indicate an erred receipt of this message by setting this bit- field to "1". n ote : the receive ds3 hdlc controller block will not generate an interrupt to the p due to the detection of an fcs error. therefore, the user is advised to "validate" each and every received lapd message by checking this bit- field prior to processing the lapd message. removal of stuff bits from the payload portion of the incoming lapd message while the lapd receiver is receiving a lapd mes- sage, it has the responsibility of removing all of the "0" stuff bits from the payload portion of the incoming lapd message frame. recall that the text in section 3.2.3.2 indicated that the lapd transmitter (at the re- mote terminal) will insert a "0" immediately following a string of 5 consecutive "1s" within the payload portion of the lapd message frame. the lapd transmitter performs this bit-stuffing procedure in order to prevent the user data from mimicking the flag sequence oc- tet (0x7e) or the abort sequence. therefore, in or- der to recover the user data to its original content (pri- or to the bit-stuffing), the lapd receiver will remove the "0" that immediately follows a string of 5 consecu- tive "1s". writing the incoming lapd message into the "re- ceive lapd message" buffer the lapd receiver will obtain the lapd message frame from the incoming ds3 data-stream. in addi- tion to processing the framing overhead octets, per- forming error checking (via fcs) and removing the stuffed "0s" from the user payload data. the lapd receiver will also write the payload portion of the lapd frame into the "receive lapd message" buff- er at locations 0xde through 0x135 in on-chip ram. therefore, the local p/c must read this location when it wishes to process this newly received lapd message. figure 105 presents a flow chart depicting how the lapd receiver works. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 310 n otes : 1. the white (e.g., unshaded) boxes reflect tasks that the users system must perform in order to con- figure the lapd receiver to receive lapd mes- sages. 2. a brief description of the steps that must exist within the receive lapd interrupt service routine exists in section 3.3.6. 4.3.4 the receive overhead data output inter- face figure 106 presents a simple illustration of the "re- ceive overhead data output interface" block within the XRT72L13. f igure 105. f low c hart depicting the f unctionality of the lapd r eceiver start start enable the lapd receiver this is done by writing the value 0xfc into the rxlapd control register (address = 0x14) lapd receiver begins reading in the dl bits from each inbound ds3 frame does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? flag sequence flag sequence abort sequence abort sequence lapd receiver is reading in a lapd message frame, containing a pmdl message. lapd receiver is reading in a lapd message frame, containing a pmdl message. does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 6 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? does the lapd receiver detect 7 consecutive zeros ? end of message (eom) end of message (eom) verify the fcs value report results in the rxlapd status register.. verify the fcs value report results in the rxlapd status register.. un-stuff contents of received message un-stuff contents of received message write received pmdl message into the receive lapd message buffer (addresses 0xde - 0x135) write received pmdl message into the receive lapd message buffer (addresses 0xde - 0x135) generate received lapd interrupt generate received lapd interrupt execute receive lapd interrupt service routine execute receive lapd interrupt service routine 1 1 1 1 no yes no yes yes no yes no ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 311 the ds3 frame consists of 4760 bits. of these bits, 4704 bits are payload bits and the remaining 56 bits are overhead bits. the XRT72L13 has been de- signed to handle and process both the payload type and overhead type bits for each ds3 frame. the receive payload data output interface block, within the receive section of the XRT72L13, has been designed to handle the payload bits. likewise, the receive overhead data output interface block has been designed to handle and process the over- head bits. the receive overhead data output interface block unconditionally outputs the contents of all overhead bits within the incoming ds3 data stream. the XRT72L13 does not offer the user a means to shut off this transmission of data. however, the receive overhead output interface block does provide the user with the appropriate output signals for external data link layer equipment to sample and process these overhead bits, via the following two methods. ? method 1- using the rxohclk clock signal. ? method 2 - using the rxclk and rxohenable output signals. each of these methods are described below. 4.3.4.1 method 1 - using the rxohclk clock signal the receive overhead data output interface block consists of four (4) signals. of these four signals, the following three signals are to be used when sampling the ds3 overhead bits via method 1. ? rxoh ? rxohclk ? rxohframe each of these signals are listed and described below in table 35 . f igure 106. a s imple i llustration of the "r eceive o verhead o utput i nterface " block receive overhead output interface block receive overhead output interface block from receive ds3 framer block rxohframe rxoh rxohclk rxohenable XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 312 interfacing the receive overhead data output interface block to the terminal equipment (meth- od 1) figure 107 illustrates how one should interface the receive overhead data output interface block to the terminal equipment; when using method 1 to sample and process the overhead bits from the in- bound ds3 data stream. t able 35: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface " b lock s ignal n ame t ype d escription rxoh output receive overhead data output pin: the XRT72L13 will output the overhead bits, within the incoming ds3 frames, via this pin. the receive overhead data output interface block will output a given overhead bit, upon the falling edge of "rxohclk". hence, the external data link equipment should sample the data, at this pin, upon the rising edge of "rxohclk". the XRT72L13 will always output the "ds3 overhead" bits via this output pin. there are no external input pins or register bit settings available that will disable this output pin. rxohclk output receive overhead data output interface clock signal: the XRT72L13 will output the overhead bits (within the incoming ds3 frames), via the "rxoh" output pin, upon the falling edge of this clock signal. as a consequence, the "user's data link equipment" should use the rising edge of this clock signal to sample the data on both the "rxoh" and "rxohframe" output pins. this clock signal is always active. rxohframe output receive overhead data output interface - start of frame indicator: the XRT72L13 will drive this output pin "high" (for one period of the "rxohclk" signal); when- ever the first overhead bit within a given ds3 frame is being driven onto the "rxoh" output pin. ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 313 method 1 operation of the terminal equipment if the terminal equipment intends to sample any overhead data from the inbound ds3 data stream (via the receive overhead data output interface block) then it is expected to do the following: 1. sample the state of the rxohframe signal (e.g., the rx_start_of_frame input signal) on the rising edge of the rxohclk (e.g., the ds3_oh_clock_in) signal. 2. keep track of the number of rising clock edges that have occurred in the rxohclk (e.g., the ds3_oh_clock_in) signal, since the last time the rxohframe signal was sampled high. by doing this, the terminal equipment will be able to keep track of which overhead bit is being output via the rxoh output pin. based upon this infor- mation, the terminal equipment will be able to derive some meaning from these overhead bits. table 36 relates the number of rising clock edges (in the rxohclk signal, since the rxohframe signal was last sampled high) to the ds3 overhead bit that is being output via the rxoh output pin. f igure 107. i llustration of how to interface the t erminal e quipment to the r eceive o verhead d ata o utput i nterface block ( for m ethod 1). terminal equipment xrt725l13e3 framer ic rxohclk ds3_oh_clock_in rxoh rxohframe ds3_oh_in rx_start_of_frame XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 314 t able 36: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since "r x ohf rame " was last sampled " high ") to the ds3 o verhead b it , that is being output via the r x oh output pin n umber of r ising c lock e dges in r x ohc lk t he o verhead b it being output by the "XRT72L13" 0 (clock edge is coincident with rxohframe being detected high) x 1f1 2aic 3f0 4na 5f0 6 feac 7f1 8x 9f1 10 udl 11 f0 12 udl 13 f0 14 udl 15 f1 16 p 17 f1 18 cp 19 f0 20 cp 21 f0 22 cp 23 f1 24 p 25 f1 26 febe 27 f0 28 febe 29 f0 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 315 figure 108 presents the typical behavior of the re- ceive overhead data output interface block, when method 1 is being used to sample the incoming ds3 overhead bits. 30 febe 31 f1 32 m0 33 f1 34 dl 35 f0 36 dl 37 f0 38 dl 39 f1 40 m1 41 f1 42 udl 43 fo 44 udl 45 fo 46 udl 47 f1 48 m0 49 f1 50 udl 51 f0 52 udl 53 f0 54 udl 55 f1 t able 36: t he r elationship between the n umber of r ising c lock e dges in r x ohc lk , ( since "r x ohf rame " was last sampled " high ") to the ds3 o verhead b it , that is being output via the r x oh output pin n umber of r ising c lock e dges in r x ohc lk t he o verhead b it being output by the "XRT72L13" XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 316 method 2 - using rxoutclk and the rxohen- able signals method 1 requires that the terminal equipment be able to handle an additional clock signal; rxo- hclk. however, there may be a situation in which the terminal equipment circuitry does not have the means to accommodate and process this extra clock signal, in order to use the receive overhead data output interface. hence, method 2 is available. method 2 involves the use of the following signals. ? rxoh ? rxoutclk ? rxohenable ? rxohframe each of these signals are listed and described below in table 37 . f igure 108. i llustration of the signals that are output via the r eceive o verhead o utput i nterface ( for m ethod 1). rxohclk rxohframe rxoh x f1 aic f0 feac terminal equipment should sample the rxohframe and rxoh signals here. recommended sampling edges ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 317 interfacing the receive overhead data output interface block to the terminal equipment (meth- od 2) figure 109 illustrates how one should interface the receive overhead data output interface block to the terminal equipment, when using method 2 to sample and process the overhead bits from the in- bound ds3 data stream. t able 37: l isting and d escription of the p in a ssociated with the r eceive o verhead d ata o utput i nterface " b lock (m ethod 2) s ignal n ame t ype d escription rxoh output receive overhead data output pin: the XRT72L13 will output the overhead bits, within the incoming ds3 frames, via this pin. the receive overhead output interface will pulse the rxohenable output pin (for one rxoutclk period) at approximately the middle of the rxoh bit period. the user is advised to design the terminal equipment to latch the contents of the rxoh output pin, whenever the rxohenable output pin is sampled high on the falling edge of rxoutclk. rxohenable output receive overhead data output enable - output pin: the XRT72L13 will assert this output signal for one rxoutclk period when it is safe for the terminal equipment to sample the data on the rxoh output pin. rxohframe output receive overhead data output interface - start of frame indicator: the XRT72L13 will drive this output pin high (for one period of the rxoh signal), whenever the first overhead bit, within a given ds3 frame is being driven onto the rxoh output pin. rxoutclk output receive section output clock signal: this clock signal is derived from the rxlineclk signal (from the liu) for loop-timing applica- tions, and the txinclk signal (from a local oscillator) for local-timing applications. for ds3 applications, this clock signal will operate at 44.736mhz. the user is advised to design the terminal equipment to latch the contents of the rxoh pin, anytime the rxohenable output signal is sampled high on the falling edge of this clock sig- nal. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 318 method 2 operation of the terminal equipment if the terminal equipment intends to sample any overhead data from the inbound ds3 data stream (via the receive overhead data output interface), then it is expected to do the following. 1. sample the state of the rxohframe signal (e.g., the rx_start_of_frame input) on the fall- ing edge of the rxoutclk clock signal; when- ever the rxohenable output signal is also sam- pled high. 2. keep track of the number of times that the rxo- henable signal has been sampled high since the last time the rxohframe was also sampled high. by doing this, the terminal equipment will be able to keep track of which overhead bit is being output via the rxoh output pin. based upon this information, the terminal equipment will be able to derive some meaning from these overhead bits. 3. table 38 relates the number of rxohenable output pulses (that have occurred since both the rxohframe and the rxohenable pins were both sampled high) to the ds3 overhead bit that is being output via the rxoh output pin. f igure 109. i llustration of how to interface the t erminal e quipment to the r eceive o verhead d ata o utput i nterface block ( for m ethod 2). rxoh rxohenable rxoutclk rxohframe ds3_oh_in ds3_oh_enable_in ds3_clk_in rx_start_of_frame terminal equipment XRT72L13 ds3 framer ic ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 319 t able 38: t he r elationship between the n umber of r x ohe nable output pulses (( since "r x ohf rame " was last sampled " high ") to the ds3 o verhead b it , that is being output via the r x oh output pin n umber of r x ohe nable o utput p ulses t he o verhead b it being output by the "XRT72L13" 0 (the rxohenable and rxohframe signals are both sampled high) x 1f1 2aic 3f0 4na 5f0 6 feac 7f1 8x 9f1 10 udl 11 f0 12 udl 13 f0 14 udl 15 f1 16 p 17 f1 18 cp 19 f0 20 cp 21 f0 22 cp 23 f1 24 p 25 f1 26 febe 27 f0 28 febe 29 f0 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 320 figure 110 presents the typical behavior of the re- ceive overhead data output interface block, when method 2 is being used to sample the incoming ds3 overhead bits. 30 febe 31 f1 32 m0 33 f1 34 dl 35 f0 36 dl 37 f0 38 dl 39 f1 40 m1 41 f1 42 udl 43 fo 44 udl 45 fo 46 udl 47 f1 48 m0 49 f1 50 udl 51 f0 52 udl 53 f0 54 udl 55 f1 t able 38: t he r elationship between the n umber of r x ohe nable output pulses (( since "r x ohf rame " was last sampled " high ") to the ds3 o verhead b it , that is being output via the r x oh output pin n umber of r x ohe nable o utput p ulses t he o verhead b it being output by the "XRT72L13" ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 321 4.3.5 the receive payload data output inter- face figure 111 presents a simple illustration of the "re- ceive payload data output interface" block. f igure 110. i llustration of the signals that are output via the r eceive o verhead d ata o utput i nterface block ( for m ethod 2). rxoutclk rxohenable rxohframe rxoh udl f1 x1 f1 aic recommended sampling edges XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 322 each of the output pins of the "receive payload data output interface" block are listed in table 39 and de- scribed below. the exact role that each of these out- put pins assume, for a variety of operating scenarios are described throughout this section. f igure 111. a s imple illustration of the "r eceive p ayload d ata o utput i nterface " block receive payload data output interface receive payload data output interface rxohind rxser rxnib[3:0] rxclk rxoutclk rxframe from receive ds3 framer block ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 323 t able 39: l isting and d escription of the pin associated with the r eceive p ayload d ata o utput i nterface block s ignal n ame t ype d escription rxser output receive serial payload data output pin: if the user opts to operate the XRT72L13 in the "serial" mode, then the chip will output the pay- load data, of the incoming ds3 frames, via this pin. the XRT72L13 will output this data upon the rising edge of rxclk. the user is advised to design the terminal equipment such that it will sample this data on the falling edge of rxclk. this signal is only active if the "nibint" input pin is pulled "low". rxnib[3:0] output receive nibble-parallel payload data output pins: if the user opts to operate the XRT72L13 in the "nibble-parallel" mode, then the chip will output the payload data, of the incoming ds3 frames, via these pins. the XRT72L13 will output data via these pins, upon the falling edge of the rxclk output pin. the user is advised to design the terminal equipment such that it will sample this data upon the rising edge of rxclk. these pins are only active if the "nibint" input pin is pulled "high". rxclk output receive payload data output clock pin: the exact behavior of this signal depends upon whether the XRT72L13 is operating in the "serial" or in the "nibble-parallel-mode". serial mode operation in the "serial" mode, this signal is a 44.736mhz clock output signal. the receive payload data output interface will update the data via the rxser output pin, upon the rising edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the "rxser" pin, upon the falling edge of this clock signal. nibble-parallel mode operation in this nibble-parallel mode, the XRT72L13 will derive this clock signal, from the rxlineclk sig- nal. the XRT72L13 will pulse this clock 1176 times for each "inbound" ds3 frame. the receive payload data output interface will update the data, on the "rxnib[3:0]" output pins upon the fall- ing edge of this clock signal. the user is advised to design (or configure) the terminal equipment to sample the data on the "rxnib[3:0] output pins, upon the rising edge of this clock signal rxohind output receive overhead bit indicator output: this output pin will pulse "high" whenever the "receive payload data output interface" outputs an "overhead" bit via the "rxser" output pin. the purpose of this output pin is to alert the termi- nal equipment that the current bit, (which is now residing on the rxser output pin), is an over- head bit and should not be processed by the terminal equipment. the XRT72L13 will update this signal, upon the rising edge of the rxclk" signal. the user is advised to design (or configure) the terminal equipment to sample this signal (along with the data on the "rxser" output pin) on the falling edge of the rxclk signal. for ds3 applications, this output pin is only active if the XRT72L13 is operating in the "serial mode". this output pin will be "low" if the device is operating in the "nibble-parallel" mode. rxframe output receive "start of frame" output indicator: the exact behavior of this pin, depends upon whether the XRT72L13 has been configured to operate in the "serial" mode or the "nibble-parallel" mode. serial mode operation: the receive section of the XRT72L13 will pulse this output pin "high" (for one bit period) when the "receive payload data output interface" block is driving the very first bit (or "nibble") of a given ds3 frame, onto the rxser output pin. nibble-parallel mode operation: the "receive section" of the XRT72L13 will pulse this output pin "high" (for one nibble period), when the "receive payload data output interface" is driving the very first nibble of a given ds3 frame, onto the "rxnib[3:0] output pins. XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 324 operation of the receive payload data output in- terface block the receive payload data output interface permits the user to read out the payload data of "inbound" ds3 frames, via either of the following modes. ? serial mode ? nibble-parallel mode each of these modes are described in detail, below. 4.3.5.1 serial mode operation behavior of the XRT72L13 if the XRT72L13 has been configured to operate in the serial mode, then the XRT72L13 will behave as follows. payload data output the XRT72L13 will output the payload data, of the in- coming ds3 frames via the rxser output, upon the rising edge of rxclk. delineation of "inbound" ds3 frames the XRT72L13 will pulse the "rxframe" output pin "high" for one bit-period; coincident with it driving the first bit within a given ds3 frame, via the "rxser" out- put pin. interfacing the XRT72L13 to the "receive termi- nal equipment" figure 112 presents a simple illustration as how the user should interface the XRT72L13 to that terminal equipment which processes "receive direction" pay- load data. required operation of the terminal equipment the XRT72L13 will update the data on the rxser out- put pin, upon the rising edge of "rxclk". however, because the rising edge of rxclk to data delay is between 14ns to 16ns; the terminal equipment should sample the data on the "rxser" output pin (or the "ds3_data_in" pin at the terminal equipment) upon the rising edge of rxclk. this will still permit the terminal equipment with a rxser to rxclk set- up time of approximately 6ns; and a hold time fo 14 to 16ns. as the terminal equipment samples "rxser" with each rising edge of "rxclk" it should also be sampling the following signals. ? rxframe ? rxohind the need for sampling "rxframe" f igure 112. i llustration of the XRT72L13 ds3/e3 f ramer ic being interfaced to the "r eceive " t ermi - nal e quipment (s erial m ode o peration ) terminal equipment (receive payload section) XRT72L13 ds3 framer ds3_data_in rx_ds3_clock_in rx_start_of_frame rxclk rxframe rxohins 44.736 mhz clock signal rxser rx_ds3_oh_ind rxlineclk 44.736 mhz clock source ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 325 the XRT72L13 will pulse the "rxframe" output pin "high" coincident with it driving the very first bit of a given ds3 frame onto the "rxser" output pin. if knowledge of the "ds3 frame boundaries" is impor- tant for the operation of the terminal equipment, then this is a very important signal for it to sample. the need for sampling "rxohind" the XRT72L13 will indicate that it is currently driving an "overhead" bit onto the "rxser" output pin, by pulsing the "rxohind" output pin "high". if the termi- nal equipment samples this signal "high", then it should know that the bit, that it is currently sampling via the "rxser" pin is an "overhead" bit and should not be processed. the behavior of the signals between the "receive payload data output interface" block and the ter- minal equipment the behavior of the signals between the XRT72L13 and the terminal equipment for ds3 serial mode op- eration is illustrated in figure 113 . 4.3.5.2 nibble-parallel mode operation behavior of the XRT72L13 if the XRT72L13 has been configured to operate in the "nibble-parallel" mode, then the XRT72L13 will behave as follows. payload data output the XRT72L13 will output the payload data of the in- coming ds3 frames, via the "rxnib[3:0] output pins, upon the falling edge of "rxclk". n otes : 1. in this case, "rxclk" will function as the "nibble clock" signal between the XRT72L13 the terminal equipment. the XRT72L13 will pulse the "rxclk" output signal "high" 1176 times, for each "inbound" ds3 frame. 2. unlike "serial mode" operation, the duty cycle of rxclk, in "nibble-parallel" mode operation is approximately 25%. delineation of "inbound" ds3 frames f igure 113. a n i llustration of the behavior of the signals between the "r eceive p ayload d ata o ut - put i nterface " block ( of the XRT72L13) and the t erminal e quipment (s erial m ode o peration ) terminal equipment signals ds3_clock_in ds3_data_in rx_start_of_frame ds3_overhead_ind XRT72L13 receive payload data i/f signals rxclk rxser rxframe rxoh_ind payload[4702] payload[4703] x-bit payload[0] payload[4702] payload[4703] x-bit payload[0] note: x-bit will not be processed by the transmit payload data input interface. ds3 frame number n ds3 frame number n + 1 note: rxframe pulses high to denote ds3 frame boundary. note: rxoh_ind pulses high to denote overhead data (e.g., the x-bit). XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 326 the XRT72L13 will pulse the "rxframe" output pin "high" for one "nibble-period" coincident with it driving the very first nibble, within a given "inbound" ds3 frame, via the "rxnib[3:0] output pins. interfacing the XRT72L13 the terminal equip- ment. figure 114 presents a simple illustration as how the user should interface the XRT72L13 to that terminal equipment which processes "receive direction" pay- load data. required operation of the terminal equipment the XRT72L13 will update the data on the "rx- nib[3:0]" line, upon the falling edge of "rxclk". hence, the terminal equipment should sample the data on the "rxnib[3:0]" output pins (or the "ds3_data_in[3:0]" input pins at the terminal equip- ment) upon the rising edge of "rxclk". as the termi- nal equipment samples "rxser" with each rising edge of "rxclk" it should also be sampling the "rx- frame" signal. the need for sampling "rxframe" the XRT72L13 will pulse the "rxframe" output pin "high" coincident with it driving the very first nibble of a given ds3 frame, onto the "rxnib[3:0]" output pins. if knowledge of the "ds3 frame boundaries" is im- portant for the operation of the terminal equipment, then this is a very important signal for it to sample. n ote : for ds3/nibble-parallel mode operation, none of the overhead bits will be output via the rxnib[3:0] output pins. hence, the rxoh_ind output pin will be in-active in this mode. the behavior of the signals between the "receive payload data output interface" block and the "terminal equipment" the behavior of the signals between the XRT72L13 and the terminal equipment for "ds3 nibble-mode" operation is illustrated in figure 115 . f igure 114. i llustration of the XRT72L13 ds3/e3 f ramer ic being interfaced to the r eceive s ection of the t erminal e quipment (n ibble -m ode o peration ) terminal equipment (receive payload section) XRT72L13 ds3 framer ds3_data_in[3:0] rx_ds3_clock_in rx_start_of_frame rxclk rxframe 11.184 mhz clock signal rxnib[3:0] rxlineclk 44.736 mhz clock source ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 327 4.3.6 receive section interrupt processing the receive section of the XRT72L13 can generate an interrupt to the microcontroller/microprocessor for the following reasons. ? change of state of receive los (loss of signal) condition ? change of state of receive oof (out of frame) condition ? change of state of receive ais (alarm indicator signal) condition ? change of state of receive idle condition. ? change of state of receive ferf (far-end receive failure) condition. ? change of state of aic (application identification channel) bit. ? detection of p-bit error in a ds3 frame ? detection of cp-bit error in a ds3 frame ? the receive feac message - validation interrupt ? the receive feac message - removal interrupt ? completion of reception of a lapd message 4.3.6.1 enabling receive section interrupts as mentioned in section 1.6, the interrupt structure, within the XRT72L13 contains two hierarchical levels. ? block level ? source level the block level the enable state of the block level for the receive section interrupts dictates whether or not interrupts (if enabled at the source level), are actually enabled. the user can enable or disable these receive sec- tion interrupts, at the block level by writing the ap- propriate data into bit 7 (rx ds3/e3 interrupt enable) within the block interrupt enable register (address = 0x04); as illustrated below. f igure 115. a n i llustration of the b ehavior of the signals between the r eceive p ayload d ata o ut - put i nterface b lock ( of the XRT72L13) and the t erminal e quipment (n ibble -m ode o peration ). terminal equipment signals XRT72L13 receive payload data i/f signals ds3 frame number n ds3 frame number n + 1 note: rxframe pulses high to denote ds3 frame boundary. rxoutclk rx_start_of_frame rx_ds3_clock_in ds3_data_in[3:0] nibble [0] nibble [1] rxoutclk rxframe rxclk rxnib[3:0] nibble [0] nibble [1] recommended sampling edge of terminal equipment XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 328 setting this bit-field to 1 enables the receive sec- tion (at the block level) for interrupt generation. conversely, setting this bit-field to 0 disables the receive section for interrupt generation. 4.3.6.2 enabling/disabling and servicing receive section interrupts as mentioned earlier, the receive section of the XRT72L13 framer ic contains numerous interrupts. the enabling/disabling and servicing of each of these interrupts is described below. 4.3.6.2.1 the change of state on receive los interrupt if the change of state on receive los (loss of sig- nal) interrupt is enabled, then the XRT72L13 framer ic will generate an interrupt in response to either of the following conditions. 1. when the XRT72L13 framer ic declares an los (loss of signal) condition, and 2. when the XRT72L13 framer ic clears the los (loss of signal) condition. conditions causing the XRT72L13 framer ic to declare an los condition ? if the xrt7300 liu ic declares an los condition, and drives the rlos input pin (of the XRT72L13 framer ic) high. ? if the XRT72L13 framer ic detects a 180 consecu- tive 0s, via the rxpos and rxneg input pins. conditions causing the XRT72L13 framer ic to clear the los condition. ? when the xrt7300 liu ic ceases declaring an los condition and drives the rlos input pin (of the XRT72L13 framer ic) low. ? when the XRT72L13 framer ic detects at least 60 marks (via the rxpos and rxneg input pins) out of 180 bit-periods. enabling and disabling the change of state on receive los interrupt: the user can enable or disable the change of state on receive los interrupt, by writing the appropriate value into bit 6 (los interrupt enable) within the rxds3 interrupt enable register, as illustrated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive los interrupt whenever the XRT72L13 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int*) by driving this pin low. block interrupt enable register (address = 0x04) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxds3/e3 interrupt enable not used m13 interrupt enable unused txds3/e3 interrupt enable one second interrupt enable r/wrororororor/wr/w x0000000 rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 329 ? it will set bit 6 (los interrupt status) within the rxds3 interrupt status register to 1, as illus- trated below. whenever the users system encounters the change of los on receive interrupt, then it should do the following. 1. it should determine the current state of the los condition. recall, that this interrupt can gener- ated, whenever the XRT72L13 framer declares or clears the los defects. hence, the user can determine the current state of the los defect by reading the state of bit 6 (rxlos), within the rxds3 configuration & status registers, as illustrated below. if the los state is true 1. it should transmit a ferf (far-end receive fail- ure) to the remote terminal equipment. the XRT72L13 framer ic automatically supports this action via the ferf-upon-los feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal, indicating that a loss of signal condition has been declared. if the los state is false 1. it should cease transmitting a ferf indicator to the remote terminal equipment. the XRT72L13 framer ic automatically supports this action via the ferf-upon-los feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal equipment, indicating that the loss of sig- nal condition has been cleared. 4.3.6.2.2 the change of state on receive oof interrupt if the change of state on receive oof (out-of- frame) interrupt is enabled, then the XRT72L13 framer ic will generate an interrupt in response to ei- ther of the following conditions. 1. when the XRT72L13 framer ic declares an oof (out of frame) condition, and 2. when the XRT72L13 framer ic clears the oof (out of frame) condition. conditions causing the XRT72L13 framer ic to declare an oof condition ? if the receive ds3 framer block (within the XRT72L13 framer ic) detects at least either 3 or 6 f-bit errors, in the last 16 f-bits. conditions causing the XRT72L13 framer ic to clear the oof condition. ? whenever, the receive ds3 framer block transi- tions from the m-bit search into the in-frame state (within the frame acquisition/maintenance state machine diagram). enabling and disabling the change of state on receive oof interrupt: the user can enable or disable the change of state on receive oof interrupt, by writing the appropriate value into bit 1 (oof interrupt enable) within the rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 01000000 rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro ro ro rur 01000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 330 rxds3 interrupt enable register, as illustrated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive oof interrupt whenever the XRT72L13 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int*) by driving this pin low. ? it will set bit 1 (oof interrupt status), within the rxds3 interrupt status register to 1, as indi- cated below. whenever the terminal equipment encounters a change in oof on receive interrupt, then it should do the following. 1. it should determine the current state of the oof condition. recall, that this interrupt can gener- ated, whenever the XRT72L13 framer declares or clears the oof defects. hence, the user can determine the current state of the oof defect by reading the state of bit 4 (rxoof), within the rxds3 configuration & status registers, as illustrated below. if oof is true. 1. it should transmit a ferf (far-end receive fail- ure) to the remote terminal equipment. the XRT72L13 framer ic automatically supports this action via the ferf-upon-oof feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal, indicating that a service affecting condi- tion has been detected in the local terminal equipment. if oof is false rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rurrurrurrurrurrurrurrur 00000010 rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro ro ro rur 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 331 1. it should cease transmitting a ferf (far-end receive failure) indicator to the remote termi- nal equipment. the XRT72L13 framer ic auto- matically supports this action via the ferf- upon-oof feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote terminal equipment, indicating that the service affecting condition has been cleared. 4.3.6.2.3 the change of state of receive ais interrupt if the change of state on receive ais (alarm indica- tion signal) interrupt is enabled, then the XRT72L13 framer ic will generate an interrupt in response to ei- ther of the following conditions. 1. when the XRT72L13 framer ic detects an ais pattern, in the incoming ds3 data stream, and 2. when the XRT72L13 framer ic no longer detects the ais pattern in the incoming ds3 data stream. conditions causing the XRT72L13 framer ic to declare an ais condition ? if the receive ds3 framer block (within the XRT72L13 framer ic) detects at least 63 ds3 frames, which contains the ais pattern. conditions causing the XRT72L13 framer ic to clear the ais condition. ? whenever, the receive ds3 framer block detects 63 ds3 frames, which do not contain the ais pattern. enabling and disabling the change of state on receive ais interrupt: the user can enable or disable the change of state on receive ais interrupt, by writing the appropriate value into bit 5 (ais interrupt enable) within the rxds3 interrupt enable register, as illustrated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive ais interrupt whenever the XRT72L13 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int*) by driving it low. ? it will set bit 5 (ais interrupt status) within the rxds3 interrupt status register, to 1, as indi- cated below. whenever the terminal equipment encounters a change in ais on receive interrupt, it should do the following. rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00100000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 332 1. it should determine the current state of the ais condition. recall, that this interrupt can gener- ated, whenever the XRT72L13 framer declares or clears the ais defects. hence, the user can determine the current state of the ais defect by reading the state of bit 7 (rxais), within the rxds3 configuration & status registers, as illustrated below if the ais condition is true 1. the local terminal equipmenit should transmit a ferf (far-end receive failure) to the remote terminal equipment. the XRT72L13 framer ic automatically supports this action via the ferf- upon-ais feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core), to the remote ter- minal, indicating that a service affecting condi- tion has been detected in the local terminal equipment. if the ais condition is false 1. the local terminal equipment should cease transmitting a ferf (far-end receive failure) indicator to the remote terminal equipment. the XRT72L13 framer ic automatically supports this action via the ferf-upon-ais feature. 2. it should transmit the appropriate feac message (per bellcore gr-499-core) to the remote ter- minal, indicates that the service affecting condi- tion no longer exists. 4.3.6.2.4 the change of state of receive idle interrupt if the change of state on receive idle interrupt is enabled, then the XRT72L13 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L13 framer ic detects an idle pattern, in the incoming ds3 data stream, and 2. when the XRT72L13 framer ic no longer detects the idle pattern in the incoming ds3 data stream. conditions causing the XRT72L13 framer ic to declare an idle condition ? if the receive ds3 framer block (within the XRT72L13 framer ic) detects at least 63 ds3 frames, which contains the idle pattern. conditions causing the XRT72L13 framer ic to clear the idle condition. ? whenever, the receive ds3 framer block detects 63 ds3 frames, which do not contain the idle pattern. enabling and disabling the change of state on receive idle interrupt: the user can enable or disable the change of state on receive idle interrupt, by writing the appropriate value into bit 4 (idle interrupt enable) within the rxds3 interrupt enable register, as illustrated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro ro ro rur 00000000 rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 333 servicing the change of state on receive idle interrupt whenever the XRT72L13 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int*) by driving it low. ? it will set bit 4 (idle interrupt status), within the rx ds3 interrupt status register to 1, as indicated below. ? whenever the terminal equipment encounters the change in idle condition receive interrupt, it should do the following. 1. it should determine the current state of the idle condition. recall, that this interrupt can gener- ated, whenever the XRT72L13 framer declares or clears the idle condition. hence, the user can determine the current state of the idle condition by reading the state of bit 5 (rxidle), within the rxds3 configuration & status registers, as illustrated below 4.3.6.2.5 the change of state of receive ferf interrupt if the change of state on receive ferf interrupt is enabled, then the XRT72L13 framer ic will generate an interrupt in response to either of the following con- ditions. 1. when the XRT72L13 framer ic detects the ferf indicator, in the incoming ds3 data stream, and 2. when the XRT72L13 framer ic no longer detects the ferf indicator, in the incoming ds3 data stream. conditions causing the XRT72L13 framer ic to declare an ferf (far-end-receive failure) condi- tion ? if the receive ds3 framer block (within the XRT72L13 framer ic) detects some incoming ds3 frames with both of the x bits set to 0. conditions causing the XRT72L13 framer ic to clear the ferf condition. ? whenever, the receive ds3 framer block starts to detect some incoming ds3 frames, in which the x bits are not set to 0. enabling and disabling the change of state on receive ferf interrupt: the user can enable or disable the change of state on receive ferf interrupt, by writing the appropri- ate value into bit 3 (ferf interrupt enable) within the rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00010000 rxds3 configuration & status register (address = 0x10) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 rxais rxlos rxidle rxoof reserved framing on parity fsync algo msync algo ro ro ro ro ro ro ro rur 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 334 rxds3 interrupt enable register, as illustrated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive ferf interrupt whenever the XRT72L13 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int*) by driving it high. ? it will set bit 3 (ferf interrupt status), within the rx ds3 interrupt status register, to 1, as indi- cated below. ? whenever the terminal equipment encounters a change in ferf condition on receive interrupt, it should do the following. 1. it should determine the current state of the ferf condition. recall, that this interrupt can generated, whenever the XRT72L13 framer declares or clears the ferf condition. hence, the user can determine the current state of the ferf condition by reading the state of bit 5 (rxi- dle), within the rxds3 configuration & status registers, as illustrated below 4.3.6.2.6 the change of state of receive aic interrupt if the change of state of receive aic interrupt is enabled, then the XRT72L13 framer ic will generate an interrupt, anytime the receive ds3 framer block has detected a change in the value of the aic bit, within the incoming ds3 data stream. enabling and disabling the change of state of receive aic interrupt: the user can enable or disable the change of state on receive aic interrupt, by writing the appropriate value into bit 2 (aic interrupt enable) within the rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rurrurrurrurrurrurrurrur 00001000 rxds3 status register (address = 0x11) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved rxferf rxaic rxfebe[2:0] ro ro ro ro ro ro ro ro 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 335 rxds3 interrupt enable register, as illustrated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the change of state on receive aic interrupt whenever the XRT72L13 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int*) by driving it high. ? it will set bit 3 (aic interrupt status), within the rx ds3 interrupt status register, to 1, as indicated below. whenever the terminal equipment encounters this in- terrupt, it should do the following. ? it should continue to check the state of the aic bit, in order to see if this change is constant. ? if this change is constant, then the user should con- figure the XRT72L13 framer ic to operate in the m13 framing format, if the aic bit-field is 0. ? conversely, if the aic bit-field is 1, then the user should configure the XRT72L13 framer ic to oper- ate in the c-bit parity framing format. 4.3.6.2.7 the detection of p-bit error inter- rupt if the detection of p-bit error interrupt is enabled, then the XRT72L13 framer ic will generate an inter- rupt, anytime the receive ds3 framer block has detected a p-bit error, within the incoming ds3 data stream. enabling and disabling the detection of p-bit er- ror interrupt: the user can enable or disable the detection of p-bit error interrupt, by writing the appropriate value into bit 0 (p-bit error interrupt enable) within the rxds3 interrupt enable register, as illustrated below. rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 00000100 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 336 setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the detection of p-bit error interrupt whenever the XRT72L13 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int*) by driving it high. ? it will set bit 0 (p-bit error interrupt status) within the rx ds3 interrupt status register, to 1, as indicated below. whenever the terminal equipment encounters the detection of p-bit error interrupt, it should do the fol- lowing. ? it should read contents of pmon parity error count register (located at 0x54 and 0x55), in order to determine the number of p-bit errors recently received. 4.3.6.2.8 the detection of cp-bit error inter- rupt if the detection of cp-bit error interrupt is enabled, then the XRT72L13 framer ic will generate an inter- rupt, anytime the receive ds3 framer block has detected a cp-bit error, within the incoming ds3 da- ta stream. enabling and disabling the detection of cp-bit error interrupt: the user can enable or disable the detection of cp- bit error interrupt, by writing the appropriate value into bit 7 (cp-bit error interrupt enable) within the rxds3 interrupt enable register, as illustrated be- low. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rurrurrurrurrurrurrurrur 00000001 rxds3 interrupt enable register (address = 0x12) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp bit error interrupt enable los interrupt enable ais interrupt enable idle interrupt enable ferf interrupt enable aic interrupt enable oof interrupt enable p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 00000000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 337 servicing the detection of cp-bit error inter- rupt whenever the XRT72L13 framer ic detects this in- terrupt, it will do all of the following. ? it will assert the interrupt request output pin (int*) by driving it high. ? it will set bit 7 (cp-bit error interrupt status) within the rx ds3 interrupt status register, to 1, as indicated below. whenever the terminal equipment encounters the detection of cp-bit error interrupt, it should do the following. ? it should read contents of pmon frame cp-bit error count register (located at 0x72 and 0x73), in order to determine the number of cp-bit errors recently received. 4.3.6.2.9 the receive feac message - valida- tion interrupt if the receive feac message - validation interrupt is enabled, then the XRT72L13 framer ic will gener- ate an interrupt any time the receive feac proces- sor validates a new feac (far-end alarm & control) message. in partcular, the receive feac processor will vali- date a feac message, it that same feac message has been received in 8 of the last 10 feac message receptions. enabling/disabling the receive feac message - validation interrupt the user can enable or disable the receive feac message - validation interrupt, by writing the appro- priate data into bit 1 (rxfeac valid interrupt enable) within the rxds3 feac interrupt enable/status register, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the receive feac message - valida- tion interrupt. whenever the XRT72L13 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int*) by driving it low. ? it will set bit 0 (rxfeac valid interrupt status), within the rxds3 feac interrupt enable/status register to 1, as indicated below. rxds3 interrupt status register (address = 0x13) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 cp-bit error interrupt status los interrupt status ais interrupt status idle interrupt status ferf interrupt status aic interrupt status oof interrupt status p-bit error interrupt status rur rur rur rur rur rur rur rur 10000001 rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 000000x0 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 338 ? it will write the contents of this validated feac message into the rx ds3 feac register, as indi- cated below. whenever the terminal equipment encounters the receive feac message - validation interrupt, then it should do the following. ? it should read the contents of the rxds3 feac register, and respond accordingly. 4.3.6.2.10 the receive feac message - removal interrupt if the receive feac message - removal interrupt is enabled, then the XRT72L13 framer ic will generate an interrupt any time the receive feac processor removes a new feac (far-end alarm & control) message. in particular, the receive feac processor will re- move a feac message, it has received a different feac message (from the most recently validated message) in 3 of the last 10 feac message recep- tions. enabling/disabling the receive feac message - removal interrupt the user can enable or disable the receive feac message - removal interrupt, by writing the appro- priate data into bit 1 (rxfeac remove interrupt en- able) within the rxds3 feac interrupt enable/sta- tus register, as indicated below. setting this bit-field to 1 enables this interrupt. con- versely, setting this bit-field to 0 disables this inter- rupt. servicing the receive feac message - valida- tion interrupt. whenever the XRT72L13 framer ic generates this interrupt, it will do the following. rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 00000011 rxds3 feac register (address = 0x16) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxfeac[5:0] not used ro ro ro ro r/o r/o r/o r/o 00000000 rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 0000x0x0 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 339 ? it will assert the interrupt request output pin (int*) by driving it low. ? it will set bit 2 (rxfeac remove interrupt status), within the rxds3 feac interrupt enable/status register to 1, as indicated below. ? it will write the delete contents of the most recently validated feac message from the rx ds3 feac register, as indicated below. 4.3.6.2.11 the completion of reception of a lapd message interrupt if the completion of reception of a lapd message interrupt is enabled, then the XRT72L13 framer ic will generate an interrupt anytime the receive hdlc controller block has received a new lapd message buffer, from the remote terminal equipment, and has stored the contents of this message in the receive lapd message buffer. enabling/disable the receive lapd message interrupt the user can enable or disable the receive lapd message interrupt by writing the appropriate data in- to bit 1 (rxlapd interrupt enable) within the rxds3 lapd control register, as indicated below. writing a 1 into this bit-field enables the receive lapd message interrupt. conversely, writing a 0 into this bit-field disables the receive lapd mes- sage interrupt. servicing the receive lapd message interrupt whenever the XRT72L13 framer ic generates this interrupt, it will do the following. ? it will assert the interrupt request output pin (int*) by driving it low. rxds3 feac interrupt enable/status register (address = 0x17) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status ro ro ro ro r/w rur r/w rur 00000011 rxds3 feac register (address = 0x16) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxfeac[5:0] not used ro ro ro ro r/o r/o r/o r/o 0xxxxxx0 rxds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 000000x0 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 340 ? it will set bit 0 (rxlapd interrupt status), within the rx ds3 lapd control register to 1, as indi- cated below. ? it will write the contents of this newly received lapd message into the receive lapd message buffer (located at 0xde through 0x135). whenever the terminal equipment encounters the receive lapd interrupt, then it should read out the contents of the receive lapd message buffer, and respond accordingly. rxds3 lapd control register (address = 0x18) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used rxlapd enable rxlapd interrupt enable rxlapd interrupt status ro ro ro ro ro r/w r/w rur 00000011 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 341 5.0 channelized (m13) mode operation of the XRT72L13 this section will provide a detailed discussion the op- eration of the xrt72l713 device, when it has been configured to operate in the channelized mode. configuring the XRT72L13 to operate in the channelized mode the XRT72L13 can be configured to operate in the channelized mode by setting bit 6 (payload hdlc controller enable) to 1 and bit 4 (m13 disable) to 0, within the m22 configuration register, as illus- trated below.. 5.1 a n o verview of c hannelized o peration in simple terms, the XRT72L13, when it is configured to operate in the channelized mode will multiplex and de-multiplex signals via a two-step process. this two-step process is briefly discussed below. 5.1.1 in north american applications a very simple, general overview of both the multi- plexing and demultiplexing schemes that are typi- cally applied to ds1 and ds3 signals are briefly de- scribed below. in the transmit direction: 1. the XRT72L13 will accept 28 ds1 signals, via seven (7) m12 mux blocks. these m12 mux blocks will multiplex these 28 ds1 signals into seven ds2 signals. 2. these seven ds2 signals will then be routed to the m23 mux block. the m23 mux block will multiplex these seven ds2 signals into a ds3 data stream. this two-step multiplexing process is illustrated be- low in figure 116. in the receive direction: 1. the m23 demux block (within the XRT72L13) will receive a ds3 data stream and will de-multi- plex it into seven ds2 signals. each of these seven ds2 signals will then be routed to one of the 7 m12 demux blocks. 2. each of these m12 demux blocks will then de- multiplex these ds2 signals into 4 ds1 signals. hence, a total of 28 ds1 signals will be de-multi- plexed (from the ds3 signal) and will be output via the XRT72L13. m23 configuration register (address = 0x07) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used payload hdlc controller enable rxds1clk gapped (crc-32) m13 disable m13 loopback/ (remote loopback) tributary polarity m23 loopback code[1] m23 loopback code[0] r/o r/w r/w r/w r/w r/w r/w r/w 0 1x0xxxx f igure 116. s imple i llustration of the o verall s cheme to mux 28 ds1 signals into a ds3 signal ds1 channel 1 ds1 channel 2 ds1 channel 3 ds1 channel 4 ds2 channel 1 ds2 channel 2 ds2 channel 3 ds2 channel 4 ds2 channel 5 ds2 channel 6 ds2 channel 7 ds3 channel m12 mux m23 mux XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 342 this two-step de-multiplexing process is illustrated below in figure 117. 5.1.2 .itu-t g.747 applications a very simple, general overview of both the multi- plexing and demultiplexing schemes that are typi- cally applied to e1 and ds3 signals (in itu-t g.747 applications) are briefly described below. in the transmit direction: 1. the XRT72L13 will accept 21 e1 signals, via seven (7) m12 mux blocks. these m12 mux blocks will multiplex these 21 e1 signals into seven itu-t g.747 signals. 2. these seven itu-t g.747 signals will then be routed to the m23 mux block. the m23 mux block will multiplex these seven itu-t g.747 signals into a ds3 data stream. this two-step multiplexing process is illustrated be- low in figure 118. in the receive direction: 1. the m23 demux block (within the XRT72L13) will receive a ds3 data stream and will de-multi- plex it into seven itu-t g.747 signals. each of these seven itu-t g.747 signals will then be routed to one of the 7 m12 demux blocks. 2. each of these m12 demux blocks will de-multi- plex these itu-t g.747 signals into 3 e1 sig- nals. hence, a total of 21 e1 signals will be multi- plexed (from the ds3 signal) and will be output via the XRT72L13. f igure 117. s imple i llustration of the o verall s cheme to demux a ds3 signal into 28 ds1 signals ds1 channel 1 ds1 channel 28 ds2 channel 1 ds2 channel 2 ds2 channel 3 ds2 channel 4 ds2 channel 5 ds2 channel 6 ds2 channel 7 ds3 channel m23 demux m12 demux f igure 118. s imple i llustration of the o verall s cheme to mux 21 e1 signals into a ds3 signal e1 channel 1 e1 channel 2 e1 channel 3 g.747 channel 1 g.747 channel 2 g.747 channel 3 g.747 channel 4 g.747 channel 5 g.747 channel 6 g.747 channel 7 ds3 channel g.747 mux m23 mux ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 343 this two-step de-multiplexing process is illustrated below in figure 119. 5.1.3 real configuration options offered by the XRT72L13 the above-mentioned channelized cases were somewhat simplistic. in one case, a discussion of muxing and demuxing 28 ds1 signals into/from a ds3 signal was discussed. in the other case, a dis- cussion of muxing and demuxing 21 e1 signals in- to/from a ds3 signal was discussed. in reality, the XRT72L13 permits the user to mux/de- mux certain mixtures of ds1 and e1 signals into/ from ds3 signals. the details and procedures for handling these mixtures are presented below. 5.2 c hannelized o peration in the t ransmit d irection the XRT72L13, while operating in the channelized mode, can be configured to support either the c-bit parity or m13 framing formats. when the XRT72L13 is configured to operate in either one of these framing formats, it affects channelized opera- tion. as a consequence, the discussion of channel- ized operation of the XRT72L13 will be divided into two sections. section 5.1.1 - channelized operation of the XRT72L13, while it is configured to operate in the m13 framing format. section 5.1.2 - channelized operation of the XRT72L13, while it is configured to operate in the c- bit parity framing format. each of these two sections are presented below. 5.2.1 channelized operation, while the XRT72L13 is operating in the m13 framing for- mat. when the XRT72L13 has been configured to operate in the channelized mode, then each of the following blocks become active. ? the m23 mux/demux blocks ? seven (7) m12 mux/demux blocks since section 5.1 addresses channelized operation in the transmit direction, the m12 mux and the m23 mux blocks will be discussed below. 5.2.1.1 operation of the m12 mux blocks the XRT72L13 consists of seven m12 mux blocks. the purpose of each of these mux blocks are to ? accept 4 ds1 signals (along with 4 corresponding ds1 clock signals) and multiplex this data into a ds2 stream. ? accept 3 e1 signals (along with 3 corresponding e1 clock signals) and multiplex this data into an itu-t g.747 data stream. ? accept a ds2 signal (along with the corresponding clock signal) and route this signal directly to the m23 mux. a more detailed description of the operation of the m12 mux is presented below. 5.2.1.1.1 ds1 operation of the m12 mux as mentioned earlier, the XRT72L13 consists of sev- en (7) m12 mux blocks. each of these m12 mux blocks can be independently configured to operate in f igure 119. s imple i llustration of the o verall s cheme to demux 21 e1 signals from a ds3 signal e1 channel 1 e1 channel 21 g.747 channel 1 g.747 channel 2 g.747 channel 3 g.747 channel 4 g.747 channel 5 g.747 channel 6 g.747 channel 7 ds3 channel g.747 demux m23 demux XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 344 either the ds1, the e1 (or itu-t g.747) or the ds2 pass-thru modes. 5.2.1.1.1.1 configuring m12 mux # 1 into the ds1 mode the user can configure m12 mux # 1 to operate in the ds1 mode by setting bits 4 (m12 g.747) and 5 (m12 by-pass) to 0, within the m12 ds2 # 1 con- figuration register, as illustrated below. once the user implements this configuration setting then m12 mux # 1 will be configured to operate in the ds1 mode. when m12 mux # 1 is operating in the ds1 mode, then it will be configured to accept four (4) ds1 signals (via the txds1data_0 through txds1data_3 input pin) and generate a ds2 signal. m12 mux # 1 will use the rising edges of txds1clk_0 through txds1clk_3 in order to latch the contents of the txds1data[3:0] inputs into the m12 mux # 1 circuitry. n ote : once the user configures m12 mux #1 to operate in the ds1 mode, m12 demux # 1 will also be configured to operate in the ds1 mode. figure 120 presents a simple illustration of m12 mux # 1 (which has been configured to operate in the ds1 mode), accepting the four ds1 signals, along with their corresponding clock signals. as m12 mux # 1 accepts these four (4) ds1 signals, it will form a ds2 signal, by performing bit-wise multiplexing each of these composite ds1 signals. m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w xx0 0xxxx f igure 120. i llustration of m12 mux #1 being configured to operate in the ds1 m ode m12 mux ds1 channel 1 ds1 channel 2 ds1 channel 3 ds1 channel 4 ds2 channel ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 345 as m12 mux #1 generates this ds2 signal, it will cre- ate a data stream that has the ds2 framing struc- ture, as presented below in figure 121. configuring the remaining m12 mux blocks the remaining m12 mux blocks (e.g., m12 mux blocks numbers 2 through 7) can also be configured to operate in the ds1 mode, by setting bits 4 (m12 g.747) and bit 5 (m12 bypass) to 0, within each of their corresponding m12 ds2 configuration regis- ters (address locations: 0x1b through 0x20). 5.2.1.1.1.1.1 description of the ds2 frames and associated overhead bits in order to fully understand and appreciate the role the m12 mux block while it is operating in the ds1 mode, it is best to first describe the ds2 framing for- mat. the ds2 frame consists of 1176 bits, of which 24 of these bits are overhead bits, and the remaining 1152 bits are payload bits. the payload data is format- ted into packets of 48 bits and the overhead (oh) bits are inserted between these payload packets. as mentioned earlier, this ds2 data stream is created by the m12 mux performing bit-wise multiplexing of the four (input) ds1 signals. as a consequence, each of these 48-bit ds2 payload packets, consists of a re- peating bit-wise multiplexing data stream, as illustrat- ed below in figure 122. since each of the ds2 payload packets consists of 48 bits, then that means that each of the four ds1 sig- nals, contributed 12 bits of data to this data stream. the ds2 f and m bits each ds2 frame consists of 8 f-bits and 3 m-bits. the purpose of these f and m bits are to permit the remote terminal equipment to acquire and maintain ds2 frame synchronization, with this data stream. the f bits are used to support sub-frame frame synchronization; whereas the m bits are used to support m frame synchronization. the cxx bits f igure 121. i llustration of the ds2 f raming s tructure m0 i[48] c11 i[48] f0 i[48] c12 i[48] c13 i[48] f1 i[48] m1 i[48] c21 i[48] f0 i[48] c22 i[48] c23 i[48] f1 i[48] m1 i[48] c31 i[48] f0 i[48] c32 i[48] c33 i[48] f1 i[48] x i[48] c41 i[48] f0 i[48] c42 i[48] c43 i[48] f1 i[48] f igure 122. t he ds2 p ayload b its d1d2d3d4d1d2d3d4.... the 48 payload bits (in each block) notes: 1. d1 denotes that the source of data was from ds1 channel #1 2. d2 denotes that the source of data was from ds1 channel #2 3. d3 denotes that the source of data was from ds1 channel #3 4. d4 denotes that the source of data was from ds1 channel #4 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 346 each ds2 frame consists of 12 cxx bits. the cxx bits are used to indicate whether bit-stuffing hass oc- curred when the four ds1 signals were being multi- plexed into this ds2 signal. the c1x bits reflect the stuffing status for ds1 channel 1 (when assembling the current ds2 frame). if all three c1x bits (c11, c12, and c13) are set to 0, then stuffing was performed in ds1 channel 1. conversely, if all three c1x bits are set to 1, then stuffing was performed in ds1 channel 1. likewise, the c2x bits reflect the stuffing status for ds1 channel 2 (when assembling the current ds2 frame); and so on. why is bit-stuffing necessary when creating the ds2 data stream the m12 mux accepts four (4) ds1 signals and mul- tiplexes these signals into a ds2 signal. however, each of these four ds1 signals are asynchronous with respect to each other. some ds1 signals may be clocked into the m12 mux at a slightly slower or faster rate than that of another ds1 signal. eventually, there will be a timing slip, such that a bit (from one of the ds1 channels) which is needed to form the ds2 data stream, is not present. in this case, (in order to maintain proper timing, etc.) a stuff bit will be inserted into the ds2 frame. the m12 mux will set the cxx bits to the appropriate value in or- der to reflect this bit-stuffing action. this signal will permit the receiving terminal to know what bit- stuffing has occurred, and that it should discard this extra bit. the ds2 x-bit each ds2 frame consists of a single x bit. the ds2 x-bit functions as the yellow alarm indicator. if a given terminal detects an los (loss of signal), ais or lof (loss of framing) condition, then that terminal will set the x bits (within its outbound ds2 frames) to 1. the terminal will continue to set the x bits (within each outbound ds2 frame) to 1 for the du- ration that this defect exists. the terminal will set the x bits (within each outbound ds2 frame) to 0 during non-alarm conditions. 5.2.1.1.1.2 additional roles of the m12 mux block - ds1 mode as the m12 mux block accepts the four (4) ds1 sig- nals and multiplexes these signals into a ds2 data stream, the m12 mux block will also do the following. ? it will insert the necessary f and m bits in order to permit an m12 demux block (at the remote ter- minal equipment) in order to acquire and maintain ds2 frame synchronization with this particular ds2 data stream. ? it will insert the necessary stuff-bits and will reflect the stuff status within the cxx bits, within each outbound ds2 frame. ? if the companion m12 demux block (within the XRT72L13) detects and declares a red alarm condition (e.g., an los, ais or lof condition), then the m12 mux will set the x bit (within each out- bound ds2 frame) to 1. this form of siganling is also known as transmitting a ds2 yellow alarm or ds2 ferf (far-end-receive failure) indicator to the remote terminal equipment. the m12 mux will continue to set the x bit to 1 for the duration that this red alarm condition persists. if the corre- sponding m12 demux block does not detect any red alarm conditions, then the m12 mux block will set the x bits to 0, which denotes the normal condition. obviously this x bit, along with the remaining ds2 bits will be multiplexed into a ds3 data stream (via the m23 mux block). however, as this ds3 data stream is transmitted to the remote terminal equip- ment, and the remote terminal de-multiplexes this sig- nal back into the seven ds2 signals, the correspond- ing m12 demux (at the remote terminal equipment) will receive this ds2 yellow alarm indicator. 5.2.1.1.1.2.1 forcing the ds2 ferf condition the XRT72L13 permits the user to configure (or force) a given m12 mux block to transmit a ds2 ferf indicator to the remote terminal equipment. this can be accomplished by setting bit 2 (m12 ferf), within the appropriate m12 ds2 configura- tion register to 1. for example, if the user sets bit 2 (m12 ferf), within the m12 ds2 configuration register to 1 (as illus- trated below); then m12 mux block # 1 will begin to ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 347 transmit the ds2 ferf indicator to the remote ter- minal equipment. the user can terminate this forced transmission of the ds2 ferf indicator by setting bit 2 (m12 ferf) to 0. at this point, the m12 mux block will set the x bits, based upon receive conditions as detected by m12 demux block # 1. the user can configure any of the remaining seven (7) m12 mux blocks to transmit a ferf condition by also setting the bit 2 (m12 ferf), within the corre- sponding m12 ds2 configuration register (address locations 0x1b through 0x20), to 1. 5.2.1.1.1.2.2 forcing the ds1 ais condition the XRT72L13 permits the user to configure (or force) a given m12 mux block to transmit a ds1 ais signal. this can be accomplished by setting the cor- responding bits (within the appropriate m12 ds2 ais register to 1). an illustration of the m12 ds2 # 1 ais register, is presented below. this particular register permits the user to command the m12 mux block to overwrite ds1 channels 0 through 3 (e.g., the ds1 channels associated with m12 mux block # 1), with a ds1 ais pattern.. the XRT72L13 also contains m12 ds2 ais regis- ters, which corresponds to the remaining m12 mux blocks. each of these register also provide bit-fields with permits the user to configure these m12 mux blocks to overwrite any of these ds1 channels with a ds1 ais pattern. 5.2.1.1.1.2.3 forcing the ds2 ais pattern in addition to be able to transmit a ds1 ais pattern, the XRT72L13 permits the user to force the transmis- sion of a ds2 ais pattern. this can be accomplished by setting the appropriate bit-field, within the m23 tx ds2 ais register (ad- dress = 0x08) to 1. for example, setting bit 3 (txds2 ais channel 3), within the m23 tx ds2 ais register, to 1 config- ures m12 mux block # 4 to transmit a ds2 ais signal to the remote terminal equipment. setting this partic- ular bit-field to 0 terminates the transmission of the ds2 ais signal. m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0000x1xx m12 ds2 # 1 ais register (address = 0x21) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 3 insert ais rx ds1 channel 2 insert ais rx ds1 channel 1 insert ais rx ds1 channel 0 insert ais tx ds1 channel 3 insert ais tx ds1 channel 2 insert ais tx ds1 channel 1 insert ais tx ds1 channel 0 r/w r/w r/w r/w r/w r/w r/w r/w 00001111 m23 tx ds2 ais register (address = 0x08) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txds2 ais channel 6 txds2 ais channel 5 txds2 ais channel 4 txds2 ais channel 3 txds2 ais channel 2 txds2 ais channel 1 txds2 ais channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 348 5.2.1.1.2 e1 (itu-t g.747) operation of the m12 mux this section discusses the various configuration op- tions and features that are available whenever the XRT72L13 has been configured to operate in the itu-t g.747 mode. 5.2.1.1.2.1 configuring m12 mux # 1 into the itu-t g.747 mode the user can configure m12 mux # 1 to operate in the itu-t g.747 mode by setting bit 4 (m12 g.747) to 1 and bit 5 (m12 by-pass) to 0, within the m12 ds2 # 1 configuration register, as illustrated below. once the user implements this configuration setting then m12 mux # 1 will be configured to operate in the itu-t g.747 mode. when m12 mux # 1 is operat- ing in the itu-t g.747 mode, then it will be config- ured to accept three (3) e1 signals (via the txds1data_0 through txds1data_2 input pins) and generate a g.747 data stream. m12 mux # 1 will use the rising edges of txds1clk_0 through txds1clk_2 in order to latch the contents of the txds1data[2:0] inputs into the m12 mux # 1 cir- cuitry. figure 123 presents an illustration of m12 mux # 1 (which has been configured to operate in the g.747 mode, accepting the three e1 signals, along with their corresponding clock signals. as m12 mux # 1 accepts these three (3) e1 signals, it will form a g.747 data stream, by performing bit- wise multiplexing of the e1 signals. as m12 mux # 1 m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w xx0 1xxxx f igure 123. i llustration of the m12 mux # 1 being configured to operate in the g.747 m ode m12 mux e1 channel 1 e1 channel 2 e1 channel 3 g.747 channel ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 349 generates this g.747 signal, it will create a data stream that has the g.747 framing structure, as presented below in figure 124. configuring the remaining m12 mux blocks the remaining m12 mux blocks (e.g., m12 mux blocks numbers 2 through 7) can be configured to op- erate in the g.747 mode, by setting bit 4 (m12 g.747) to 1 and bit 5 (m12 bypass) to 0, within each of their corresponding m12 ds2 configuration registers (address locations 0x1b through 0x20). 5.2.1.1.2.1.1 description of the itu-t g.747 frames and the associated overhead bits in order to fully understand and appreciate the role of the m12 mux, it is best to first describe the itu-t g.747 framing format. the itu-t g.747 frame consists of 840 bits, of which 24 of these bits are overhead bits, and the re- maining 816 bits are payload bits. the payload data is formatted into a single packet of 159 bits (with- in subframe # 1); and into packets of 165 bits, within subframes # 2 through 5. as mentioned earlier, these itu-t g.747 data streams are created by the m12 mux performing bit-wise multiplexing of the three (in- put) e1 signals. as a consequence, each of these payload packets consists of a repeating bit-wise mul- f igure 124. i llustration of the itu-t g.747 f raming s tructure fas pattern a p * c11 c12 c13 c21 c22 c23 c31 c32 c33 payload bits (159) payload bits (165) payload bits (165) payload bits (165) payload bits (165) XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 350 tiplexing data stream, as illustrated below in figure 125. the itu-t g.747 fas (framing alignment signal) pattern the first nine bits, within a given itu-t g.747 frame functions as the framing alignment signal. this nine bit quantity is assigned the following pattern. 111010000 this pattern permits the receiving terminal to ac- quire and maintain itu-t g.747 frame synchroniza- tion with the incoming g.747 frames. the a bit the itu-t g.747 a bit functions as the yellow alarm indicator. if a given terminal detects an los (loss of signal), ais or lof (loss of framing) condi- tion, then that terminal will set the a bit (within its outbound g.747 frames) to 1. the terminal will continue to set the a bit (within each outbound g.747 frame) to 1 for the duration that the defect ex- ists. the terminal equipment will set the a bits (within its outbound g.747 frames) to 0 during non-alarm condition. the p bit the p bits within a given g.747 frame, represents the even parity calculation result over the payload bits and stuff bits of the previous g.747 frame. this bit is used to support error detection. the cxx bits the cxx bits are used to indicate whether bit-stuff- ing has occurred, when the three e1 signals are be- ing multiplexed into the g.747 signal. the c1x bit reflects the stuffing status for e1 channel 1 (when as- sembling the current g.747 frame). if c11 = c12 = c13 = 0, then no stuffing was performed in e1 channel 1. conversely, if c11, c12 and c13 are all 1, then bit-stuffing was per- formed in e1 channel 1. likewise, the c2x bits re- flect the stuffing status for e1 channel 2 (when as- sembling the current g.747 frame) and the c3x bits reflect the stuffing status for e1 channel 3 5.2.1.1.2.2 additional roles of the m12 mux block - g.747 mode as the m12 mux block accepts the three (3) e1 sig- nals and multiplexes these signals into an itu-t g.747 data stream, the m12 mux block will also do the following. ? it will insert the fas (framing alignment signal) into the outbound g.747 data stream. ? it will compute the p value of a given g.747 frame, and will insert the resulting parity value into the p bit-field of the very next g.747 frame. ? it will insert the necessary stuff bits, and will reflect the stuff status within the cxx bits, within each outbound ds2 frame. ? if the companion m12 demux block (within the XRT72L13) detects and declares a red alarm condition (e.g., an los, ais or lof condition), then the m12 mux will set the a bit (within each out- bound g.747 frame) to 1. this form of signaling is known as transmitting a g.747 ferf indicator to the remote terminal equipment. the m12 mux block will continue to set the a bit to 1 for the duration that this red alarm condition persists. if the corresponding m12 demux block does not detect any red alarm condition, then the m12 mux block will set the a bit to 0, which denotes the normal condition. f igure 125. t he itu-t g.747 p ayload b its d1 d2 d3 d1 d2 d3 d1 d2 . . . . the 159 or 168 payload bits (in each set) notes: 1. d1 denotes that the source of data was from e1 channel #1 2. d2 denotes that the source of data was from e1 channel #2 3. d3 denotes that the source of data was from e1 channel #3 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 351 5.2.1.1.2.3 forcing the g.747 ferf condi- tion the XRT72L13 permits the user to configure (or force) a given m12 mux block to transmit a g.747 ferf indicator to the remote terminal equipment. this can be accomplished by setting bit 2 (m12 ferf), within the appropriate m12 ds2 configura- tion register, to 1. for example, if the user sets bit 2 (m12 ferf), within the m12 ds2 configuration register to 1 (as illus- trated below); then m12 mux block # 1 will begin to transmit the g.747 ferf indicator to the remote ter- minal equipment. the user can terminate this forced transmission of the g.747 ferf indicator by setting bit 2 (m12 ferf) to 0. at this point, the m12 mux block will set the a bits, based upon receive conditions as detected by m12 demux block # 1. 5.2.1.1.2.4 forcing the e1 ais condition the XRT72L13 permits the user to configure (or force) a given m12 mux block to transmit an e1 ais signal. this can be accomplished by setting the cor- responding bits (within the appropriate m12 ds2 ais register to 1). an illustration of the m12 ds2 # 1 ais register, is presented below. this particular register permits the user to to command the m12 mux block to overwrite e1 channels 0 through 2 (e.g., the e1 channels as- sociated with m12 mux block # 1), with an e1 ais signal. the XRT72L13 also contains m12 ds2 ais regis- ters, which corresponds to the remaining m12 mux blocks. each of these registers also provide bit-fields which permits the user to configure these m12 mux blocks to overwrite any of these e1 channels with an e1 ais pattern. 5.2.1.1.2.5 forcing the g.747 ais pattern in addition to being able to transmit an e1 ais pat- tern, the XRT72L13 also permits the user to force the transmission of a g.747 ais pattern. this can be accomplished by setting the appropriate bit-field, within the m23 tx ds2 ais register (ad- dress = 0x08) to 1. 5.2.1.1.3 ds2 pass-thru mode operation of the m12 mux m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w xx0 1x1xx m12 ds2 # 1 ais register (address = 0x21) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 insert ais rx ds1 channel 3 insert ais rx ds1 channel 2 insert ais rx ds1 channel 1 insert ais rx ds1 channel 0 insert ais tx ds1 channel 3 insert ais tx ds1 channel 2 insert ais tx ds1 channel 1 insert ais tx ds1 channel 0 r/w r/w r/w r/w r/w r/w r/w r/w 00001111 m23 tx ds2 ais register (address = 0x08) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 not used txds2 ais channel 6 txds2 ais channel 5 txds2 ais channel 4 txds2 ais channel 3 txds2 ais channel 2 txds2 ais channel 1 txds2 ais channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 00000000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 352 this section discusses the various configuration op- tions and features that are available whenever the XRT72L13 has been configured to operate in the ds2 pass-thru mode. configuring m12 mux # 1 into the ds2 pass th- ru mode the user can configure m12 mux # 1 to operate in the ds2 pass-thru mode by setting bit 4 (m12 g.747) to 0 and bit 5 (m12 bypass) to 1 within the m12 ds2 # 1 configuration register, as illustrated below. once the user implements this configuration setting, then m12 mux # 1 will be configured to operate in the ds2 pass-thru mode. when m12 mux # 1 is oper- ating in the ds2 pass-thru mode, then it will be configured to accept a ds2 signal, via the txds1data_3 input pin. in this case, the m12 mux will perform no processing on this ds2 signal, and will simply route it to the m23 mux block. 5.2.1.2 operation of the m23 mux block as mentioned earlier, the XRT72L13 consists of sev- en m12 mux blocks and a single m23 mux block. the purpose of the m23 mux block is to accept sev- en signals (which can either be ds2 signals or itu-t g.747 signals, from each of the seven m12 mux blocks); and to multiplex these signals into a ds3 da- ta stream. 5.2.2 channelized operation, while the XRT72L13 is operating in the c-bit parity fram- ing format. 5.3 c hannelized o peration in the r eceive d irection 5.3.1 channelized operation, while the XRT72L13 is operating in the m13 framing for- mat. 5.3.1.1 operation of the m23 demux block the purpose of the m23 demux block is to accept a ds3 data stream, and to de-multiplex this data into seven signals. these signals can either be ds2 sig- nals or itu-t g.747 signals. the output of the m23 demux block will then be routed to each of the vari- ous m12 demux blocks. 5.3.1.2 operation of the m12 demux blocks the XRT72L13 consists of seven m12 demux blocks. the purpose of each of these blocks are to: ? accept a ds2 signal (from the m23 demux) and to de-multiplex these signals into four ds1 signals. ? accepts a g.747 signal (from the m23 demux) and to de-multiplex these signals into three e1 sig- nals. ? accept a ds2 signal from the m23 demux, and (if configured) route this signal directly to the output pins. a more detailed description of the operation of the m12 demux is presented below. 5.3.1.2.1 ds1 operation of the m12 demux as mentioned earlier, the XRT72L13 consists of sev- en (7) m12 mux blocks. each of these m12 mux blocks can be independently configured to operate in either ds1, the e1 (or itu-t g.747) or the ds2 pass-thru mode. 5.3.1.2.1.1 configuring the m12 demux # 1 into the ds1 mode the user can configure m12 demux # 1 to operate in the ds1 mode by setting bits 4 (m12 g.747) and 5 (m12 by-pass) to 0, within the m12 ds2 # 1 con- figuration register, as illustrated below. m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w xx1 0xxxx m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w xx0 0xxxx ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 353 once the user implements this configuration setting then m12 demux # 1 will be configured to operate in the ds1 mode. when m12 demux # 1 is operating in the ds1 mode, then it will then be configured to accept a ds2 signal, and de-multiplex this signal into 4 ds1 signals. m12 demux # 1 will then output this signal (via the rxds1data_0 through rxds1data_3 output pins). m12 demux # 1 will output this demultiplexed data upon the rising edges of rxds1clk_0 through rxds1clk_3. configuring the remaining m12 demux blocks the remaining m12 demux blocks (e.g., m12 de- mux block numbers 2 thorugh 7) can also be config- ured to operate in the ds1 mode, by setting bits 4 (m12 g.747) and bit 5 (m12 bypass) to 0, within each of their corresponding m12 ds2 configuration registers (address locations: 0x1b through 0x20). 5.3.1.2.1.2 additional roles of the m12 demux blocks - ds1 mode as the m12 demux block accepts the ds2 data stream and de-multiplexes it into 4 ds1 signals, the m12 demux block will also do the following. ? it will acquire and maintain ds2 synchronization (via the f and m bits). if the m12 demux were to fail to maintain ds2 frame synchronization, then it will declare a ds2 oof condition. ? it will also detect and declare a ds2 ais and ds2 ferf condition. ? it will detect and flag the occurrences of f and m bit errors. 5.3.1.2.1.2.1 declaring and clearing the ds2 oof condition it a given m12 demux declares a ds2 oof condi- tion, then it will do so by setting bit 4 (ds2 oof sta- tus), within the corresponding ds2 framer status register to 1. an illustration of bit 4 being set to 1, within the ds2 # 1 framer status register, is pre- sented below. n ote : the m12 demux will also generate a change in ds2 oof condition interrupt, if it detects or clears the ds2 oof condition. when the m12 demux ceases to declares the ds2 oof condition, then it will set this bit-field back to 0, in order to reflect normal operation. n ote : the locations of the remaining ds2 framer status register (for the remaining m12 demux blocks) are at address locations 0xa4 through 0xa9. 5.3.1.2.1.2.2 declaring and clearing the ds2 ais condition it a given m12 demux declares a ds2 ais condi- tion, then it will do so by setting bit 2 (ds2 ais sta- tus), within the corresponding ds2 framer status register to 1. an illustration of bit 4 being set to 1, within the ds2 # 1 framer status register, is pre- sented below. n ote : the m12 demux will also generate a change in ds2 ais condition interrupt, if it detects or clears the ds2 ais condition. when the m12 demux ceases to declares the ds2 ais condition, then it will set this bit-field back to 0, in order to reflect normal operation. ds2 # 1 framer status register (address = 0xa3) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00010000 ds2 # 1 framer status register (address = 0xa3) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000010 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 354 n ote : the locations of the remaining ds2 framer status register (for the remaining m12 demux blocks) are at address locations 0xa4 through 0xa9. 5.3.1.2.1.2.3 declaring and clearing the ds2 ferf condition it a given m12 demux declares a ds2 ferf condi- tion, then it will do so by setting bit 3 (ds2 ferf sta- tus), within the corresponding ds2 framer status register to 1. an illustration of bit 3 being set to 1, within the ds2 # 1 framer status register, is pre- sented below. n ote : the m12 demux will also generate a change in ds2 ferf condition interrupt, if it detects or clears the ds2 ferf condition. when the m12 demux ceases to declares the ds2 ferf condition, then it will set this bit-field back to 0, in order to reflect normal operation. n ote : the locations of the remaining ds2 framer status register (for the remaining m12 demux blocks) are at address locations 0xa4 through 0xa9. 5.3.1.2.2 e1 (itu-t g.747) operation the user can configure m12 demux # 1 to operate in the itu-t g.747 mode by setting bit 4 (m12 g.747) to 1 and bit 5 (m12 by-pass) to 0, within the m12 ds2 # 1 configuration register, as illustrated below. once the user implements this configuration setting then m12 demux # 1 will be configured to operate in the itu-t g.747 mode. when m12 demux # 1 is operating in the itu-t g.747 mode, then it will be configured to accept a g.747 data stream, from the m23 demux block, and then de-multiplex this signal into three (3) e1 signals. m12 demux # 1 will then output this signal (via the rxds1data_0 through rxds1data_2 output pins). m12 demux # 2 will output this demultiplexed data upon the rising edges of rxds1clk_0 through rxds1clk_2. configuring the remaining m12 demux blocks the remaining m12 demux blocks (e.g., m12 de- mux block numbers 2 thorugh 7) can also be config- ured to operate in the e1 mode, by setting bit 4 (m12 g.747) to 1 and bit 5 (m12 bypass) to 0, within each of their corresponding m12 ds2 configu- ration registers (address locations: 0x1b through 0x20). 5.3.1.2.2.1 additional roles of the m12 demux blocks - e1 mode as the m12 demux block accepts the ds2 data stream and de-multiplexes it into 3 e1 signals, the m12 demux block will also do the following. ? it will acquire and maintain g.747 synchronization (via the fas pattern). if the m12 demux were to fail to maintain g.747 frame synchronization, then it will declare a g.747 oof condition. ? it will also detect and declare a g.747 ais and g.747 ferf condition. ds2 # 1 framer status register (address = 0xa3) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00001000 m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w xx0 1xxxx ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 355 ? it will detect and flag the occurrences of fas bit errors. ? it will detect and flag the occurrences of p bit errors. 5.3.1.2.3 ds2 pass-thru mode operation the user can configure m12 demux # 1 to operate in the ds2 pass-thru mode by setting bit 4 (m12 g.747) to 0 and bit 5 (m12 bypass) to 1 within the m12 ds2 # 1 configuration register, as illustrated below. once the user implements this configuration setting, then m12 demux # 1 will be configured to operate in the ds2 pass-thru mode. when m12 demux # 1 is operating in the ds2 pass-thru mode, then it will be configured to accept a ds2 signal from the m23 demux. afterwards, m12 demux # 1 will simply output this signal via the rxds1data_3 output pin. in this case, the m12 demux will perform no pro- cessing on this ds2 signal. configuring the remaining m12 demux blocks the remaining m12 demux blocks (e.g., m12 de- mux block numbers 2 thorugh 7) can also be config- ured to operate in the ds2-pass thru mode, by set- ting bits 4 (m12 g.747) to 0 and bit 5 (m12 bypass) to 1, within each of their corresponding m12 ds2 configuration registers (address locations: 0x1b through 0x20). 5.3.1.2.3.1 additional roles of the m12 demux blocks - ds2 pass-thru mode as the m12 demux block accepts the ds2 data stream it will also do the following. ? it will acquire and maintain ds2 synchronization (via the f and m bits). if the m12 demux were to fail to maintain ds2 frame synchronization, then it will declare a ds2 oof condition. ? it will also detect and declare a ds2 ais and ds2 ferf condition. ? it will detect and flag the occurrences of f and m bit errors. 5.3.1.2.3.1.1 declaring and clearing the ds2 oof condition it a given m12 demux declares a ds2 oof condi- tion, then it will do so by setting bit 4 (ds2 oof sta- tus), within the corresponding ds2 framer status register to 1. an illustration of bit 4 being set to 1, within the ds2 # 1 framer status register, is pre- sented below. n ote : the m12 demux will also generate a change in ds2 oof condition interrupt, if it detects or clears the ds2 oof condition. when the m12 demux ceases to declares the ds2 oof condition, then it will set this bit-field back to 0, in order to reflect normal operation. n ote : the locations of the remaining ds2 framer status register (for the remaining m12 demux blocks) are at address locations 0xa4 through 0xa9. 5.3.1.2.3.1.2 declaring and clearing the ds2 ais condition it a given m12 demux declares a ds2 ais condi- tion, then it will do so by setting bit 2 (ds2 ais sta- tus), within the corresponding ds2 framer status register to 1. an illustration of bit 4 being set to 1, within the ds2 # 1 framer status register, is pre- sented below. m12 ds2 # 1 configuration register (address = 0x1a) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved 7 reserved 6 m12 bypass m12 g.747 m12 g.747 res m12 ferf m12lbcode[1:0] r/w r/w r/w r/w r/w r/w r/w r/w xx1 0xxxx ds2 # 1 framer status register (address = 0xa3) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00010000 XRT72L13 ? ? ? ? m13 multiplexer/clear channel ds3 framer ic rev. p1.0.6 preliminary 356 n ote : the m12 demux will also generate a change in ds2 ais condition interrupt, if it detects or clears the ds2 ais condition. when the m12 demux ceases to declares the ds2 ais condition, then it will set this bit-field back to 0, in order to reflect normal operation. n ote : the locations of the remaining ds2 framer status register (for the remaining m12 demux blocks) are at address locations 0xa4 through 0xa9. 5.3.1.2.3.1.3 declaring and clearing the ds2 ferf condition it a given m12 demux declares a ds2 ferf condi- tion, then it will do so by setting bit 3 (ds2 ferf sta- tus), within the corresponding ds2 framer status register to 1. an illustration of bit 3 being set to 1, within the ds2 # 1 framer status register, is pre- sented below. n ote : the m12 demux will also generate a change in ds2 ferf condition interrupt, if it detects or clears the ds2 ferf condition. when the m12 demux ceases to declares the ds2 ferf condition, then it will set this bit-field back to 0, in order to reflect normal operation. n ote : the locations of the remaining ds2 framer status register (for the remaining m12 demux blocks) are at address locations 0xa4 through 0xa9. 5.3.2 channelized operation, while the XRT72L13 is operating in the c-bit parity fram- ing format. 5.4 d iagnostic o perations - c hannelized m ode 5.4.1 m12 mux (ds1 or e1) loop-backs 5.4.2 m23 mux (ds2 or g.747) loop-backs 5.5 c hannelized m ode i nterrupts ds2 # 1 framer status register (address = 0xa3) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00000010 ds2 # 1 framer status register (address = 0xa3) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused ds2 cofa status ds2 oof status ds2 ferf status ds2 red alarm status ds2 ais status ds2 resv status r/o r/o r/w r/w r/w r/w r/w r/w 00001000 ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 357 package dimensions ordering information p art #p ackage o perating t emperature XRT72L13iq 208 pin pqfp -40c to +85c ? ? ? ? XRT72L13 m13 multiplexer/clear channel ds3 framer ic preliminary rev. p1.0.6 358 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2001 exar corporation datasheet april 2001. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revisions rev. 1.0.4 modified pin description, sect 1 and sect 3. rev. 1.0.6 added electrical tables missing from previous version. |
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